Chapter 2 Layout Design Rules

- Layout Design Rules

- Definition of Layout Rules
- Stick Diagram
- Euler Path
- CMOS Inverter Layout

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 Layout Design Rules

™ a prescription for preparing the photomasks that are used in the

fabrication of integrated circuits.
™ a set of specification for the mask patterns used in the layout and
provide geometry information such as the minimum width and
spacing for each layer.
™ provide a necessary communication link between circuit designer
and process engineer during the manufacturing phase.
™ obtain the circuit with optimum yield in an small a geometry as
possible without compromising reliability of the circuit

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 Layout Design Rules

‰ Compromise between performance and yield

™ the more conservative the rules are, the most likely it is that the
circuit will function.
™ the more aggressive the rules are, the greater the probability of
improvements in circuit performance, this improvement may be at
the expense of yield.

The design rules primarily address two issues :

1. The geometrical reproduction of features that can be reproduced by

the mask masking and lithography process.
2. The interaction between different layers.

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 Physical Basic of Design Rules

™ limitation of lithography
™ physics of the process flow
™ electrical characteristics of the final structure

Minimum line width

™ limitation on the lithographic resolving power.

™ if the line width are made too small, it is possible for the to be
discontinuous.

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 Minimum Spacing
™ lines on a given layer also tend to originate form the lithography
™ if the wire are placed two close, it is possible for them to merge
together.
™ lines on different layers : restriction arises because the layers
must be stacked to form devices
™ spacing between lines of different layers are chosen to
compensate for misalignment or registration errors in the layering
process, thus a registration tolerance must be allowed.

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 Active Area Definition in a LOCOS Process

™ active area encroachment induced by the

formation of the bird’s beak requires that
the nitride mask dimensions be layer than
the final active area.

Poly gate overhang distance

™ ensure that the source/drain region

will be separated in the event of a
misalignment between the active
area and the poly mask.

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 Implant in a Depletion-Mode MOSFET

™ The implanted region must be large

than the device active area to ensure
that it misalignment occurs.

Well rules

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 Well Rules

™ the well is usually a deeper implant compared width the transistor

source/drain implant, therefore it is necessary for the outside
dimension to provide sufficient clearance between the n-well and
the adjacent different region.
™ the inside clearance is determined by the transition of the yield
oxide across the well boundary, “ bird’s beak ” effect.
™ to avoid shorten condition, active region is not permitted to across
a well boundary.
™ sheet resistance of well is about several kΩ/□, it is necessary
thoroughly contact the well to VDD or VSS, this will prevent
excessive voltage drops due to substrate current.

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 Transistor Rules

™ where poly crosses active, the source and drain diffusion is

masked by the region, the source, drain, and channel are
therefore self-aligned to the gate.

™ poly is necessary to extend beyond the edges of the diffusion

region to the drain and source will not be shorted.

™ poly and active region that do not meet intentionally to form a

transistor should be kept separated.

™ two of implant/diffusion layers to form the p- and n-transistor.

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 Contact Rules

• metal to p-active (p-diffusion)

• metal to n-active (n-diffusion)
• metal to polysilicon
• VDD and VSS substrate contacts
• split (substrate constant)

™ depending on process, “buried contact” (poly-diffusion) maybe

allowed. Ex : NMOS process, SRAM process.
™ each isolated well must be tied to the appropriate supply voltage.
™ the split or merge (butting) contact is equivalent to two separate
metal-diffusion contacts that are strapped together with metal.

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 Layout Design Rules
Guard Ring
p+ diffusion in the p-substrate (p-well) and n+ diffusion in the n-well
are used to collect injected minority carriers. n+ guard rings tied to
VDD. p+ guard rings tied to VSS.

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 Metal1 rules

™ metal spacing may vary with the width of the metal line (so-called
fat-metal riles), this is due to etch characteristics of small versus
large metal wires.
™ some process require a certain proportion of the chip area to be
covered with metal.

Via rules

™ process may vary in whether they allow via to be placed over poly
and diffusion.
™ some process allow via to be placed within these areas but not
allow the via to straddle the boundary of poly or diffusion, this
results from the sudden vertical topology variations that occur at
sublayer boundaries.

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 Metal2 rules

™ the possible increase in width and separation of 2nd level metal are
conservative rules to ensure against broken conductor or shorts
between adjoining wire due to vertical topology.
™ modern processes frequency have the metal1 and metal2
pitches identical.

Via2 rules
™ similar to 1st via, the rules for placement of via2 may vary with
process.

Metal3 rules
™ the rules usually but not always increase in width and separation over
metal2.
™ metal3 is generally need primarily for power-supply connections and
clock distribution.

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 Passivation or overglass
™ this is a protective glass layer that covers the final chip,
™opening are required at pads and any internal test points.

Definition of the layout layers

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 “Line of Diffusion” Rule

™ The transistors from a line of diffusion intersected by polisilicon gate

connections.
™ The CMOS circuit is converted to a graph where
(1) The vertices in the graph are the source/drain connections.
(2) The edges in the graph are transistors that connect particular
source-drain vertices.
™ Two graphs, one for the n-logic tree and one for the p-logic tree
result.
™ The connection of edges in the graph mirror the series-parallel
connection of gate signal name for that particular transistor.

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 N-Well
Cross-Sectional & Layout View

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 Thin Oxide
Cross-Sectional & Layout View

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 Ploy
Cross-Sectional & Layout View

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 P+ Implant
Cross-Sectional & Layout View

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 N+ Implant
Cross-Sectional & Layout View

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 Contact
Cross-Sectional & Layout View

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 Metal-1
Cross-Sectional & Layout View

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 Via1
Cross-Sectional & Layout View

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 Metal-2
Cross-Sectional & Layout View

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 Technology Parameters for Typical Case

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 DNW (deep N-Well definition)

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 Seal Ring Rule

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