Here is your 12-week (3-month) weekly study planner for starting from zero knowledge in ASIC

Design, tailored for a 4th-year ECE student. You can continue deepening each topic in the following 3
months with projects and interview prep.

ASIC Design Weekly Study Planner (12 Weeks)

Weekly Commitment: 2 hours/day (14 hrs/week)

Week 1 – Digital Logic Basics

• Number systems, Boolean algebra, K-maps

• Combinational circuits: MUX, DEMUX, Encoder, Decoder

• Sequential circuits: Flip-flops, Latches

Practice:

• Truth tables and Boolean expressions

• Draw timing diagrams

Resources: Neso Academy, GATEBook

Week 2 – Verilog HDL: Basics

• Verilog module structure

• Data types, Operators

• Always blocks, Initial blocks

Practice:

• Write Verilog code for AND, OR, MUX

• Simulate on EDA Playground

Week 3 – Verilog: Combinational Circuits

• RTL coding style

• Conditional and case statements

• Assign statements

Projects:

• 4-bit adder/subtractor
• Priority Encoder

• 8x1 multiplexer

Week 4 – Verilog: Sequential Circuits

• Flip-flops (D, T, JK)

• Counters, Shift registers

• FSM Design

Projects:

• 4-bit Up/Down counter

• Traffic light FSM

Week 5 – Testbenches & Simulation

• Writing Verilog testbenches

• $display, $monitor, $dumpvars

• Waveform analysis

Tasks:

• Create TBs for Week 3/4 designs

• Debug using waveforms

Week 6 – Advanced Verilog + Projects

• Blocking vs Non-blocking

• Tasks and Functions

• Parameterized modules

Mini Project:

• 8-bit ALU with testbench

Week 7 – ASIC Design Flow Overview

• RTL → Synthesis → P&R → GDSII

• RTL Design Guidelines

• What is netlist, DRC, LVS

Week 8 – Synthesis & Constraints

• Synthesis basics (Design Compiler overview)

• SDC constraints (clocks, input delay, output delay)

• Combinational vs Sequential paths

Task:

• Study sample SDC file

• Map RTL modules to gates (conceptual)

Week 9 – Static Timing Analysis (STA)

• Setup/Hold time, Slack

• Clock skew, jitter

• Timing exceptions: false path, multicycle

Task:

• Solve paper-based timing diagrams

• Read STA report formats

Week 10 – Design for Timing + Pipelining

• Critical paths

• Retiming and pipelining

• Clock domain crossing basics

Projects:

• Pipelined 4-bit multiplier

• Clock synchronizer design

Week 11 – Mini Projects + Debugging

• UART Protocol implementation (RTL + TB)

• Finite State Machine: Elevator controller

• Review timing paths manually

• Build your resume (project-focused)

• Solve 20+ common interview Qs:

o Verilog tricky questions

o FSM, synthesis, STA

• Mock Interviews or peer reviews

Resources:

• vlsiq.com

• asics-world.com

Deliverables After 12 Weeks:

• Verilog portfolio with 4–5 RTL projects

• Good understanding of ASIC design flow

• Ready-to-apply resume for internships/fresher roles

• Clear with STA and synthesis basics

Would you like me to generate this plan as a Notion template or Excel sheet you can check off
daily/weekly?
Here's a Daily 6-Month (180-Day) ASIC Design Learning Plan tailored for a 4th-year ECE student with
zero prior knowledge. It breaks everything into 2-hour daily tasks covering digital design, Verilog,
ASIC flow, synthesis, STA, and final project + interview prep.

Phase 1: Foundations (Days 1–30)

Goal: Master Digital Design + Start Verilog

Day Range Focus Area

1–7 Number systems, Boolean algebra, logic gates

8–14 Combinational circuits: MUX, decoders, encoders, adders

15–21 Sequential circuits: flip-flops, latches, counters, FSM

22–30 Verilog basics: modules, data types, operators, always blocks

Hands-On:

• Write gates, mux, adder in Verilog

• Simulate using EDA Playground

Phase 2: Verilog RTL Design (Days 31–60)

Goal: Write synthesizable RTL + testbenches

Day Range Focus Area

31–40 Combinational Verilog: ALU, priority encoder, case/if

41–50 Sequential Verilog: counters, shift registers, FSMs

51–60 Testbench writing, $monitor, waveform debugging

Mini Projects:

• 4-bit ALU with TB

• Traffic light controller FSM

Phase 3: ASIC Design Flow (Days 61–90)

Goal: Understand complete ASIC flow and start synthesis concepts

Day Range Focus Area

61–70 ASIC flow: RTL → GDSII, design stages overview

71–80 RTL coding for synthesis, logic optimization

81–90 Synthesis basics, SDC constraints (clocks, delay)

Tasks:

• Review tool logs (DC or Genus if available)

• Write sample SDC files

Phase 4: STA & Timing Closure (Days 91–120)

Goal: Learn STA, setup/hold, clocking issues

Day Range Focus Area

91–100 Setup, hold, slack, combinational/sequential paths

101–110 Clock skew, jitter, clock domain crossing

111–120 Timing exceptions: false path, multi-cycle path

Practice:

• Timing diagram problems

• Analyze sample timing reports

Phase 5: Design Techniques & Pipelining (Days 121–150)

Goal: Tackle advanced RTL design, retiming, pipelining

Day Range Focus Area

121–130 FSM design (Moore vs Mealy), multi-module design

131–140 Pipelining: deep vs shallow, stages

141–150 Power + area optimization in RTL

Projects:

• UART controller (transmit/receive logic)

• Pipelined multiplier

Phase 6: Projects + Resume + Interview Prep (Days 151–180)

Day Range Focus Area

151–160 Resume writing, GitHub setup, project documentation

161–170 VLSI interview questions (Verilog, synthesis, timing)

171–180 Mock interviews, HR Qs, final revision

Final Projects:

• UART design + TB

• Elevator FSM

• ALU with pipelined stages

Daily Format (Example)

Time Task

0–30 min Watch/Read theory (YouTube, book, course)

30–90 min Hands-on coding or practice

90–120 min Simulation, review waveforms, write notes

Would you like me to deliver this as a PDF, Excel tracker, or Notion template so you can follow and
check it off daily?