• Initiated by the U.S.

Department of Defense in 1983, standardized in 1987 (IEEE

CPE 15 – Lesson 1 – Introduction to Digital Logic Design 1076).
Digital Circuit Primarily consist of interconnected transistors • HDLs initially used for documentation and simulation.
Hierarchical Structure: Logic Synthesis:
Transistors → Organized into logic gates. • IBM pioneered automated logic synthesis in the 1970s.
Logic gates → Combined into adders, registers, timing modules. • Synopsys (founded in 1986) integrated synthesis with HDLs, enabling direct
Registers → Grouped into memory banks. translation of HDL descriptions into hardware.
Simplifies design and analysis of complex systems (e.g., CPUs). Major Milestones In The Advancement Of Digital Logic And HDLS
• Digital circuit design advanced rapidly over 25 years with integrated circuits (ICs). 1854: George Boole creates a two-valued algebraic framework.
• Early SSI (Small Scale Integration) chips had few gates per chip 1859: Augustus DeMorgan adds two powerful "Laws" to Boole's framework.
• MSI (Medium Scale Integration) allowed hundreds of gates per chip. 1930: Claude Shannon applies Boolean Algebra to the design of electrical switching
• LSI (Large Scale Integration) enabled thousands of gates per chip, increasing complexity. circuits.
• Automation needs led to Computer-Aided Design (CAD) techniques. 1947: William Shockley, et al., file a patent for the first transistor while working for Bell
Schematics Visual diagrams of interconnected components. Intuitive but Labs.
impractical for highly complex designs. 1954: Maurice Karnaugh creates the K-map as a graphical way to minimize logic circuits.
Hardware Description Languages (HDLs): 1959: Jack Kilby and Robert Noyce file patents for the integrated circuit within six months
• Textual languages for clear and concise digital design representation. of each other.
• Similar to programming languages but describe hardware, not software. 1964: Texas Instruments releases the first TTL Logic Family (7400) based on bipolar
• Used for structure, behavior, and timing of digital circuits (e.g., processors, CPUs). transistors.
• Enable simulation and verification of circuits. 1968: RCA releases the first CMOS Logic Family (CD4000) based on MOSFET transistors.
What is HDL? 1971: The first single-chip microprocessor is released (Intel 4004) containing 2300
Digital Circuit Notations: transistors.
Developed to capture logical behavior at various abstraction levels. 1978: IBM creates logic synthesis algorithm to design mainframe computers.
Examples: Boolean equations, timing charts, state transition tables, schematics, HDLs. 1983: Verilog HDL development begins.
Hardware Description Languages (HDLs): 1986: Synopsys is founded, integrating synthesis with HDLs.
Popular HDLs: 1987: VHDL is released and standardized by IEEE in 1987 (IEEE 1076).
• Verilog HDL and VHDL are industry standards (IEEE). 1995: IEEE releases the first open Verilog standard "IEEE 1364".
• Widely used for large-scale digital system design. 2012: Intel releases the 10-core Xeon Westmere EX microprocessor containing 2.5 billion
Advantages of HDLs: transistors
• Replace schematics for large designs. Why HDL?
• Support logic simulation at multiple abstraction levels. • Logic circuits scale quickly, making manual design difficult.
• Allow high-level design and verification before detailed implementation. • Transition from high-level descriptions (e.g., truth tables) to implementation
Origin of Hard Description Language (e.g., minimized logic diagrams) is well-defined.
• Driven by increasing complexity in digital circuit design. Challenges in Design Complexity:
• Integrated circuit invented in 1959 by Jack Kilby and Robert Noyce. • Early designs used simulation for blocks of ~100 transistors.
• First microprocessor (Intel 4004) introduced in 1971, containing 2300 transistors. • Breadboard testing and manual layout were common.
Key Inventions and Contributions: • VLSI (Very Large Scale Integration) enabled chips with >100,000 transistors,
• Jack Kilby filed the first IC patent in 1959, winning the Nobel Prize in 2000. making breadboard verification impossible.
• Robert Noyce filed a similar patent and co-founded Intel in 1968. Role of CAD Tools:
• Gordon Moore predicted transistor doubling every 2 years (Moore’s Law). • Critical for verification and design of VLSI circuits.
Challenges in Digital Design: • Automated placement, routing, and logic simulation became essential.
• Schematics became cumbersome for large designs. Top-Down Design Approach:
• Word descriptions were too massive and ineffective. • Scalable across logic families.
• Need for standardized documentation and compatibility among manufacturers. • HDLs support automated synthesis, converting functional descriptions (e.g.,
Development of HDLs: truth tables) into gate-level circuitry.
• Verilog developed in 1983, standardized by IEEE in 1995 (IEEE 1364).
• Allows designers to focus on system behavior rather than manual synthesis
steps.
 3. Synthesis Create the gate-level connection (schematic or netlist) of the design
using logic synthesis processes (e.g., K-maps or automated CAD tools).
Benefits of HDL 4. Technology Select the logic technology that will achieve the specifications (e.g.,
Timing Analysis HDLs provide designers with the ability to analyze the timing behavior Mapping 74HC family, 32nm CMOS ASIC). Manipulate the gate-level
of digital circuits and ensure that the circuits meet the timing netlist/schematic into a form that is suitable for this technology (e.g.,
requirements. DeMorgan's NAND/NOR).
Design HDLs provide a way to design reusable components that can be used for 5. Place and Arrange the components to minimize the area needed (on a board or
Reusability multiple circuit designs, reducing time and effort, which improves Route chip). Wire all connections to minimize interconnect length and
overall design quality. crossings.
Optimization HDLs provide a way to optimize the design of digital circuits for 6. Verification Once a technology is chosen and the routing is complete, the gate and
performance. wiring delays can be used to estimate whether the final design meets
Circuit Design It provides a way to design digital circuits that meet the required the timing and power consumption requirements of the original
specifications. specifications.
Simulation HDLs help the designer to test, debug, and verify the digital circuit 7. Fabrication Once the design is verified, it can be implemented (ASIC, programmable
before it is built through waveforms. device, board-level, discrete parts).
Verification HDLs provide designers with the ability to verify the functionality of the
digital circuit by testing it against different inputs and ensuring that the
circuit functionality is correct and meets the desired functionality.
Synthesis HDLs can be used to synthesize digital circuits. Synthesis is a process of
automatically generating circuits from HDL code that represents the
design in terms of hardware components for physical implementation.
Levels of Abstraction
HDLs were originally defined to be able to model
behavior at multiple levels of abstraction. Abstraction is
an important concept in engineering design because it
allows us to specify how systems will operate without
getting consumed prematurely with implementation
details. Also, by removing the details of the lower level
implementation, simulations can be conducted in
reasonable amounts of time to model the higher-level
functionality.

Modern Design Flow

The modern design flow based on HDLs includes the ability to simulate functionality at each
step of the process. Functional simulations can be performed on the initial behavioral
description of the system. At each step of the design process the functionality is described
in more detail, ultimately moving toward the fabrication step. At each level, the detailed
information can be included in the simulation to verify that the functionality is still correct
and that the design is still meeting the original specifications.
Steps and Description of Tasks at Each Step
1. Specifications State the desired behavior of the design using broad, high-level
specifications.
2. Functional Describe the high-level architecture of the design (e.g., block diagrams
Design for inputs/outputs, sub-systems). Define generic behavior using tools
such as truth tables, state diagrams, and/or algorithms.
 MODERN DESIGN FLOW Level Four More complex functional logic units: Microprocessors.
- Third IC level (VLSI)
Level Five Complex systems, functional units from levels two through four:
Systems that integrate multiple functional units like
microprocessors, memory, and I/O controllers.

CPE 15 – Lesson 2 – Review of Logic Circuits

Number System A mathematical way of representing set of values using digits or
symbols. It uniquely represents a number and helps perform
mathematical operations.
Base/Radix Number of unique symbols within its set. The definition of a number
system includes both the symbols used and the relative values of each
symbol with it. It is the number of numerals in the number system
Binary Number uses digits 0 and 1, called bits. Eight bits make a byte, which computers
System (Base 2) and digital devices use to store data. This is fundamental in computing
because it is easily implemented in electronic circuits using logic gates.
Each binary digit is referred to as a bit."
Signed They represent both positive and negative values. The most significant
Numbers bit (MSB) is the sign bit: 0 for positive and 1 for negative. The number
of bits is fixed, ensuring the sign bit stays in the same position. There are
several encoding methods for negative numbers, but modern
computers exclusively use two's complement.
Decimal It consists of digits 0 to 9 with a base of 10. Here, the first few successive
Number System places to the left of the decimal point represent units, tens, hundreds,
(Base 10) and thousands. It is commonly used in everyday life."
Levels of Integration Octal number It uses digits 0 to 7 with a base of 8, making it fewer than the decimal
Small-scale Several independent gates (<10) per package. Basic digital system (Base 8) system. It’s used in computers alongside binary
Integration (SSI) functions. Hexadecimal It uses sixteen digits and alphabets t includes numbers 0 to 9, as in the
Medium-scale Between 10-100 gates per chip. Perform basic digital functions, Number System decimal number system, and alphabets A to E with a base of 16. Here,
Integration (MSI) e.g., 4-bit addition. (Base 16) the letters A to E represent numbers from 10 to 15. This is also used in
Large-scale Between 100 and a few thousand gates per chip. Implement more computers to reduce the large string size of binary numbers.
Integration (LSI) complex functions. 1’s One simple way to encode negative numbers is by flipping all the bits of
Very Large-scale Integration (VLSI) Complement the positive equivalent (1's to 0's and 0's to 1's). This process is called
Several thousands to over 100 million transistors per chip, e.g., complex microprocessors. complementing. The most significant bit remains the sign bit (0 for
Not Feasible Anymore: Breadboarding, Manual layout design. positive, 1 for negative), while the other bits represent the number.
Modern Approaches: Simulator programs, Automatic place-and-route. Bottom-Up Design: 2’s is an encoding scheme that fixes the double zero issue in signed
Design small building blocks, Combine them to develop bigger ones, More and more Complement magnitude and 1's complement. To get a negative number, flip all bits
emphasis on logic simulation. of the positive equivalent and add 1. The most significant bit is the sign
Related Tools: - CAD (Computer-Aided Design) CAD vs. CAE (Computer-Aided Engineering) bit (0 for positive, 1 for negative), and negative numbers are shifted to
Logic and circuit simulators Prototyping on a breadboard eliminate the double zero gap. Taking the two's complement of a
Layout by hand on paper or a computer terminal positive number gives its negative counterpart, and vice versa.
Level One Electronic components: Transistors, diodes, resistors, capacitors. Logic Circuits
- Components level Logic Gate/ is a digital circuit that performs basic binary functions. When analyzing
Level Two Functional logic units: Basic logic gates (NOT, AND, NAND). Gate its operation, we treat inputs and outputs as ideal 1's and 0's, ignoring
- First IC level (SSI) details like voltage or transistors. This abstraction simplifies designing
Level Three Functional logic units: Adders, counters, multiplexers. complex logic circuits without delving into hardware specifics.
- Second IC level (MSl and LSI)
Logic Symbol It is a graphical representation of a circuit, showing how components
interface. Basic logic gates have unique symbols, while complex circuits
use rectangular symbols. Inputs are typically on the left, and outputs on
the right.
Truth Table formally defines a logic circuit's functionality. It lists every possible input
combination and the corresponding output. For a circuit with n inputs,
there are 2^n possible input codes. These codes are listed in ascending
binary order, starting from 0, allowing each row to be assigned a decimal
equivalent for easy reference
Logic Level In digital systems, Positive Logic assigns HIGH to 1 and LOW to 0, while
Negative Logic assigns HIGH to 0 and LOW to 1, defining how logic levels
map to binary codes."
Logic It graphically shows how a circuit's output relates to its inputs over time.
Waveform It mimics real-world measurements, like those from an oscilloscope,
where signals are either 1 or 0. For clarity, logic values are often labeled
at each transition point."
Logic is an equation that provides the functionality of each output as a
Function/Logic function of the inputs. Logic operations for basic gates use symbolic
Expression operators (e.g., +, -, ·). It describes the operations needed to produce
the outputs in the truth table. It describes a single output that can only
be 1 or 0. For circuits with multiple outputs, this is needed for each.
Input variables are included in the expression, just as an analog function.
Logic Family a group of parts that adhere to common specifications so they work
together. It has a specific name, and once specifications are agreed
upon, manufacturers produce these parts. They share the same power
supply requirements and DC input/output specifications, allowing them
to communicate successfully when connected directly
 CPE 15 – Lesson 3 – Modern HDLs 10. Scientific Example: Particle accelerators, telescopes, and laboratory instruments.
Purpose of HDLs Research and Application: HDLs develop control systems and signal processing
Simulation The inputs are applied to a module and the outputs are checked to Instrumentation circuits for scientific instruments, enabling precise measurements and
verify that the module operates correctly data acquisition.
Synthesis The textual description of a module is transformed into logic gates. It VHDL It was originally developed in 1981 by the Department of Defense to
transforms HDL into a netlist code hardware; e.g., logic gates and the describe the structure and function of hardware. Its roots draw from
wires connecting them. The logic synthesizer may perform the Ada programming language.
optimizations to reduce the amount of hardware required. It is utilized in electronic design automation to express mixed-signal systems, such as ICs
Netlist It may be a text file, or it may be displayed as a schematic to help (integrated circuits) and FPGA (field-programmable gate arrays). We can also use VHDL as
visualize the circuit. a general-purpose parallel programming language. We utilize VHDL to write text models
Real Life Application of HDLs that describe or express logic circuits. If the text model is part of the logic design, the model
1. Consumer Example: Smartphones, tablets, and wearable devices. is processed by a synthesis program. The next step in the process incorporates a simulation
Electronics Application: HDLs are used in designing the processors, memory units, program to test the logic design. During this step, we utilize the simulation models to
and various control circuits within these devices, ensuring efficient and characterize the logic circuit that interfaces to the design.
reliable operation. SystemC addresses the need for a system design and verification language that
2. Automotive Example: Advanced Driver Assistance Systems (ADAS), engine control spans hardware and software. It is a language built in Standard C++ by
Industry units, and infotainment systems. extending the language with the use of class libraries
Application: HDLs create control systems for collision detection, engine The language is particularly suited to model system partitioning, to evaluate and verify the
performance, and infotainment, improving safety and efficiency. assignment of blocks to either hardware or software implementations, and to architect and
3. Aerospace Example: Avionics systems, communication systems, and radar measure the interactions between and among functional blocks. Leading companies in the
and Defense systems. intellectual property (IP), electronic design automation (EDA), semiconductor, and software
Application: HDLs design control systems for aircraft, spacecraft, and industries currently use SystemC to deliver high-performance hardware blocks at various
military equipment, ensuring accurate navigation, communication, and levels of architectural exploration.
defense. SystemVerilog This is the 2005 revision of Verilog, is the latest publication of the
4. Medical Example: MRI and CT scanners, patient monitoring systems. standard. We call the IEEE Verilog standard document the Language
Devices Application: HDLs develop electronic circuits for medical imaging and Reference Manual (LRM). Currently, the standard defines the PLI
diagnostics, enabling precise signal processing and detailed image (Programming Language Interface). In general, Verilog lacks the
generation. advanced constructs needed for large-scale system verification. It is an
5. Example: Routers, switches, and network equipment. extension of Verilog, and was developed to address these limitations by
Telecommuni- Application: HDLs design high-speed data processing systems for adding features for more complex design and verification tasks.
cations efficient routing and switching of data across telecommunication It includes object-oriented programming (OOP) concepts, enhanced data types, assertions,
networks. and interfaces for better abstraction and reusability. SystemVerilog also integrates
6. FPGA Example: Prototyping and specialized computing solutions. verification constructs like random stimulus generation and functional coverage, which
Programming Application: HDLs program FPGAs for applications like signal streamline the testing and debugging of hardware designs. As a result, SystemVerilog is
processing, cryptography, and hardware acceleration. preferred in modern, large-scale projects, especially for verification environments, whereas
7. Automated Example: Programmable Logic Controllers (PLCs), robotics, and Verilog is typically used for simpler, smaller-scale designs.
Manufacturing automation systems. WHICH ONE SHOULD YOU CHOOSE?
and Industrial Application: HDLs create control systems for manufacturing The choice between VHDL and Verilog depends on your project requirements:
Automation equipment, assembly lines, and robotics, ensuring precise and efficient - Choose VHDL if you need a reliable, maintainable, and portable design for mission-critical
production. applications.
8. Example: Application-Specific Integrated Circuits (ASICs), custom chips. - Choose Verilog if speed, simplicity, and compatibility with commercial tools are priorities.
Semiconductor Application: HDLs are used in the design and verification of ASICs, For many modern projects, SystemVerilog (an extension of Verilog) offers enhanced
Industry which are customized for specific functions or applications. features that bridge the gap between VHDL and Verilog
9. Networking Example: Data center switches, load balancers, and network
and Data appliances.
Centers Application: HDLs design specialized hardware components for data
processing, routing, and switching in data center environments.
Parameters Verilog VHDL architecture architecture_name of entity_name
Definition Verilog is a hardware VHDL is a hardware description architecture_declarative_part;
description language used for language used to describe digital begin
modeling electronic systems. and mixed-signal systems. Statements;
Introduced Verilog is a newer language as VHDL is an older language as it was end architecture_name;
it was introduced in 1984. introduced in 1980. 3. Configuration 4. Package declaration 5. Package body
Language Verilog is based on the C VHDL is based on Ada and Pascal VHDL CODE OF LOGIC OPERATIONS
language. languages.
AND GATE OR GATE
Difficulty Verilog is easier to learn. VHDL is comparatively harder to
learn.
Types of Modern HDLs
1. VHDL Mostly used in government and defense applications.
Has a somewhat complex syntax.
2. Verilog Most widely used HDL in industry.
Syntax is closer to C than VHDL, but still quite different.
3. SystemC A newer HDL built directly on top of C++.
Designed for system-level modeling (very high level).
4. An extension of Verilog that incorporates some features of VHDL.
SystemVerilog Includes some of the higher-level features of SystemC.
5. Chisel Based on Scala.
Provides powerful capabilities with functional programming. NOT GATE NAND GATE
- Ideal for creating parameterized hardware, such as RISC-V cores.
6. MyHDL Based on Python.
Allows high-level hardware description and generates traditional HDLs
(Verilog/VHDL).
Great for rapid prototyping and easier integration with software tools.
7. Bluespec Based on Haskell.
Known for its formal verification features and rule-based modeling.
Offers strong guarantees on correctness, making it useful for safety-
critical systems.
Describing a Design
In VHDL an entity is used to describe a hardware module An entity can be described using:
1. Entity It defines the names, input output signals and modes of a hardware
declaration module. It should start with ‘entity’ and end with ‘end’ keywords. The
direction will be input, output or inout. NOR GATE XNOR GATE
SYNTAX
entity entity_name is
Port declaration;
end entity_name;
In Port can be read.
Out Port can be written.
Inout Port can be read and written.
Buffer Port can be read and written, but it can have only one source.
2. Architecture It can be described using structural, dataflow, behavioral or mixed style.
It must specify the entity name for which we are writing its body.
statements should be inside the ‘begin’ and ‘end’ keyword.
Architecture may contain variables, constants, or component declaration.
declarative part
 CPE 15 – Lesson 4 – Introduction to Verilog (Using Logic How it works: Uses built-in Verilog gate primitives.
A digital element such as a flip-flop can be represented with combinational gates like Gates) Also known as Structural Level Modeling
NAND and NOR. The functionality of a flip-flop is achieved by the connection of a certain SWITCH LEVEL The lowest level, defining behavior using transistors (PMOS & NMOS).
set of gates in a particular manner. How the gates have to be connected is usually figured (Transistor- Uses nmos and pmos to model actual semiconductor behavior.
out by solving K-map from the truth table. The truth table is nothing but a table that tells Based)
us what inputs combine together to give what values of output. Verilog Design It describes a single system in a single file. The file has the suffix *.v.
Hardware It is a diagram that shows how the combinational gates should be Within the file, the system description is contained within a module.
Schematic connected to achieve a particular hardware functionality All behavior code should be described within the keywords module and endmodule. The
Black-Box This block provides us with certain inputs and outputs that is similar to module includes the interface to the system (i.e., the inputs and outputs) and the
the hardware schematic made up of combinational gates. If we know description of the behavior. The design code would mostly follow the given template:
what values of inputs contribute to make the output have a value of 1, 1. Module definition and port list declaration
then hide the internal details of the connections and encapsulate it. 2. List of input and output ports
Circuit It is the most common and widely practiced method of verification. The 3. Declaration of other signals using allowed Verilog data types
Simulation output of the design is then checked against expected values to see if 4. Design may depend on other Verilog modules, and hence their instances are created by
the design is functionally correct. module instantiations.
All simulations are performed by EDA (Electronic Design Automation) software tools and 5. The actual Verilog design for this module that describes its behavior.
the Verilog design RTL is placed inside an entity.
Testbench This is where various tests provide different stimuli to the design.
Verilog
- It is used to describe digital systems and circuits in the form of code.
- It was developed by Gateway Design Automation in the mid-1980s and later acquired by
Cadence Design Systems.
- It is widely used for design and verification of digital and mixed-signal systems, including
both application-specific integrated circuits (ASICs) and field-programmable gate arrays
(FPGAs).
- It supports a range of levels of abstraction, from structural to behavioral, and is used for
both simulation-based design and synthesis-based design.
- The language is used to describe digital circuits hierarchically, starting with the most basic
elements such as logic gates and flip-flops and building up to more complex functional
blocks and systems. The code shown describes the behavior of a D-type flip-
- It also supports a range of modeling techniques, including gate-level, RTL-level, and flop. The first few lines declare a new module called dff
behavioral-level modeling.
and define the input and output ports. The only other
- It creates a level of abstraction that helps hide away the details of its implementation and signal used in this design is q and is declared next. Since
technology. this is a simple design, it does not depend on any other
- It helps us to focus on the behavior and leave the rest to be sorted out later.
module, and hence there are no module instantiations.
Design It refers to the different levels of detail at which a hardware system can
Abstraction be described. These facilitate the design process by allowing designers
Layers to focus on specific aspects of the system without getting bogged down
by lower-level details.
Types of Description/Modeling Styles in Verilog
Behavioral What it is: Describes what the circuit should do without worrying about
Level (High- how it's implemented. always It is the block describes how the hardware should behave during certain
level, How it works: Uses always blocks, if-else, case statements, etc. events and hence is behavioral code.
Algorithmic) - It is the highest level of description testbench It is the Verilog container module that allows us to drive the design with
Dataflow Level What it is: Describes how data moves through logical expressions. different inputs and monitor its outputs for expected behavior. It is
(Using Boolean How it works: Uses assign statements and Boolean equations denoted by tb_*. These signals are then assigned certain values and are
Equations) eventually driven as inputs to the design.
Gate Level What it is: Describes the design using logic gates (AND, OR, NOT).
- Verilog syntax is similar to C in that it uses a stream of tokens
Lexical tokens They are the basic building blocks of Verilog code, such as keywords,
identifiers, and operators. They are like a way of communicating with
the language and are useful for constructing Verilog statements and
expressions
Lexical Tokens
- Module Declaration - White Space - Comments - Numbers
- Operators - Strings - Identifiers and Keywords - Data Types
Every line in Verilog should end with a semicolon (;). Verilog is case-sensitive, meaning
var_a and var_A are treated as different identifiers.
Ports They are a set of signals that act as inputs and outputs to a particular
module and are the primary way of communicating with it. They are like
pins and are used by the design to send and receive signals from the
outside world. Each needs to have a user-defined name, a direction, and
a type. The user-defined names are case-sensitive and must begin with
an alphabetic character.
Port Declarations
The port directions are declared to be one of the three types: input, output, and inout. A
port can take on any of the previously described data types, but only wires.
Input – The module can only receive values from outside
Output – The module can only send values from the outside
Inout – The design module can send or receive values
Wire – ports are by default considered as nets of type.
Signed – it is attribute can be attached to a port declaration or a net/reg declaration or
both. Implicit nets are by default unsigned.
Module It represents a design unit that implements certain behavioral
characteristics and will get converted into a digital circuit during
synthesis.
Any combination of inputs can be given to the module, and it will provide a corresponding
output. This allows the same module to be reused to form bigger modules that implement
more complex hardware.
Whitespace It is a term used to represent the characters for spaces, tabs, newlines,
and formfeeds, and is usually ignored by Verilog except when it
separates tokens. In fact, this helps in the indentation of code to make
it easier to read.
If a number is simply entered into Verilog without identifying syntax, it is treated as an
integer. However, Verilog supports defining numbers in other bases. Verilog also supports
an optional bit size and sign of a number. When defining the value of arrays, the “” can be
inserted between numerals to improve readability. The “” is ignored by the Verilog
compiler. Values of numbers can be entered in either upper or lower case (i.e., z or Z, f or
F, etc.). The syntax for specifying the base of a number is as follows
<size_in_bits>’<base><value>
Note that specifying the size is optional. If we didn't mention the size in Verilog, the number
will takes default size of 32-bit vector in decimal number system notation with leading zeros
added as necessary. The supported bases are as follows
 CPE 15 – Lesson 5 – Verilog Basics Verilog Value Sets
Verilog HDL 0 Logic zero, or false condition.
- is a hardware description language (HDL) used to model electronic systems. The language 1 Logic one, or true condition.
supports the design, verification, and implementation of analog, digital, and mixed-signal X Unknown or uninitialized.
circuits at various levels of abstraction. Z High impedance, tri-stated, or floating.
- It was invented at Automated Integrated Design Systems (later renamed as Gateway Verilog Data Type Declarations
Design Automation) in 1985 as a hardware modeling language. Gateway Design Automation 1. Nets They are used to connect between hardware entities like logic gates and
was later purchased by Cadence Design Systems in 1990. hence do not store any value on its own. Nets/Signals are declared as
- Only a subset of the language can be synthesized “wires”.
Module Functionality wire It is most popular and widely used net in digital designs of type. It is a
Structural modeled as a netlist of module instances or primitive instances. connect Verilog data-type elements and used to connect nets that are
Behavioral modeled with procedural blocks or continuous assignment statements. driven by a single gate continuous assignment. It is similar to the one used
Dataflow modeled with the assign keyword, how data flows from input to output to connect two components on a breadboard.
- Combination of any of the above 2. Variable On the other hand, is an abstraction of a data storage element and can hold
Verilog Lexical Conventions values. A flip-flop is a good example of a storage element.
White Space Characters – Spaces, Tabs, Carriage return, Newline, Formfeeds and EOF (end- a. reg A Verilog data-type that can be used to model hardware registers since it
of-file) can hold values between assignments.
Syntax Elements - List separator: , Statement terminator: ; Variables are declared as "reg". Note that reg (register) is not necessarily a hardware
register.

b. integer a general purpose variable of 32-bits wide that can be used for other
purposes while modeling hardware and store integer values.
c. time This variable is unsigned, 64-bits wide and can be used to store simulation
quantities for debugging purposes.
d. realtime A variable that simply stores time as a floating point quantity.
e. real A variable that can store floating point values and can be assigned the same
way as integer and reg.
f. or constant, is useful for representing a quantity that will be used multiple
parameter times in the architecture.
Syntaxes

integer count; // Count is an integer value

time end_time; // end_time can store a time value like 5ns
realtime rtime; // rtime = 48.25ps
real float; // float = 12.344 - can store floating numbers
parameter <type> constant_name = <value>;
- The type is optional and can only be integer, time, real, or realtime. If a type is provided,
the parameter will have the same properties as a variable of the same type If the type is
excluded, the parameter will take on the type of the value assigned to it.
parameter BUS_WIDTH = 64;
parameter NICKEL = 8'b0000_0101;
 Binary appear between two operands.
Scalar A net or reg declaration without a range specification is considered 1-bit wide
operators
Vector If a range is specified, then the net or reg becomes a multibit entity
Ternary have two separate operators that separate three operands.
Note that the msb and lsb should be a constant expression and cannot be substituted by a
operators
variable. However, they can be any integer value - positive, negative or zero - and the lsb
Examples:
value can be greater than, equal to or less than the msb value.
a = ~b; // ~ is a unary operator. b is the operand
Bit-select It is any bit in a vectored variable can be individually selected and assigned a
a=b && c; // && is a binary operator. b and c are operands
new value
a=b?c:d;// ? is a ternary operator. b, c and d are operands
Verilog Operators
1. Assignment It has two parts - right-hand side (RHS) and left- hand side (LHS) with an
Operators equal symbol (=) or a less than-equal symbol (<=) in between.
The left-hand side (LHS) of the assignment is the target signal. The right-hand side (RHS)
contains the input arguments and can contain both signals, constants, and operators.
a. Blocking represented by the = operator, execute sequentially. Each assignment
Assignment must complete before the next one begins. This sequential behavior
resembles traditional programming languages and is ideal for modeling
combinational logic in Verilog.
variable = expression;
Key Characteristics:
- Executes statements in the order they are written.
- Blocks subsequent statements until the current assignment is complete.
- Typically used inside procedural blocks such as always or initial.
b. Non- represented by the <= operator, allow parallel execution. The right-hand
Strings
- are stored in reg variables, and the width of the reg variable must be enough to hold it. blocking side (RHS) of the assignment is evaluated immediately, but the actual
assignment assignment to the left-hand side occurs later, at the end of the time step
- Each character in a string represents an ASCII value and requires 1 byte. If the size of the
variable is smaller than the string, then Verilog truncates the leftmost bits of the string. variable <= expression;
- If the size of the variable is larger than the string, then Verilog adds zeros to the left of the Key Characteristics:
string. - Enables concurrent execution of statements.
- The LHS value is updated after all RHS evaluations in the current time step.
- Commonly used in sequential logic (e.g., flip-flops, registers).
2. Bitwise These operators perform logic functions on individual bits. Operation on
Operators a bit-by-bit basis. Result bit length is the widest operand's length
Narrower operands are right-aligned and zero extended.

Verilog Building Blocks

1. Strings Sequence of characters enclosed with double quotation. Ex.: “Hello
World!”
2. Identifiers Name of variables, must follow specific rules. Ex.: integer var_a;
3. Keywords Reserved words with special meanings. Ex.: module, input, output
Operators perform an operation on operands. They are similar to those in the C
programming language. They return a True/False result will return a 1-bit
value where 1 is True, 0 is False, and X is indeterminate.
Operands They may be either net or register data types. They may be scalar, vector,
or bit selects of a vector.
Unary precede the operand.
operators
 3. Reduction uses each bit of a vector as individual inputs into a logic operation and 7. Conditional can be used to provide a more intuitive approach to modeling logic
Operators produces a single bit output. Operator statements. The keyword for the conditional operator is ? with the
following syntax: cond_expr ? true_expr : false_expr
8. Multi-bit Verilog wires and variables can be clubbed together to form a
Concatenation multi-net wire or variable using _________{ and } separated by commas.
Operators It is also allowed to have expressions and sized constants as operands
in addition to wires and variables.

4. Shift Operators 9. Replication It provides the ability to replicate a vector or non-negative number which
Operators cannot be x or z. This uses double curly brackets (i.e., {{}}) and an integer
indicating the number of replications to be performed. The syntax is as
follows: {<number_of_replications>{<vector_name_to_be_replicated>}}

10. Equality Operators

5. Logical or returns a value of TRUE (1), FALSE (0) or UNKNOWN (x) based on logic
Boolean operation of the input operations. These operations are used in decision
Operators statements.

11. Arithmetic Operators

6. Relational These operators return a value of TRUE (1) or FALSE (0) based on a
Operators comparison of two inputs. If either of the operands is X or Z, then the
result will be X.
 Digital Logic Circuits
Combinational Logic Circuit
- the output at any given time depends only on the current inputs, not on past states.
- are made from basic logic gates like AND, OR, and NOT or from universal gates like NAND
and NOR. These gates are connected together to create more complex circuits.
- not dependent upon previous input to generate any output,
- they are fundamental in performing tasks like arithmetic operations, data routing and
comparison.
Arithmetic and Logic Functions - Adders Subtractors Comparators
Data Transmission – Multiplexers, Demultiplexers, Encoders, Decoders
Code Converters – Binary BCD
Output determined solely by inputs
Output = f(inputs)
Sequential It differs from combinational logic in that its output depends on both
Logic Circuit the current inputs and its previous states. This means the devices have
memory, storing part of their "history" to influence future outputs.
Main Parts of Sequential Logic Circuit
Memory Typically flip-flops, made up of a combination of logic gates that store
Elements the circuit's state.
Combinational Generates the excitation inputs to the memory elements and produces
Logic the required outputs based on both current inputs and the stored state
Types of Sequential Logic Circuit
1. Asynchronous Sequential Circuit 2. Synchronous Sequential Circuit
 Categories of Combinational Logic Circuit Aspect Combinational Circuit Sequential Circuit
1. Arithmetic These circuits perform mathematical or logical operations, such Definition Output depends only on current Output depends on current inputs
/Logical Functions as addition subtraction or comparison inputs. and past states (memory).
2. Data Transmission These circuits are used for routing and controlling data flow Memory Does not require memory Requires memory elements (flip-
between different parts of a system ensuring proper data Elements elements. flops, latches).
transfer Timing Output is immediate upon input Output depends on clock pulses
3. Code Converters These circuits convert data from one format or code to another Dependency changes. and previous states.
Examples of Combinational Circuit Functionality Performs logical operations Performs operations requiring
1. Multiplexers (MUX) Used to select one input from multiple sources. without sequence dependency. sequences/timed events.
2.Demultiplexers Used to distribute one input to multiple outputs. Examples Adders, Subtractors, Multiplexers, Counters, Shift Registers, Flip-
(DEMUX) Encoders. Flops, State Machines.
3. Encoders Convert multiple input signals into a smaller number of outputs. Power Generally lower power Higher due to memory and clock
4. Decoders Convert binary information from encoded inputs to a specific Consumption consumption. circuitry.
output. Applications Tasks requiring direct logical Sequential operations (e.g.,
5. Half Adder and Full Perform binary addition. operations (e.g., arithmetic). counters, registers).
Adder
6. Half Subtractor and Perform binary subtraction.
Full Subtractor Full Adder Code
7. ALU (Arithmetic Performs logical and arithmetic operations.
Logic Unit) module full_adder (
8. Parity Generators Used in error detection in digital communication. input wire a,
and Checkers input wire b,
Types of Sequential Circuit input wire cin,
Synchronous In these circuits, the memory contents change only at specific output reg sum,
Sequential Circuits times, triggered by clock transitions. Since the operation of the output reg cout
circuit is controlled by a clock, these circuits are also known as );
clocked sequential circuits. always @ (a or b or cin) begin
Asynchronous In these circuits, the output can change at any time as a result {cout, sum} = a + b + cin;
Sequential Circuits of changes in the inputs. The memory elements used are delay- end
type, and the circuit can be considered a combinational circuit endmodule
with feedback. D-Flip Flop
Examples of Sequential Circuit
Flip-Flops Basic memory storage elements. 2 to 1 Multiplexer module d_flip_flop (
Registers Store multiple bits of data for processing. module mux2to1 ( input clk, // Clock input
Counters Used for counting applications. input wire sel, input reset, // Asynchronous active-high reset
Shift Registers Used in data serialization and deserialization. input wire in0, input d, // Data input
Finite State Machines Control units in processors and automation systems. input wire in1, output reg q // Output
(FSMs) );
output reg out
Memory Units Store and retrieve data.
);
Timers and Clocks Generate precise time delays and clock pulses. always @(posedge clk or posedge reset) begin
Control Units in Direct the operations of the processor. if (reset) begin
always @(*) begin q <= 1'b0; // Reset the output to 0 when reset is high
Microprocessors
if (sel == 1'b0) end else begin
out = in0; q <= d; // On rising clock edge, pass input d to output q
else end
out = in1; end
end
endmodule endmodule