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Adders and Subtractors

The experiment involves designing a half adder, full adder, half subtractor, and full subtractor using Verilog code and testing them with the Xilinx simulation tool. The objective is to verify the functionality of these designs against their truth tables through various input combinations. The document includes source codes for each component and test benches for simulation.

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8 views8 pages

Adders and Subtractors

The experiment involves designing a half adder, full adder, half subtractor, and full subtractor using Verilog code and testing them with the Xilinx simulation tool. The objective is to verify the functionality of these designs against their truth tables through various input combinations. The document includes source codes for each component and test benches for simulation.

Uploaded by

momis12444
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab Experiment-2

Title of the Experiment:


To design adder and subtractor using Verilog code and compare with
their respective truth tables.

Objective:
In this lab, a half adder, full adder, half subtractor and full
subtractor are designed. The objective will be to test these designs
on Xilinx simulation tool. The tests will be performed for all the
possible combinations of inputs to verify their functionality.
Moreover, the knowledge gained will be used to design much larger
and complex logic designs.

Equipment required:

● Xilinx Vivado Design Suite 2016

Logic diagram(s):
Half Adder:
Logic Diagram and Truth Table:
Source codes:
Half Adder:
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
xor x1(sum,a,b);
and a1(carry,a,b);
endmodule
Half Subtractor:
module halfsub(diff, borrow, a, b);
output diff;
output borrow;
input a;
input b;
wire abar;
xor x1(diff,a,b);
not n1(abar,a);
and a1(borrow,abar,b);
endmodule

Full Adder:
module full_adder(sum, carry, a, b, c);
output sum; output carry;
input a;
input b;
input c;
wire s1,t1,t2;
xor x1(s1,a,b);
xor x2(sum,s1,c);
and a1(t1,a,b);
and a2(t2,s1,c);
or o1(carry,t1,t2);
endmodule

Full Subtractor:
module fullsub(diff, borrow, a, b, c);
output diff;
output borrow;
input a;
input b;
input c;
wire abar,q,r,s;
xor x1(diff,a,b,c);
not n1(abar,a);
and a1(q,abar,b);
and a2(r,abar,c);
and a3(s,b,c);
or o1(borrow,q,r,s);
endmodule

Test Bench:
For Half Adder and Half Subtractor:
Module ha_tb(); // change accondely
Reg a,b;
Wire S,c;
Ha dut(a,b,S,c);
Initial
begin
a=0 ; b=0;
#10 a=0 ; b=1;
#10 a=1 ; b=0;
#10 a=1 ; b=1;
# 10 $finish;
endmodule

For Full Adder and Full Subtractor:


Module fa_tb(); // change accordingly
Reg a,b;
Wire S,c;
Ha dut(a,b,S,c);
Initial
Begin
a=0 ; b=0; c=0;
#10 a=0 ; b=0; c=1;
#10 a=0 ; b=1; c=0;
#10 a=0 ; b=1; c=1;
#10 a=1 ; b=0; c=0;
#10 a=1 ; b=0; c=1;
#10 a=01; b=1; c=0;
#10 a=1; b=1; c=1;
#10 $finish;
endmodule

Result:
Full Adder:
Full Subtractor:

Half Adder:
Half Subtractor:

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