BEC602 VLSI Design and Testing

MODULE 5

I- Sequential MOS Logic Circuits

a) Introduction

b) Behaviour of Bistable Elements (Excluding

Mathematical analysis)

c) SR Latch Circuit

d) Clocked Latch and Flip-Flop Circuits, Clocked

SR Latch, Clocked JK Latch

Introduction

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• In combinational logic circuits, the output levels at any given time point are directly

determined as Boolean functions of the input variables applied at that time.

• Thus, the combinational circuits lack the capability of storing any previous events, or displaying

an output behavior which is dependent upon the previously applied inputs. There is no memory

of past inputs.

• Circuits of this type are also classified as non-regenerative circuits, since there is no feedback

relationship between the output and the input.

In contrast, sequential logic circuits, in which the output is determined by the current inputs as

well as the previously applied input variables. This type of circuit has memory.

• Figure below conceptually shows a sequential circuit composed of a combinational logic block

and a memory element connected in a feedback loop.

• The feedback in sequential circuits gives rise to regenerative behavior, allowing them to retain

state and thus act as memory elements.

• The critical components of sequential systems are the basic regenerative circuits, which can be

classified into three main groups:

• Bistable circuits ii) Monostable circuits iii) Astable circuits.

• The general classification of non-regenerative and regenerative logic circuits is shown in the

figure below:

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Behavior of Bistable Elements

• A bistable circuit is a fundamental digital building block with two stable states.

• It is widely used in memory elements such as latches, flip-flops, and registers.

• The basic bistable element consists of two identical cross coupled inverter circuits, as shown

in the figure (a).

Fig(a) : Cross coupled inverters

In this configuration:

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• Output of Inverter 1 is connected to the input of Inverter 2

• Output of Inverter 2 is connected to the input of Inverter 1

Thus, we have:

• In order to investigate the static input-output behavior of both inverters, we start by plotting

the voltage transfer characteristic of inverter (1) with respect to the Vo1 – Vi1, axis pair. Notice

that the input and output voltages of inverter (2) correspond to the output and input voltages

of inverter (1), respectively.

• Consequently, we can also plot the voltage transfer characteristic of inverter (2) using the

same axis pair, as shown in Fig.(a).

• The intersection points indicate possible operating points of the circuit.

• There are three intersection points. Two of them are stable

• One is unstable Stability analysis:

• At stable points: inverter gain < 1 ⇒ small disturbances decay.

• At the unstable point: inverter gain > 1 ⇒ disturbances are amplified.

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Energy Landscape Analogy:

• The bistable nature of a cross-coupled inverter circuit can be understood not only through

voltage transfer characteristics but also through a qualitative analysis of the total potential

energy levels at different operating points refer figure (b).

• The circuit exhibits three possible operating points:

• Two stable operating points, One unstable Operating point

• At the two stable points, the total potential energy is at a minimum.

• This occurs when the voltage gains of both inverters are approximately zero.

• At the intermediate operating point, the potential energy is at a maximum.

• Here, both inverters exhibit maximum voltage gain, making the system highly sensitive to

small perturbations.

• A small disturbance at the unstable point causes the system to transition into one of the two

stable states.

• This bistable energy profile explains why the cross-coupled inverter configuration is widely

used in digital memory circuits such as SR latches and flip-flops, which rely on having two

stable states to store binary information.

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CMOS Two-Inverter Bistable Element:

Figure below shows the circuit diagram of a CMOS bistable element constructed using two

cascaded CMOS inverters.

• These inverters are connected in a positive feedback loop —

the output of the first inverter is the input to the second, and vice versa.

• This configuration creates a system with two stable states and one unstable state.

• Unstable Operating Point: At the unstable operating point, both outputs are at an

intermediate voltage level. At this condition: All four transistors (2 NMOS and 2 PMOS) are in

saturation region.

• This results in the maximum loop gain of the system. The operating point is highly sensitive

to even the smallest perturbation.

• This point is referred to as a metastable state.

Behavior Under Perturbation:

• If the circuit is initialized exactly at the unstable point, any small voltage perturbation or

noise will move the system away from it. Due to the positive feedback:

• The small disturbance gets amplified.

• The outputs of the inverters diverge rapidly.

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• The system settles in one of two stable states (refer the figure shown below):

Figure: One possible time-domain response of the output voltages when the circuit is initially

biased at its unstable operating point.

• One output reaches VOH (logic high).

• The other output reaches VOL (logic low).

Polarity of Divergence:

• The direction in which each output voltage diverges is determined by the

initial perturbation polarity.

For example:

• If the output of inverter 1 is slightly higher than that of inverter 2, it will rise further toward

VOH. Consequently, the output of inverter 2 will fall toward VOL.

• This positive feedback ensures that the circuit acts as a memory element.

Key Takeaways:

• The CMOS two-inverter bistable element is fundamental to binary state storage.

• The metastable point is unstable and cannot retain a state in the presence of noise.

• Positive feedback ensures rapid convergence to a stable logic level.

• This circuit is the basis for SRAM cells, latches, and flip-flops.

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The SR latch circuit

• A bistable element constructed using two cross-coupled inverters has two stable operating

states.

• As long as a power supply is available, the circuit retains its current state, making it suitable for

memory storage.

• However, the simple two-inverter setup does not allow external control to change its state.

• Need for Triggering Inputs:

• To enable external control and allow a change of state, additional switching elements (inputs)

must be added.

• The resulting circuit is a CMOS SR Latch (see figure below), which includes: S-(Set) input

and the R-(Reset) input

• This circuit is often referred to as an SR latch/flip-flop, as it can toggle between two stable

states.

The SR latch circuit

• The SR latch is implemented using two CMOS NOR gates:

• Each NOR gate’s output is fed into one input of the other NOR gate (cross-coupling).

• The second input of each NOR gate is connected to the external control input (S or R).

• The gate-level schematic and its corresponding block diagram representation is shown below.

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• These figures clearly show how the SR latch structure supports both internal feedback and

external control via S and R inputs

The SR latch circuit

• The circuit provides two outputs: Q: Primary output, 𝑄̅ : Complement of Q

• By definition: Set state: Q = 1, 𝑄̅ = 0 Reset state: Q = 0, 𝑄̅ = 1

Operating Conditions:

• If S = 0 and R = 0: The latch holds its previous state (memory function).

• If S = 1 and R = 0: The latch is set; Q = 1, 𝑄̅ = 0. If S = 0 and R =1: The latch is reset; Q = 0, 𝑄̅ = 1.

• If S = 1 and R = 1: Both outputs go to 0, which violates the complementarity condition. This is a

forbidden or invalid state. The truth table of the NOR-based SR latch is summarized in the

following:

The SR latch circuit : Figure: CMOS SR latch circuit based on NOR2 gates

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Transistor-Level Operation of CMOS SR Latch:

• The operation of the CMOS SR latch circuit can be examined more closely by analyzing the

behavior of its four nMOS transistors: M1, M2, M3, and M4.

Case 1: S = VOH (1) , R = VOL (0)

• Transistors M1 and M2 (connected in parallel) are turned ON. This pulls node 𝑄̅ to logic-low

level, i.e., VOL.

• Transistors M3 and M4 are OFF, so node Q rises to logic-high level VOH .

• The latch is in the Set state.

Case 2: S = VOL, R = VOH

• Transistors M1 and M2 are OFF. Transistors M3 and M4 are turned ON.

• Node Q is pulled to VOL and node 𝑄̅ rises to VOH . The latch is in the Reset state.

• Case 3: S = VOL, R = VOL

• Both M1 and M4 (trigger transistors) are OFF. Depending on the previous state:

• Either M2 is ON → Q = VOL, 𝑄̅ = VOH

• Or M3 is ON → Q = VOL, Q = VOH

• The latch holds its previous state.

• The above analysis focuses only on the nMOS transistor network.

• For simplicity, the operating states of the complementary pMOS transistors are not explicitly

listed.

• The static operation modes and voltage levels of the NOR-based CMOS SR latch circuit are

summarized in the following table:

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Transient Analysis of CMOS SR Latch:

• To study dynamic behavior, we consider a switching event where the latch changes state. For

instance:

• Reset → Set: Applying S = 1, R = 0 , Set → Reset: Applying S = 0, R = 1

• In both cases, the outputs undergo opposite transitions:

One output rises from logic 0 to logic 1 The other falls from logic 1 to logic 0

• Coupled Behavior and Simplification:

• Ideally, simultaneous switching requires solving two coupled differential equations, which is

complex. Instead, we simplify by assuming:

The rise and fall occur sequentially, not simultaneously.

• This approximation results in a slight overestimation of switching time but provides useful

first-order analysis.

The SR latch circuit

• Capacitance at Output Nodes:

• The circuit diagram of the SR latch is shown in figure below together with the lumped load

capacitances at the nodes Q and ̅

𝑄

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• ̅ can be approximated as:

The total parasitic capacitance at nodes Q and 𝑄

Rise Time Estimation:

Assuming a transition from reset to set:

• τrise,Q(SR−latch) = τrise, Q (NOR2) + τfall, Q (NOR2)

• Assumptions: M1 turns ON ⇒ Q falls M3 turns OFF ⇒ Q rises

• M2 and M4 are OFF (although M2 might turn ON during transition, helping Q fall faster)

• This method avoids simultaneous differential equations and gives a simplified delay estimate.

Depletion-Load nMOS NOR-Based SR Latch:

• The NOR-based SR latch can also be implemented using two cross-coupled depletion-load

nMOS NOR2 gates, as shown in figure below:

• Depletion-Load nMOS vs. CMOS SR Latch: Logic Functionality:

• The logical behavior of the depletion-load nMOS NOR-based SR latch is identical to that of the

CMOS-based implementation.

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Implementation Comparison:

• CMOS Implementation:

• Offers better power efficiency.

• No static power dissipation while holding a state. Provides full output voltage swing between 0

and VDD .

• nMOS Depletion-Load Implementation:

• Logic works the same, but suffers from static power dissipation.

• Output levels may not reach full rail voltages.

NAND-Based SR Latch: Circuit Structure

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• It uses two NAND2 gates with cross-coupled feedback Inputs: S , R (active-low)

• Outputs: Q, 𝑄̅ . The truth table is shown below:

• NAND SR Latch Behavior:

• Comparison with NOR SR Latch: NAND latch is active-low triggered NOR latch is active-

high triggered

• CMOS NAND latch dissipates negligible static power

• NAND latch with depletion-load NMOS gates is possible, but CMOS offers better noise margins

and full output swing. The NAND-based SR latch can also be implemented by using two cross-

coupled depletion-load NAND2 gates, as shown in figure below:

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Figure: Depletion-load nMOS NAND-based SR latch circuit

Clocked Latch and Flip-Flop Circuits

Clocked SR Latch:

• In the previous section, we examined the behavior of the basic SR latch, which is an

asynchronous sequential circuit.

• These circuits respond to changes in their inputs at a time determined by internal circuit

delays. However, many digital systems require synchronous operation, where outputs change

only in response to a clock signal.

• Need for Clocked Latch:

• To ensure that the SR latch responds to inputs in a synchronized fashion, we introduce a gating

clock signal (CK). This clock restricts changes in the output to specific periods (when the clock

is active), enabling predictable and stable circuit behavior.

• The clock (CK) is typically a periodic square waveform. It is applied simultaneously to all

clocked logic gates in the system.

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• Inputs S and R affect the latch only during the active level of the clock.

Clocked NOR-Based SR Latch

• If CK = 0: The AND gates output 0 regardless of S and R, so the SR latch maintains its current

state.

• If CK = 1: The values of S and R propagate to the NOR-based SR latch, potentially altering its

state. If S = R = 1 during CK = 1:

• Both outputs of the latch go to 0 momentarily. When CK returns to 0, the state becomes

indeterminate, depending on circuit delay mismatches.

• To illustrate the operation of the clocked SR latch, a sample sequence of CK, S, and R

waveforms, and the corresponding output waveform Q are shown in figure below:

• The circuit is level-sensitive during CK = 1.

• Even narrow spikes or glitches in S or R during CK = 1 can trigger a change in state if the pulse

width exceeds loop delay.

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CMOS Implementation Using AOI Gates

Figure: AOI-based implementation of the clocked NOR-based SR latch circuit

• Uses AND-OR-Invert (AOI) gates for compact design. Reduces the total transistor count

compared to using two AND2 and two NOR2 gates

Clocked NAND-Based SR Latch (Active-Low Inputs):

Figure: Gate-level schematic of the clocked NAND-based SR latch circuit, with active low inputs

 Inputs S , R, and CK are all active low.

 If CK = 1: Inputs have no effect on the output (latch holds state).

 If CK = 0: Inputs S and R determine the next state: S = 0, R = 1 ⇒ Q = 1 (Set)

 S = 1, R = 0 ⇒ Q = 0 (Reset)

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Clocked NAND-Based SR Latch (Active-High Inputs):

Figure: Gate-level schematic of the clocked NAND-based SR latch circuit, with active high

inputs, and Partial block diagram representation of the same circuit.

 Inputs S , R, and CK are all active high. CK = 1, S = 1, R = 0 ⇒ Set

 CK = 1, S = 0, R = 1 ⇒ Reset

 CK = 0 ⇒ Latch holds current state.

 Higher transistor count compared to the active-low version.

Clocked JK Latch:

• All simple and clocked SR latch circuits discussed earlier suffer from a common drawback: they

have a not-allowed input combination.

• When both inputs (S and R) are activated simultaneously, the circuit enters an indeterminate

state. This issue can be resolved by adding feedback paths from the outputs to the inputs,

resulting in a new type of latch called the JK Latch, as shown in figure below.

Figure: Gate-level schematic of the clocked NAND-based JK latch circuit

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JK Latch: Structure and Working Principle:

 The JK latch enhances the basic SR latch by eliminating the forbidden input condition.

 It consists of an all-NAND gate structure with active-high inputs. The J and K inputs

correspond to the Set and Reset inputs of the SR latch, respectively.

 The latch responds to inputs only when the clock (CK) is active (CK = 1).

 It preserves its state when the clock is inactive (CK = 0).

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Toggle Mode and Clock Timing Constraint:

• While the JK latch resolves the undefined state issue of the SR latch, it introduces a new

potential problem:

• If J = K = 1 during an active clock pulse (CK = 1), the output toggles continuously.

• To avoid this, the clock pulse width must be less than the input-to-output propagation

delay.

• This ensures that only one toggle occurs per clock pulse. However this clock constraint is

difficult to implement for all practical applications.

• If this timing constraint is met, the JK latch toggles its state only once per clock cycle when

J = K = 1.

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• This version, as opposed to the all-NAND realization, presents the following

advantages:1) The circuit employs a CMOS realization with an AOI (AND-OR-Invert)

structure.

2) The AOI-based design results in a lower transistor count. Consequently,

the circuit becomes more compact and efficient.

3) The AOI realization of JK latch is shown in figure below:

Master-Slave Flip-Flop

• Most of the timing limitations encountered in the previously examined clocked JK latch circuits

can be prevented by using two latch stages in a cascaded configuration.

• The key operation principle is that the two cascaded stages are activated with opposite clock

phases. This configuration is called the master-slave flip-flop.

• The input latch in the figure is called the "master," is activated when the clock pulse is high.

• During this phase, the inputs J and K allow data to be entered into the flip-flop, and the first-

stage outputs are set according to the primary inputs.

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• When the clock pulse goes to zero, the master latch becomes inactive and the second-stage latch,

called the "slave,“ becomes active. The output levels of the flip-flop circuit are determined during

this second phase, based on the master-stage outputs set in the previous phase.

• Since the master and the slave stages are effectively decoupled from each other with the opposite

clocking scheme, the circuit is never transparent, i.e., a change occurring in the primary inputs

is never reflected directly to the outputs.

• This very important property clearly separates the master-slave flip-flop from all of the latch

circuits examined earlier in this section. Because the master and the slave stages are decoupled

from each other, the circuit allows for toggling when J = K = "1," but it eliminates the possibility

of uncontrolled oscillations since only one stage is active at any given time.

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• A NOR-based alternative realization for the master-slave flip-flop circuit is shown in the figure

below.

• The master-slave flip-flop circuit examined has the potential problem of "one's catching."

• When the clock pulse is high, a narrow spike or glitch in one of the inputs, for instance a glitch

in the J line (or K line), may set (or reset) the master latch and thus cause an unwanted state

transition, which will then be propagated into the slave stage during the following phase.

• This problem can be eliminated to a large extent by building an edge-triggered master-slave

flip-flop.

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II- Structured Design and Testing

 Introduction.

 Design Styles

 Testing

Introduction:

The design description for an integrated circuit may be described in terms of three domains:

1) The behavioral domain

2) The structural domain

3) The physical domain

• At the behavioral level, the freedom to choose a sequential or a parallel algorithm is

available.

• In the structural domain, the decision about which particular logic family, clocking strategy

or circuit style to use is initially unbound.

• At the physical level, how the circuit is implemented in terms of chips, boards and cabinets

also provides many options to the designer.

• These domains may be hierarchically divided into levels of design abstraction which included

the following:

1) Architectural or functional level 2) Register Transfer level 3) Logic level

4) Circuit level.

Figure(a) below illustrates a typical design flow of a contemporary design system

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Figure below illustrates an Ideal approach to design

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Design Styles

A good VLSI design system should provide descriptions in all the three description domains and at all

relevant levels of abstraction.

The design parameters may be summarized in terms of :

• Performance –speed, power, function

• Size of die

• Time to design-ease of use

• Ease of test generation and testability

Design is a continuous trade-off to achieve adequate results for all of the above parameters.

• The tools and methodologies used for a particular chip will be a function of these parameters.

Certain end results have to be met (chip must conform to performance specifications)

• But other constraints may be a function of economics(size of the die affecting yield) or even

subjectivity (one designer feels easy, other might find comprehensible)

• Given that the process of designing a system on silicon is complicated, the role of good VLSI

design aids is to reduce this complexity and assure the designer of a working product.

• A good method of simplifying the approach to a design is by the use of constraints and

abstractions.

• By using constraints the tool designer has some hope of automating procedures and taking

out ground work out of the design.

• Bu using abstractions, the designer can collapse details and arrive at a simpler concept with

which to deal.

Structured design strategies

• The primary aim of the Mead and Conway text was to allow system designers the option of

implementing high performance systems directly in silicon.

• Hence the complexity of designing an IC or complete system be reduced.

• Methods of dealing with complex design problems have been developed for large software

problems.

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• By adapting these to the IC design environment we not only can formulate methods to deal

with the apparent complexity of the IC design process to a beginner but also can propose

methods by which experts can cope with ever increasing complexity of designing circuits

with millions of devices.

• Some of the techniques to reduce the complexity of the IC design are:

• Hierarchy

• Modularity

• Regularity

• Locality

) Hierarchy

• Use of hierarchy involves dividing a module into submodules and then repeating this

operation on the submodules until the complexity of the submodules is at an appropriately

comprehensible level of detail.

• This is in parallel to the software case where large programs are split into smaller and

smaller sections until simple subroutines with well defined functions and interfaces.

• We can employ a parallel hierarchy in each domain to document the design.

For example , an adder may have a subroutine that models the behavior, the gate connection diagram

that specifies the structure and a piece of layout that specifies the physical nature of the adder for all

three domains

Composing the adder into other structures can proceed in parallel for all three domains with domain

to domain comparisons ensuring that the representations are consistent.

2) Modularity

• As the Hierarchy involves dividing a system into a set of submodules and if these modules

are well formed, the interaction with other modules can be well characterized.

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• The notion of well formed may differ from situation to situation but a good starting point are

those criteria placed on a “well formed” software subroutine.

• First of all a well defined interface is required which is an argument list with variable types in

the software case.

• In the case of ICs this corresponds to the well defined physical interface that indicates the

position, name, layer, type, size and signal type of external interconnections. For instance,

connection points may indicate the power and ground , inputs and outputs to a module.

• The function must also be defined in an unambiguous manner.

• Modularity helps the designer to clarify and document an approach to a problem and also

allows a design system to be of more utility by checking attributes of a module as it is

constructed.

• The ability to divide a task into set of well-defined modules also aids in a team design

where a number of designers have a portion of a complete chip to design.

• In structured programming, proponents advise the use of only three basic constructs.

• These are concatenation, iteration and conditional selection.

• In the IC design world these constructs have parallels.

For instance, concatenation is mirrored by cell abutment, where IC cells are connected by placing

them adjacent to each other and inter cell connections are formed on the common boundary.

• Iteration is handled in the IC case by one and two dimensional arrays of identical cells ,

typified by a memory. The use of conditional selection is typified in a Programmable

Logic Array(PLA), the function of which is determined by the location of transistors in

an array.

• When combined with the ability to parametrize designs, the above three programming

notions can greatly aid the designer in modularizing a design.

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3) Regularity

• The example of the use of regularity in an IC design is the use of iteration.

• However the extended use may be made of regular structures to simplify the design process.

Example : If one was constructing a “data path”, the interface between modules(power, ground, clocks,

busses) might be common but the internal details of modules may differ according to function.

• Regularity can exist at all levels of the design hierarchy .

• At the circuit level, uniform transistors might be used rather than the manual optimization of

each device.

• At the logic module level, identical gate structures might be employed.

• At higher levels one might construct architectures that use a number of identical processor

structures.

• By using regularity a design may be judged correct by construction and the methods for

formally proving the correctness of a design may also be aided by regularity.

4) Locality

• By defining well-characterized interfaces for a module, we are effectively stating that the

other internals of the module are unimportant to any exterior interface.

• In this way, we are performing a form of “information hiding” that reduces the apparent

complexity of that module.

• In the software world this is paralleled by the reduction of global variables to a minimum( to

zero).

• Using this model, we would not physically overlay connections to physical module, as this may

modify the internal structure and operation of a defined module.

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• Modules can also be located to minimize the global wiring that may be necessary to

connect a number of modules in an unstructured system.

• Common theme nowadays is “wires first, then modules” rather than” place modules then route

them together”.

• Handcrafted mask layout

• Handcrafted mask layout is the term applied to less constrained design techniques that

involve, at some stage , the layout of functional subsystems at the mask level.

• This is the oldest form of chip design and still the most widely used by semiconductor

vendors. This essentially requires that a design be divided among designers with expertise

in logic, circuit and process details. By attending to each transistor and optimizing layout

and circuit parameters , the highest performance and smallest die size results.

• As total freedom is allowed at the physical level, the structural specification and hence the

behavioral description may differ from that required.

• This hampered mask level layout before the advent of adequate circuit extraction tools.

• The circuit extraction tools take a mask description as input and then, by various

recognition techniques, presents the designer with the circuit description that corresponds to

the interrelationship of the mask shapes present.

• Gate Array Design

• Gate arrays are currently popular as an LSI-VLSI implementation medium.

• This arises through a combination of readily available vendors, design tools and a

compatibility with TTL design that makes it easy for the system designer to transfer design

to silicon with the minimum amount of effort.

• The cost of the gate array is potentially lowest of all the methods for certain classes of

integrated circuits.

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• The widespread availability of design tools is a result of the strictly constrained physical

layout which may not reduce the complexity of the tools required but gives a bounded

problem.

• Gate arrays come in various flavors but is categorized by a design that uses a large number of

identical “sites” . Each site consisting of a number of circuit elements

Gate Array Design(Contd..)

• In CMOS the sites consist of a number of n-transistors and p-transistors

• Some typical sites are shown below:

The first site structure shows a typical six transistor site composed of three n-transistors and

three p-transistors. The gate signals are connected in common and the n and p transistors are

connected as shown in the site schematic. A sketch of the layout is shown below:

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Second site structure is shown below:

This has four transistors. One n-p pair has a common gate connection , while the other pair has

separate gate signals. This allows the easy implementation of a transmission gate and inverter as

might be used in the latches.

Third site structure is as shown:

In the above structure , there are six transistors ratioed in a particular manner to allow the static latch

connection shown. This is one of the two types of cell used on this particular array catering for memory

structures .

The final cell is shown below: A continuous array of transistors has been used with metal completely

programming the cell.

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• The predefined topology allows a vendor to stockpile wafers processed to a given

fabrication step and then “personalize” a set of wafers to implement a given design.

• This personalization can be completed in a number of ways.

• The possible methods are:

 Single layer metal

 Single layer metal and contacts

 Double layer metal and contacts and vias

• For a given design the mask cost is a function of the normal cost.

• This also saves time in reducing a design to practice.

• The trade-off in a gate array is wasted chip area, all the transistors for a given array have to

be in place whether they are used or not.

• Other factors that lead to sub-optimum area usage arise from the fixed circuit configurations

that may be realized.

• Example: If RAM or ROM is to be included, the vendor has to estimate a good ratio of memory

to logic.

• A typical gate array for plan is as shown:

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• Arrays of sites are separated by channels.

• Strict directional control is maintained over routing(metal mostly horizontal, polysilicon

vertical ). Mask programmable IO cells surround the inner core.

• A six transistor CMOS site is shown in circuit schematic form

• In the above example , the site is programmed by metal internal to the cell(between the

power rails).

• Connection to the cell would be via vertical metal and horizontal polysilicon runners .

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• Typical design decisions in a gate array include transistor sizing, selection of the width of

the routing channel and placement and nature discrete wiring.

• A typical flowchart used in the IGC-200000D gate array product is as shown next.

1) The customer is responsible for creating a logic schematic and a set of test vectors which are used

initially to verify the customer’s logic.

2) The logic schematic is then converted to CMOS gate array macros of the type shown”

3) After simulation , the CMOS cells are placed on the appropriate array and automatically routed .

4) Any necessary revisions are communicated to the customer and this procedure is repeated until

an acceptable CMOS implementation is found.

5) Final placement and routing precedes a final simulation with all parasitics .

6) The array is then manufactured and tested with a customer-generated test vector set.

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Standard Cell Design

• Standard cell systems rely on a set of predefined logic/circuit cells to complete a design.

• The attraction to the TTL designer is also present as in gate-array design , as the cells can be

organized to follow a TTL data book.

• Complexity of cells can vary from SSI-type component such as gates and latches, to

MSI/LSI-type components such as RAMs, ROMs and PLAs.

• A full mask set is required for normal standard cell chips although design trade-offs may be

made. For instance one might design a chip than can be used for a number of applications by

personalizing a control PLA or ROM that is part of a larger custom chip.

• In comparison to gate array design , standard cell design systems use cells with predefined

layout and logic which can be placed anywhere in the area defining the chip.

• A typical standard cell floor plan for a chip designed with standard cells is shown in the figure

below:

• MSI type cells are placed in rows separated by routing channels.

• These rows are then arranged in columns. In addition, large LSI functional blocks (RAM) may

be located to optimally connect with the random logic.

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• MSI cells are often of fixed height with variable length catering for circuits of differing

complexity as shown in the figure (a) below:

• This layout strategy is representative of mature standard cell systems.

• Recently systems have been proposed and implemented that hierarchically group primitive

cells together to form larger blocks and then combine these on up to the complete chip

description.

• A skeleton cell layout is shown in the figure (b), with power rails running horizontally in first

layer metal and I/O connections running vertically in polysilicon or second layer metal.

• The I/O access to cells may vary, with a variety of methods shown in the figure ( c )

Testing- Introduction:

• Need to incorporate methods of testing circuits is a critical factor in all LSI and VLSI design.

• The task of Testing should proceed concurrently with any architectural considerations and not

to be left until fabricated parts are available.

• Figure below shows a combinational circuit with n-inputs.

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To test the above circuit exhaustively a sequence of 2n inputs (or test vectors) must be applied and

observed to fully exercise the circuit. This combinational circuit is converted to a sequential circuit

with addition of m-storage latches as shown in the figure (b)

The state of the circuit is determined by the inputs and the previous state . A minimum of 2n+m test

vectors must be applied to exhaustively test the circuit

Example: With LSI, a network with N=25 and M=50 , then 275 patterns which is approximately 3.8 X

1022 . If one had to apply those at the rate of 1microseconds per pattern, the time taken would be over

a billion years !

The design techniques for testing includes three main areas :

1) Test generation

2) Test verification

3) Design for test

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4) Test generation relates to the problems of the generation of a minimum number tests to

verify the behavior of a circuit and the goodness of a given percentage of internal nodes.

5) The problem of test verification is concerned with finding measures of the effectiveness of a

given set of tests. This is commonly gauged by performing “fault simulations”

6) Design for test is the task of designing circuits from the outset so that the previous two

methods are limited in magnitude.

7) In relation to test generation, test inputs to verify functionality are generally supplied by the

designer.

Example : Consider a variety of programs that run on a microprocessor if the MP was the device under

test. The other form of tests are those applied by the manufacturer to verify a certain percentage of

good internal circuit nodes prior to shipping parts.

• Here we examine some of the models used to model faults relevant to CMOS

• A commonly used fault model is called the “stuck-At” model, With this model, a faulty gate

input is modelled as a Stuck-At-0 (S-A-)) or Stuck-At-1(S-A-1) value.

• When a certain number of vectors are applied to a network , the percentage fault coverage is

often quoted. This is the number of S-A-0 or S-A-1 faults that could be detected by the input

sequence as a percentage of the total number of single faults that might occur.

• Not all failures that occur can be modelled by the S-A-0 and S-A-1 models.

• Many faults are caused by short-or open-circuited networks.

Consider the faults shown in the figure below:

• It can be seen that the short S1 is modelled by a S-A-0 fault at input A, while short S2 modifies

the function of the gate.

• To ensure good modelling, faults should be modelled at the transistor level as at this level the

complete circuit structure is known.

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• It can be seen that the short S1 is modelled by a S-A-0 fault at input A, while short S2 modifies

the function of the gate.

• To ensure good modelling, faults should be modelled at the transistor level as at this level the

complete circuit structure is known.

• In the case of a simple NAND gate, the intermediate node in the series n-pair is hidden by the

schematic.

• The test generation must be done in such a way as to take account of possible shorts and open

circuits at the switch level. Many existing systems rely on Boolean logic representations of

circuits.

• A particular problem that arises with CMOS is that it is possible for a fault to convert a

combinational circuit into a sequential circuit:

• Illustration: Consider a 2-input NOR gate in which one of the transistor is rendered ineffective

(stuck open or stuck closed). This might be due a missing source , drain or gate connection.

• If one of the n-transistors (A connected to gate ) is stuck open , then the function displayed by

the gate will be:

• The Function Fn is the previous state of the gate.

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• Similarly if the B n-transistor is missing , the function is:

• If either p-transistor is missing, the node would be arbitrarily charged until one of the n-

transistors discharged the node. Thereafter it would remain at zero, bar charge leakage effects.

• A model for CMOS circuits that allows test generation using methpods such as D-algorithm is

shown in the figure below:

• Figure(a) shows the CMOS gate in circuit form.

• Figure(b) shows the model used for test generation.

• The n-tree and p-tree are represented by the logic blocks shown. They are connected to a B-

block which has the characteristics as shown in the table below.

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• The m-state in the table indicates that the block retains the previous state.

• The X-state may be biased towards a 0 or 1 depending on the gate and technology.

• Considering the logic model shown in the Fig(b) , open and short faults at the circuit level may

be mapped to equivalent faults in the logic representation as shown in the table above.

Design for testability

The two key concepts in designing circuits that are testable are :

i) Controllability : It is the ability to set and reset every internal node of the circuit.

ii) Observability :It is the ability to observe either directly or indirectly the state of any node in

the circuit.

Given the circuit structure , programs such as SCOAP are available that calculate the ability to

control and observe internal circuit nodes.

The three main approaches commonly called as “design for testability” are :

1) Ad-hoc testing

2) Structured design for testability

3) Self-test and Built-in testing

The techniques grouped under this category are basically the techniques to reduce the

combinational explosion of testing. Common techniques involve partitioning large sequential

circuits and adding test points.

Long counters are good examples of circuits that can be partitioned into smaller counters that may be

exercised with fewer test vectors.

Another technique is the use of the bus in a bus-oriented system for test purposes. In this category ,

the strategies used to test bit-sliced systems are included.

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The theory relating to testing of bit-sliced systems concerns a class of components known as iterative

logic arrays(ILAs). An ILA is classed as C-testable if it can be tested with a constant number of

input patterns independent of array size .

An ILA is I-testable if the test responses from every cell in the ILA can be made identical. This allows

the ILA to be tested with a minimum number of tests by using an equality circuit.

Ad-hoc testing

• Further ILAs may possess both characteristics making them CI-testable.

• An example of an ILA modified to allow I-testability is shown below:

• It consists of a cascaded 1-bit counter cell to which two gates have been added to allow the

counter to be tested.

Structured design for testability:

• A collection of approaches have evolved for testing that involves structured approach to

testability which stems from the basic concepts of controllability and observability.

• A popular approach is called LSSD- Level Sensitive Scan Design approach by IBM. LSSD is

illustrated in the figure below:

• The latches in the circuit are termed as “shift register latches” or SRLs.

• In the normal mode of operation, the registers act as the regular storage latches in the

circuit.

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• In the test mode, all of the latches in the circuit are connected in series. In this mode , data

may be shifted into or out of the cascaded registers.

• With this capability, testing is reduced to inputting a known sequence (controllability),

exercising the combinational circuitry and storing the results and shifting the stored

values out of the register (observability)

• Automatic test generation programs are available for combinational circuits further

simplifying testing approach.

• The primary objection to this testing method is the complexity that is created by the

increased circuit count in the latch , the increased external pin count and the need to chain

widely separated latches together to some extent.

Structured design for testability:

• The decision to include the testability approach would involve trading area and some speed to

achieve this level of testability. A static latch is shown in the figure below.

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• D is the regular input to the latch, while I feeds from the Q of the preceding latch in the chain.

• A two input multiplexer has been added to the circuit.

• The circuit may be implemented as shown below, since the shift path can be relatively slow.

Other LSSD implementations are also shown:

Fig(b) Fig(C)

Fig(d)

All implementations add devices to the basic latch

Self test and Built-in Test:

• One method of incorporating a built-in test module is to use signature analysis or cyclic

redundancy checking. This involves the use of a linear feedback shift register shown in the

figure below. After initialization the value in the register will be a function of the value and

number of latch inputs and the counting function of the signature analyzer.

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• The good part will have a particular number or signature in the register.

• The bad part will have a different number in the register.

• Signature analysis can be merged with the LSSD technique to create a structure known BILBO-

Built-In Logic Block Observation. This is shown in the figure below: A 3 bit register is shown

with the associated circuitry.

In mode A, C0=C1=1: The registers act as conventional parallel registers.

In mode B, C0=C1=0: The registers act as scan registers.

In mode C (C0=1, C1=0) , the registers act as a signature analyzer or PRSG(pseudo random sequence

generator)

If C0=0 and C1=1, the registers are reset. Thus a complete test generation and observation arrangement

can be implemented as shown in the figure below:

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• Another approach to built-in test is called Design for Autonomous test.

• In this approach, modules are partitioned into small modules which are then tested

exhaustively. The main method for partitioning involves the use of multiplexers.

• Figure(a) below shows the typical circuit with multiplexers added.

• Figure(b) below shows the circuit configured for normal use.

• Figure(c) below shows the circuit configured to test module A.

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• No fault models or test generation techniques are required for this technique.

• A complete module would include a pattern generator in the form of a linear feedback shift

register, a signature analyzer and test control circuitry.

• Exhaustive testing is not suitable in situations where stuck-open faults exist.

• For this reason the circuit shown in the figure below is proposed:

This provides charge and discharge control over the output of the logic gate.

After each test, the charge-discharge circuit (C/D) is exercised by asserting TEST and strobing C/D

high then low. Outputs that are not stuck open return to the correct value, while stuck open lines will

remain charged or discharged. Another method that requires exhaustive testing is called syndrome

testing. Here all possible inputs are applied to the circuit and the number of 1’s at the output are

counted. The resultant value is compared to that of a known good machine.

Extra circuitry includes a pattern generator, counter and a comparison circuit.

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