Department Of Electronics & Communication Engineering

Digital Electronics (KEC- 039)

Unit- 5
Programmable Logic Devices

Programmable Logic Devices

Programmable Logic Devices PLDs are the integrated circuits. They contain an array of AND
gates & another array of OR gates. There are three kinds of PLDs based on the type of arrays,
which has programmable feature.

• Programmable Read Only Memory

• Programmable Array Logic
• Programmable Logic Array
The process of entering the information into these devices is known as programming.
Basically, users can program these devices or ICs electrically in order to implement the Boolean
functions based on the requirement. Here, the term programming refers to hardware
programming but not software programming.

Programmable Read Only Memory PROM

Read Only Memory ROMROM is a memory device, which stores the binary information
permanently. That means, we can’t change that stored information by any means later. If the
ROM has programmable feature, then it is called as Programmable ROM PROM. The user
has the flexibility to program the binary information electrically once by using PROM
programmer.
PROM is a programmable logic device that has fixed AND array & Programmable OR array.
The block diagram of PROM is shown in the following figure.

Here, the inputs of AND gates are not of programmable type. So, we have to generate
2n product terms by using 2n AND gates having n inputs each. We can implement these product
terms by using nx2n decoder. So, this decoder generates ‘n’ min terms.
Here, the inputs of OR gates are programmable. That means, we can program any number of
required product terms, since all the outputs of AND gates are applied as inputs to each OR
gate. Therefore, the outputs of PROM will be in the form of sum of min terms.

Example
Let us implement the following Boolean functions using PROM.
A(X,Y,Z)=∑m(5,6,7)A(X,Y,Z)=∑m(5,6,7)

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 Department Of Electronics & Communication Engineering
Digital Electronics (KEC- 039)
Unit- 5
Programmable Logic Devices
B(X,Y,Z)=∑m(3,5,6,7)B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each function is having three
variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for
producing these two functions. The corresponding PROM is shown in the following figure.

Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the
access of all these min terms. But, only the required min terms are programmed in order to
produce the respective Boolean functions by each OR gate. The symbol ‘X’ is used for
programmable connections.

Programmable Array Logic PAL

PAL is a programmable logic device that has Programmable AND array & fixed OR array. The
advantage of PAL is that we can generate only the required product terms of Boolean function
instead of generating all the min terms by using programmable AND gates. The block
diagram of PAL is shown in the following figure.

Prepared By- Santosh Dubey, Asst. Prof. ECE, Prayagraj Page 2

 Department Of Electronics & Communication Engineering
Digital Electronics (KEC- 039)
Unit- 5
Programmable Logic Devices

Here, the inputs of AND gates are programmable. That means each AND gate has both normal
and complemented inputs of variables. So, based on the requirement, we can program any of
those inputs. So, we can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are not of programmable type. So, the number of inputs to each
OR gate will be of fixed type. Hence, apply those required product terms to each OR gate as
inputs. Therefore, the outputs of PAL will be in the form of sum of products form.

Example
Let us implement the following Boolean functions using PAL.
A=XY+XZ′

A=XY′+YZ′

The given two functions are in sum of products form. There are two product terms present in
each Boolean function. So, we require four programmable AND gates & two fixed OR gates for
producing those two functions. The corresponding PAL is shown in the following figure.

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 Department Of Electronics & Communication Engineering
Digital Electronics (KEC- 039)
Unit- 5
Programmable Logic Devices
The programmable AND gates have the access of both normal and complemented inputs of
variables. In the above figure, the inputs X, X′, Y, Y′, Z & Z′, are available at the inputs of
each AND gate. So, program only the required literals in order to generate one product term by
each AND gate. The symbol ‘X’ is used for programmable connections.
Here, the inputs of OR gates are of fixed type. So, the necessary product terms are connected to
inputs of each OR gate. So that the OR gates produce the respective Boolean functions. The
symbol ‘.’ is used for fixed connections.

Programmable Logic Array PLA

PLA is a programmable logic device that has both Programmable AND array & Programmable
OR array. Hence, it is the most flexible PLD. The block diagram of PLA is shown in the
following figure.

Here, the inputs of AND gates are programmable. That means each AND gate has both normal
and complemented inputs of variables. So, based on the requirement, we can program any of
those inputs. So, we can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are also programmable. So, we can program any number of
required product terms, since all the outputs of AND gates are applied as inputs to each OR
gate. Therefore, the outputs of PAL will be in the form of sum of products form.

Example
Let us implement the following Boolean functions using PLA.
A=XY+XZ′

B=XY′+YZ+XZ′

The given two functions are in sum of products form. The number of product terms present in
the given Boolean functions A & B are two and three respectively. One product
term, Z′XZ′X is common in each function.
So, we require four programmable AND gates & two programmable OR gates for producing
those two functions. The corresponding PLA is shown in the following figure.

Prepared By- Santosh Dubey, Asst. Prof. ECE, Prayagraj Page 4

 Department Of Electronics & Communication Engineering
Digital Electronics (KEC- 039)
Unit- 5
Programmable Logic Devices

The programmable AND gates have the access of both normal and complemented inputs of
variables. In the above figure, the inputs X, X′X′, Y, Y′Y′, Z & Z′Z′, are available at the inputs
of each AND gate. So, program only the required literals in order to generate one product term
by each AND gate.
All these product terms are available at the inputs of each programmable OR gate. But, only
program the required product terms in order to produce the respective Boolean functions by
each OR gate. The symbol ‘X’ is used for programmable connections.

FPGA – Introduction
The full form of FPGA is “Field Programmable Gate Array”. It contains ten thousand to
more than a million logic gates with programmable interconnection. Programmable
interconnections are available for users or designers to perform given functions easily. A typical
model FPGA chip is shown in the given figure. There are I/O blocks, which are designed and
numbered according to function. For each module of logic level composition, there are CLB’s
(Configurable Logic Blocks).
CLB performs the logic operation given to the module. The inter connection between CLB and
I/O blocks are made with the help of horizontal routing channels, vertical routing channels and
PSM (Programmable Multiplexers).
The number of CLB it contains only decides the complexity of FPGA. The functionality of
CLB’s and PSM are designed by VHDL or any other hardware descriptive language. After

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 Department Of Electronics & Communication Engineering
Digital Electronics (KEC- 039)
Unit- 5
Programmable Logic Devices
programming, CLB and PSM are placed on chip and connected with each other with routing
channels.

Advantages

• It requires very small time; starting from design process to functional chip.
• No physical manufacturing steps are involved in it.
• The only disadvantage is, it is costly than other styles.

Gate Array Design

The gate array (GA) ranks second after the FPGA, in terms of fast prototyping capability.
While user programming is important to the design implementation of the FPGA chip, metal
mask design and processing is used for GA. Gate array implementation requires a two-step
manufacturing process.
The first phase results in an array of uncommitted transistors on each GA chip. These
uncommitted chips can be stored for later customization, which is completed by defining the
metal interconnects between the transistors of the array. The patterning of metallic interconnects
is done at the end of the chip fabrication process, so that the turn-around time can still be short,
a few days to a few weeks. The figure given below shows the basic processing steps for gate
array implementation.

Prepared By- Santosh Dubey, Asst. Prof. ECE, Prayagraj Page 6

 Department Of Electro
Electronics & Communication Engineering
Digital Electronics (KEC- 039)
Unit- 5
Programmable Logic Devices

Typical gate array platforms use dedicated areas called channels, for inter
inter-cell
cell routing between
rows or columns of MOS transistors. They simplify the interconnections. Interconnection
patterns that perform basic logic gates aare
re stored in a library, which can then be used to
customize rows of uncommitted transistors according to the netlist.
In most of the modern GAs, multiple metal layers are used for channel routing. With the use of
multiple interconnected layers, the routing can be achieved over the active cell areas; so that the
routing channels can be removed as in SeaSea-of-Gates
Gates (SOG) chips. Here, the entire chip surface
is covered with uncommitted nMOS and pMOS transistors. The neighboring transistors can be
customized usingg a metal mask to form basic logic gates.
For inter cell routing, some of the uncommitted transistors must be sacrificed. This design style
results in more flexibility for interconnections and usually in a higher density. GA chip
utilization factor is measured
ured by the used chip area divided by the total chip area. It is higher
than that of the FPGA and so is the chip speed.

Standard Cell Based Design

A standard cell based design requires development of a full custom mask set. The standard cell
is also known as the polycell. In this approach, all of the commonly used logic cells are
developed, characterized and stored in a standard cell library.
A library may contain a few hundred cells including inverters, NAND gates, NOR gates,
complex AOI, OAI gates, D-latc latches and Flip-flops.
flops. Each gate type can be implemented in
several versions to provide adequate driving capability for different fan
fan-outs.
outs. The inverter gate
can have standard size, double size, and quadruple size so that the chip designer can select the
proper
er size to obtain high circuit speed and layout density.
Each cell is characterized according to several different characterization categories, such as,

• Delay time versus load capacitance

• Circuit simulation model

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 Department Of Electronics & Communication Engineering
Digital Electronics (KEC- 039)
Unit- 5
Programmable Logic Devices
• Timing simulation model
• Fault simulation model
• Cell data for place-and-route
• Mask data
For automated placement of the cells and routing, each cell layout is designed with a fixed
height, so that a number of cells can be bounded side-by-side to form rows. The power and
ground rails run parallel to the upper and lower boundaries of the cell. So that, neighboring cells
share a common power bus and a common ground bus. The figure shown below is a floorplan
for standard-cell based design.

Full Custom Design

In a full-custom design, the entire mask design is made new, without the use of any library. The
development cost of this design style is rising. Thus, the concept of design reuse is becoming
famous to reduce design cycle time and development cost.
The hardest full custom design can be the design of a memory cell, be it static or dynamic. For
logic chip design, a good negotiation can be obtained using a combination of different design
styles on the same chip, i.e. standard cells, data-path cells, and programmable logic arrays
(PLAs).
Practically, the designer does the full custom layout, i.e. the geometry, orientation, and
placement of every transistor. The design productivity is usually very low; typically a few tens
of transistors per day, per designer. In digital CMOS VLSI, full-custom design is hardly used
due to the high labor cost. These design styles include the design of high-volume products such
as memory chips, high-performance microprocessors and FPGA.

Prepared By- Santosh Dubey, Asst. Prof. ECE, Prayagraj Page 8