Q. What is addressing modes? Explain different addressing modes with example with advantages and disadvantages.

Addressing modes are techniques used to specify the operand of an instruction. Different addressing
modes provide flexibility in accessing operands from memory or registers. There are several addressing
modes commonly used in computer architecture, including:
1) Immediate Addressing Mode:
• In this mode, the operand is specified within the instruction itself.
• Example: MOV R1, #25 (moves the immediate value 25 into register R1).
• Advantages: Simple and straightforward to implement.
• Disadvantages: Wasteful of memory as the operand is part of the instruction, limiting the range of
values that can be used.

2) Direct Addressing Mode:

• The operand's memory address is directly specified in the instruction.
• Example: LOAD R2, 500 (loads the value from memory address 500 into register R2).
• Advantages: Simple to understand and efficient for accessing specific memory locations.
• Disadvantages: Limited flexibility in accessing different memory locations.

3) Register Addressing Mode:

• The operand is located in a register specified in the instruction.
• Example: ADD R3, R4, R5 (adds the contents of registers R4 and R5 and stores the result in register
R3).
• Advantages: Fast access to operands and efficient for certain types of operations.
• Disadvantages: Limited number of available registers can restrict the complexity of operations.

4) Indirect Addressing Mode:

• The instruction specifies a memory address that contains the actual address of the operand.
• Example: LOAD R6, (R7) (loads the value from the memory address stored in register R7 into register
R6).
• Advantages: Flexibility in accessing memory locations and can support data structures like linked
lists.
• Disadvantages: Requires an additional memory access, which can impact performance.

5) Indexed Addressing Mode:

• The operand's address is calculated by adding an index value to a base address.
• Example: STORE R8, 100(R9) (stores the value from register R8 into the memory location at address
100 plus the value in register R9).
• Advantages: Useful for accessing elements of arrays and data structures.
• Disadvantages: Limited by the size of the index and base registers.

Each addressing mode has its own advantages and disadvantages, and the choice of addressing mode
depends on the specific requirements of the instruction set architecture and the intended application of
the computer system.
Q. Explain Big-Endian and Little-Endian assignments with suitable data structure examples.

Big-Endian and Little-Endian are two formats used to store multi-byte data types in computer memory. The
difference between them lies in the order in which bytes are stored. Let's explain each with suitable data
structure examples:

• Big-Endian:
In Big-Endian format, the most significant byte (MSB) is stored at the lowest memory address, and the
least significant byte (LSB) is stored at the highest memory address. This is similar to how we write
numbers, with the most significant digit on the left.
Example with a 2-byte integer (0x1234):
Memory Address: 0x100 | 0x101
Value (in hex): 12 | 34
In this example, the most significant byte (0x12) is stored at the lower memory address (0x100), and the
least significant byte (0x34) is stored at the higher memory address (0x101).

• Little-Endian:
In Little-Endian format, the least significant byte (LSB) is stored at the lowest memory address, and the
most significant byte (MSB) is stored at the highest memory address. This is the reverse of the Big-Endian
format.
Example with a 2-byte integer (0x1234):
Memory Address: 0x100 | 0x101
Value (in hex): 34 | 12
In this example, the least significant byte (0x34) is stored at the lower memory address (0x100), and the
most significant byte (0x12) is stored at the higher memory address (0x101).

• Data structures like arrays and structs can be affected by endianness. For example, consider a 4-byte
integer (0x12345678) stored in memory:
In Big-Endian:
Memory Address: 0x100 | 0x101 | 0x102 | 0x103
Value (in hex): 12 | 34 | 56 | 78
In Little-Endian:
Memory Address: 0x100 | 0x101 | 0x102 | 0x103
Value (in hex): 78 | 56 | 34 | 12

The choice of endianness can impact interoperability between systems and when reading data from
external sources. It's important for software developers to be aware of endianness when working with
multi-byte data types in different computing environments.
Q. With the help of flowchart, explain a typical instruction cycle.

The instruction cycle refers to the sequence of steps that a computer's CPU (Central Processing Unit)
follows to execute a single instruction. The typical instruction cycle consists of four main stages: Fetch,
Decode, Execute, and Write Back (also known as Fetch-Decode-Execute cycle or FDE cycle). Here's a
breakdown of each stage:
1. Fetch:
• The CPU fetches the instruction from memory. It reads the instruction from the memory address
pointed to by the program counter (PC), which holds the address of the next instruction to be
executed.
• The fetched instruction is then placed into a special-purpose register called the instruction register
(IR) within the CPU.
2. Decode:
• The fetched instruction is decoded to determine what operation needs to be performed and what
data is involved.
• The instruction is interpreted by the CPU's control unit, which generates control signals to direct
other parts of the CPU and the computer system to carry out the instruction.
3. Execute:
• The decoded instruction is executed or carried out by the CPU. This stage involves performing the
actual operation specified by the instruction, which could be arithmetic/logical operations, data
movement, control transfer, etc.
• This stage might require accessing data from registers, performing calculations, fetching additional
data from memory, or interacting with other components as needed.
4. Write Back:
• After the execution stage, the result of the instruction is written back to the designated location.
This could mean storing the result in a register, updating memory, or writing to an output device.
• Once the write back stage is complete, the cycle typically repeats itself by fetching the next
instruction in memory (incrementing the program counter) and continuing with the subsequent
stages.
Each of these stages plays a crucial role in the execution of instructions by the CPU, enabling it to carry out
a series of operations to perform tasks as instructed by a program. The efficiency of this cycle greatly
impacts the overall performance of a computer system.
Q.

The push and pop operations are fundamental to stack data structures, and they're commonly used in computer
architecture for managing data in the CPU's stack memory. In the context of Computer Architecture and Organization
(CAO), let's delve into these mechanisms with diagrams:

Stack Overview:

A stack is a Last In, First Out (LIFO) data structure where elements are added or removed from only one end, traditionally
known as the "top" of the stack. The two primary operations are:

Push: Adds an element onto the top of the stack.

Pop: Removes the top element from the stack.

Push Operation

Step 1: Initial Stack State: Start with an initial stack configuration.

Step 2: Pushing an Element (New Data): To push an element onto the stack, a new element (data) is added to the top of
the stack.

Step 3: Updated Stack State: After the push operation, the stack grows, and the new element becomes the top of the
stack.

Pop Operation

Step 1: Stack with Elements: Start with a stack containing multiple elements.

Step 2: Popping an Element: To pop an element from the stack, the top element (latest data) is removed.

Step 3: Updated Stack State: After the pop operation, the stack shrinks, and the top element is removed, revealing the
next element as the new top of the stack.

In computer architecture, the stack is often used for storing return addresses, local variables, and managing function
calls. The push operation places data onto the stack, while the pop operation retrieves and removes data from the stack.

In assembly language or low-level programming, the stack is managed through instructions like PUSH (to push data onto
the stack) and POP (to pop data from the stack). These operations utilize a special pointer called the "stack pointer" (SP)
to keep track of the top of the stack.
Q. Explain the need of stack and queues in computer organization.

Need for Stacks:

1. Function Calls and Memory Management: Stacks are vital for managing function calls and memory in
programs. When a function is called, its local variables, parameters, and return addresses are stored in
a stack frame. As functions execute, they push and pop frames onto and off the stack, ensuring orderly
memory allocation and deallocation.
2. Expression Evaluation: Stacks play a crucial role in evaluating arithmetic expressions, especially those
involving infix, postfix, or prefix notations. They help in the conversion of expressions from one form to
another and in performing calculations using postfix or prefix representations.
3. Backtracking and Undo Operations: Stacks are used in backtracking algorithms (like in-depth-first
search) and for maintaining a history of operations, enabling undo functionalities in applications.
4. CPU Operation Management: The CPU stack often holds return addresses for subroutines, enabling
efficient execution flow by allowing the CPU to return to the proper location after executing a
subroutine.

Need for Queues:

1. Task Scheduling: Queues are crucial for managing tasks and processes in a first-in, first-out (FIFO)
manner. Operating systems use queues to schedule tasks, manage I/O requests, and control access to
system resources.
2. Buffering and Communication: In networking and I/O systems, queues help manage data transfer
between different components, ensuring that data is processed in the order it was received.
3. Print Spooling: Queues are utilized in print spooling systems where multiple print jobs are lined up and
processed sequentially.
4. Breadth-First Search (BFS): In algorithms like BFS, queues facilitate the exploration of graphs by storing
nodes to be visited, ensuring that nodes are processed at the same level before moving deeper into the
graph.

Both stacks and queues provide fundamental ways of organizing data and managing program flow. They
facilitate efficient memory management, data processing, task scheduling, and algorithmic
implementations across various computing systems, ensuring orderly execution and resource utilization
within the computer architecture. Their versatility and specific functionalities make them indispensable
tools in computer organization and system design.

Q. Enumerate different types of instruction formats. Write the program code with appropriate comments for
evaluating (A+B) ((C+D)/E) or (A+B) (C+D) expression using1. Zero address instruction format. 2. One address
instruction format. 3. Two address Instruction format. 4. Three address instruction format. 5. RISC instruction
format. \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\//\//\/\\/\/\\/\/\/\/\/\/\//\/\\/\/\/\/\/\/\/\/\/\/ PTO
 • 1. Zero Address Instruction Format

LOAD A # Push A onto the stack

LOAD B # Push B onto the stack

ADD # Pop top two elements, add them, and push result

LOAD C # Push C onto the stack

LOAD D # Push D onto the stack

ADD # Pop top two elements, add them, and push result

LOAD E # Push E onto the stack

DIVIDE # Pop top two elements, divide, and push result

• 2. One Address Instruction Format

LOAD A # Load A into accumulator

ADD B # Add B to accumulator

STORE TEMP # Store result in temporary memory location

LOAD C # Load C into accumulator

ADD D # Add D to accumulator

STORE RESULT # Store result in final memory location

LOAD E # Load E into accumulator

DIVIDE TEMP # Divide temporary result by E

• 3. Two Address Instruction Format

ADD A, B, TEMP # Add A and B, store result in TEMP

ADD C, D, RESULT # Add C and D, store result in RESULT

DIVIDE RESULT, E # Divide RESULT by E

• 4. Three Address Instruction Format

ADD TEMP1, A, B # Add A and B, store result in TEMP1

ADD TEMP2, C, D # Add C and D, store result in TEMP2

DIVIDE RESULT, TEMP2, E # Divide TEMP2 by E, store result in RESULT

• 5. RISC Instruction Format

LOAD R1, A # Load A into register R1

ADD R1, R1, B # Add B to R1

LOAD R2, C # Load C into register R2

ADD R2, R2, D # Add D to R2

DIVIDE R2, R2, E # Divide R2 by E

CHAPTER 1 : _________________________________________________________________________________________
Q. What are the various performance enhancement techniques? Explain 1. Perfecting i. Write Buffer iii. Lockup-Free
Cache iv, Memory Interleaving

Several performance enhancement techniques aim to improve the overall efficiency and speed of a
computer system. These techniques play crucial roles in optimizing memory access, reducing stalls, and
improving the efficiency of various components within the computer system. They are essential in
enhancing the overall performance of modern computer architectures by minimizing bottlenecks and
optimizing data flow between the CPU and memory subsystems.
1. Write Buffer:
• Purpose: Write buffers are used to enhance performance by reducing the impact of write operations
on system speed.
• Functionality: When a CPU performs a write operation to memory, it's not immediately written to
the main memory. Instead, it's temporarily stored in a write buffer.
• Advantages: This allows the CPU to continue its operations without waiting for the actual write to
complete. The buffer later flushes these writes to memory in an optimized manner, minimizing the
stalls in the CPU due to slow memory access.

2. Lockup-Free Cache:
• Purpose: Lockup-free caches are designed to reduce the downtime of the cache during a cache miss
situation.
• Functionality: When a cache miss occurs, traditional caches may stall the CPU until the requested
data is fetched from main memory. Lockup-free caches allow other cache accesses to proceed while
the cache miss is being handled.
• Advantages: By allowing continued access to the cache, even during a cache miss, the CPU can
operate more efficiently without long waiting periods for memory access.

3. Memory Interleaving:
• Purpose: Memory interleaving is a technique used to enhance memory access speeds in multi-
channel memory architectures.
• Functionality: It involves distributing memory addresses across multiple memory modules or banks
in a round-robin fashion.
• Advantages: This technique helps improve memory bandwidth by allowing multiple memory
accesses to occur simultaneously across different memory modules. It reduces contention for
memory access and enhances overall memory throughput.

4. Prefetching:
• Purpose: Prefetching is a technique used to improve memory access times by predicting and
retrieving data before it's explicitly requested by the CPU.
• Functionality: The system predicts which data might be needed next based on patterns or access
history and preloads it into the cache or a buffer.
• Advantages: By reducing the time required to access data from main memory, prefetching can hide
memory latency and improve overall system performance.
Q. What is cache memory? Explain Associative-Mapping.Set Associative-Mapping and Direct Mapping function in cache.

Cache memory is a high-speed memory unit used to store frequently accessed data and instructions,
providing faster access than the main memory (RAM) in a computer system. It acts as a buffer between
the CPU and main memory to reduce the time taken to access data.
Functionality: When the CPU requests data, the cache is checked first. If the data is found in the cache
(cache hit), it's retrieved quickly. If not (cache miss), the data is fetched from the main memory and
placed into the cache for future use.
1) Associative Mapping:
• Functionality: In associative mapping, any block of main memory can be placed in any cache
location. Each block in main memory has a tag associated with it that identifies its location in the
cache.
• Implementation: The cache is searched in parallel for the desired data across all cache lines,
comparing tags to find a match. This allows for flexible placement of data in the cache without
the restrictions of specific locations.
• Advantages: Offers high flexibility in cache placement, eliminating conflicts and allowing any
block to be placed in any cache line. However, it requires more complex hardware and is
generally more expensive.
2) Set Associative Mapping:
• Functionality: Set associative mapping is a compromise between associative and direct mapping.
The cache is divided into a set of lines or slots, and each set contains multiple lines.
• Implementation: Each block from the main memory can be placed in any line within a specific
set, using a direct mapping approach within each set. It combines the flexibility of associative
mapping with some of the structure of direct mapping.
• Advantages: Reduces the chance of conflicts compared to direct mapping while being less
complex than fully associative mapping. It strikes a balance between flexibility and hardware
complexity.
3) Direct Mapping:
• Functionality: In direct mapping, each block of main memory is mapped to exactly one specific
line in the cache.
• Implementation: The mapping is done using a mathematical function that determines the cache
line where a particular memory block should reside. This function usually involves modulo
arithmetic.
• Advantages: Simple and cost-effective to implement since it requires minimal hardware
complexity. However, it can lead to higher conflict misses because multiple memory blocks may
map to the same cache line.
Q. What is Virtual Memory? With the help of suitable diagram, explain how logical to physical address translation done.

Virtual memory is a memory management technique that allows a computer to compensate for physical
memory shortages by temporarily transferring data from RAM to disk storage. It enables larger and
more complex programs to run, even if the physical memory (RAM) is limited.
Logical to Physical Address Translation:
1. The translation from logical addresses (used by the CPU) to physical addresses (actual locations
in memory) involves several steps and is facilitated by hardware and operating system
components:
2. Logical Address Space: The CPU generates logical addresses during program execution. These
addresses are typically contiguous and start at zero, representing the entire range of memory the
program can access.
3. Memory Management Unit (MMU): The MMU, a hardware component, plays a crucial role in
address translation. It has a page table that maps logical addresses to physical addresses.
4. Page Table: The page table is a data structure used by the MMU. It contains entries that map
logical page numbers to physical frame numbers.
5. Pages and Frames: Memory is divided into fixed-size pages (logical memory) and frames (physical
memory). Pages in the logical address space correspond to frames in the physical address space.
Translation Process:

• When the CPU generates a logical address, it's divided into a page number and an offset within
that page.
• The page number is used as an index into the page table to find the corresponding entry.
• The page table entry contains the physical frame number where that page resides in physical
memory.
• The offset within the page remains unchanged.

6. Obtaining Physical Address: Once the physical frame number is retrieved from the page table, it's
combined with the offset to generate the actual physical address.
7. Handling Page Faults: If the page table entry indicates that the required page is not currently in
physical memory (a page fault), the operating system initiates a process called page replacement.
It selects a page to remove from memory (if necessary), writes it to the disk (if modified), and
brings the required page into memory from disk.
8. TLB (Translation Lookaside Buffer): To speed up address translation, a Translation Lookaside
Buffer is used as a cache for frequently accessed page table entries. It stores recently used
mappings to reduce the time taken to fetch page table entries.
Q. What is Virtual Memory? What are the various Control Bits used in Page Table? Explain need of PBTR & TLB in
virtual memory management.

Virtual memory is a memory management technique that extends the available memory in a computer
system by temporarily transferring data from RAM to disk storage. It allows larger programs to run than
can fit entirely in physical memory. Virtual memory creates an illusion of a larger, contiguous memory
space for programs than the physical RAM available.

• Control Bits in Page Table:

Page tables, used in virtual memory systems, contain control bits that manage various aspects of
memory access. Some common control bits include:
1. Valid/Invalid Bit: Indicates whether a page is currently in physical memory (valid) or not (invalid).
2. Dirty Bit: Marks whether a page has been modified since it was brought into memory.
3. Reference Bit: Indicates whether a page has been accessed recently.
4. Protection Bit: Determines the access rights (read, write, execute) for the page.
5. Page Frame Number: Stores the physical address where the page is located in memory.
Need for Page-Based Translation and Translation Lookaside Buffer (TLB):
1. Page-Based Translation (PBTR):
• Efficient Memory Management: PBTR allows efficient memory allocation by dividing memory
into fixed-size pages, simplifying address translation.
• Flexibility: It facilitates the concept of virtual memory, enabling the use of larger address spaces
for processes than the physical memory available.
2. Translation Lookaside Buffer (TLB):
• Speed Enhancement: TLB is a hardware cache that stores recently accessed page table entries
(page number to frame number mappings). It speeds up the translation process by avoiding
frequent accesses to the slower main memory page table.
• Reduced Overhead: TLB reduces the time taken for address translation, as it holds frequently
used mappings, reducing the overhead of accessing the full page table.
Importance in Virtual Memory Management:

• Improved Performance: Both PBTR and TLB significantly improve the performance of virtual
memory systems. PBTR provides the structure for efficient page-based memory management,
while TLB reduces the time needed for address translation by caching frequently accessed page
table entries.
• Larger Address Spaces: They enable systems to manage larger address spaces efficiently, allowing
larger programs to execute without requiring all data and instructions to be loaded into physical
memory at once.
• Efficient Memory Utilization: Virtual memory management techniques like PBTR and TLB allow
for more efficient utilization of physical memory by dynamically swapping pages between RAM
and disk based on program requirements.
Q. What is Cache Coherence Problem? Explain how it is overcome.

Cache coherence problem arises in multi-processor systems where each processor might have its own
cache memory. The issue arises due to the possibility of multiple caches storing copies of the same
memory block but with potentially different values. Maintaining coherence ensures that all processors
have a consistent view of memory, despite working with their individual caches.

• Importance of Cache Coherence:

Cache coherence is vital to ensure data consistency and program correctness in multi-processor systems.
Without coherence, different processors may have different views of memory, leading to errors,
inconsistency, and incorrect program behavior.

• Causes of Cache Coherence Problem:

Multiple Copies: When multiple processors have their own caches and access the same memory
location, they might load the same memory block into their respective caches.
Data Modification: If one processor modifies a memory block stored in its cache, other processors might
still have an outdated copy of that block in their caches.

• Overcoming Cache Coherence Problem:

Several mechanisms are used to maintain cache coherence in multi-processor systems:
Snooping Protocols:

• Bus-Based Coherence: In this approach, processors monitor or "snoop" the system bus to detect
any updates or changes made by other processors to shared memory locations. If a processor
detects a change to a memory block it has cached, it takes appropriate action like invalidating its
copy or updating it.
• Advantages: Simple to implement and effective for smaller systems.
Directory-Based Coherence:

• Centralized Directory: A directory maintains information about which caches have copies of
which memory blocks. When a processor wants to read or modify a block, it communicates with
the directory to ensure coherence.
• Advantages: Scales better for larger systems with more processors as it avoids bus contention.
Cache Coherence Protocols:

• MESI Protocol (Modified, Exclusive, Shared, Invalid): This protocol categorizes cache lines as
Modified, Exclusive, Shared, or Invalid, defining the state of the data in the caches. It dictates
how caches interact when accessing or modifying shared data.
• MOESI, MOSI, etc.: Variations of the MESI protocol, adding optimizations or additional states to
handle specific scenarios more efficiently.
Flush and Invalidate Operations:

• Processors perform explicit operations to either invalidate or update their cached copies of data
when they detect modifications by other processors. This ensures coherence by making sure all
caches have consistent data.
Q. Draw a Block diagram depicting the realization of 2M X 32 memory modules using 512K X8 static memory chip.
Explain how many address lines are needed to address the single word.

Chapter 2 : _______________________________________________________________________________________
Q. Draw the Single bus organization of the datapath of the CPU and show the control sequence for the execution of
MUL (R3), R1 for this organization.
Q. Draw the Three bus organization of the datapath of the CPU and show the control sequence for the execution of
SUB R1, R2, R3 for this organization.
Q. Differentiate in between Hard-wired control and Micro-programmed control. Enumerates the advantages and
disadvantages of each organization.

Hardwired Control:

• Implementation: In hardwired control, the control signals are directly generated by

combinational logic circuits and gates.
• Organization: Control signals are generated using fixed logic circuits, often implemented with
AND, OR, and NOT gates.
Advantages:

• Faster Execution: Hardwired control can be faster due to direct hardware implementation, which
doesn't require additional decoding steps.
• Simple Design: The hardware design is typically simpler, especially for simple instruction sets,
leading to lower cost and complexity.
Disadvantages:

• Limited Flexibility: Modifications or updates to control signals or sequences require physical

changes to the circuitry, making it less flexible.
• Complex for Complex Instruction Sets: For complex instruction sets or architectures, designing
and maintaining hardwired control becomes increasingly intricate and error-prone.

Microprogrammed Control:

• Implementation: In microprogrammed control, control signals are generated by a set of

microinstructions stored in control memory (Control Store).
• Organization: The control unit fetches microinstructions from control memory, interpreting and
executing them sequentially to generate control signals.
Advantages:

• Flexibility: Easier to modify or update control signals and sequences by changing the
microinstructions, without altering the hardware.
• Complex Instruction Sets: Suitable for complex instruction sets or architectures, as it offers
greater flexibility and easier modification.
Disadvantages:

• Slower Execution: Requires additional memory access and interpretation of microinstructions,

leading to slower execution compared to hardwired control.
• Increased Complexity: Designing and maintaining control memory and microinstruction
sequencing can be complex, especially for large instruction sets.
Q. Explain the sequence of operations needed to perform following CPU functionsa. a. Fetching a word from memory.
b. Storing a word into memory. c. Performing arithmetic and logical operations.

The sequence of operations involved in performing CPU functions like fetching a word from memory,
storing a word into memory, and performing arithmetic and logical operations varies slightly but
involves several common steps.

Fetching a Word from Memory:

1. Address Generation: The CPU generates the memory address of the word to be fetched. This
address could come from the instruction pointer or other control mechanisms.
2. Memory Request: The CPU sends the memory address to the memory controller.
3. Memory Access: The memory controller initiates a read operation from the specified memory
address.
4. Data Transfer: The retrieved word from memory is transferred to the CPU via the data bus.
5. CPU Processing: The CPU receives the word and may store it temporarily in registers or other
internal structures for further processing or execution.

Storing a Word into Memory:

1. Address Generation: Similar to fetching, the CPU generates the memory address where the word
needs to be stored.
2. Data Preparation: The CPU places the word to be stored onto the data bus.
3. Memory Write Request: The CPU sends the memory address and data to the memory controller,
requesting a write operation.
4. Memory Write: The memory controller writes the word into the specified memory address.
5. Confirmation: Once the write operation is completed, the CPU may receive an acknowledgment
or status update indicating the successful write.

Performing Arithmetic and Logical Operations:

1. Register Fetch: The CPU fetches data from registers or memory locations based on the
instruction's operands.
2. ALU Operation: The Arithmetic Logic Unit (ALU) executes the desired arithmetic or logical
operation (addition, subtraction, AND, OR, etc.) on the fetched data.
3. Result Storage: The result of the operation is temporarily stored in a register or designated
location within the CPU.
4. Conditional Operations (if applicable): Conditional operations involve evaluating conditions (e.g.,
comparisons) and deciding on further actions based on the result.
5. Write Back (if applicable): If the operation involves storing the result back to memory or a
register, the CPU executes the write operation accordingly.
Q. Explain Hardwired control unit with neat labeled diagram.

A hardwired control unit in Computer Architecture and Organization (CAO) refers to a control unit designed using
combinational logic circuits to generate control signals for directing the operations of a CPU.

• Design Principle: It employs fixed logic circuits comprising AND, OR, and NOT gates to create control signals
without the need for additional memory elements.
• Function: Generates control signals based on the decoded instruction or the current state of the CPU, directing
various components (ALU, registers, memory) on what actions to perform.
• Implementation: Each instruction corresponds to a unique pattern of control signals, and the control unit's
design is specific to the instruction set architecture (ISA) of the CPU.
• Advantages: It can result in faster operation due to the direct hardware implementation and is simpler in
design, especially for CPUs with simpler instruction sets.
• Disadvantages: Lack of flexibility - any changes or modifications to the control signals require physical changes
to the circuitry, making it less adaptable to changes in the instruction set or CPU functionalities.

Q. What is microinstruction? Explain Vertical and Horizontal organization microinstruction.

Microinstructions are low-level instructions used in microprogrammed control units to control the operations of a
CPU. These instructions are executed sequentially to generate control signals that direct the activities of the CPU
components. 1. Vertical Microinstruction Organization:

• Description: In vertical microinstruction organization, each microinstruction corresponds to a single control

signal or a small set of control signals.
• Structure: Each microinstruction contains fields dedicated to specific control signals, often represented as bits
or groups of bits.
• Advantages: Offers simplicity and direct control over individual control signals, making it straightforward for
control unit design.
• Disadvantages: May require a large number of microinstructions to perform complex operations, potentially
leading to larger control memory requirements.

2. Horizontal Microinstruction Organization:

• Description: In horizontal microinstruction organization, each microinstruction contains multiple control
signals in parallel.
• Structure: Microinstructions consist of fields representing control signals for various CPU components,
allowing multiple operations to be executed simultaneously.
• Advantages: Enables simultaneous control of multiple components, leading to potentially more efficient
execution of complex operations.
• Disadvantages: May be more complex to design and implement due to the need for wider microinstruction
formats and control logic to manage parallel operations.
Q. Explain Microprogrammed control. Analyse the advantages and disadvantages of microprogrammed control over
hardwired control.

Microprogrammed control is a control mechanism used in CPU design that employs microinstructions stored
in control memory (Control Store) to execute instructions. It involves using a sequence of low-level
instructions (microinstructions) to generate control signals that orchestrate the operations of the CPU
components.

• Control Unit Design: The control unit interprets the fetched instructions and generates sequences of
microinstructions.
• Microinstruction Execution: Each microinstruction specifies control signals to coordinate the
operations of various CPU components (ALU, registers, memory).
• Control Memory: Stores microinstructions as a control program, providing the sequence of actions
needed to execute instructions.
• Flexibility: Offers greater flexibility compared to hardwired control, allowing easier modifications by
changing the microinstructions without altering the hardware.
• Complex Instruction Sets: Suited for complex instruction sets as it enables easier control signal
generation for diverse operations.
• Implementation: Involves a Control Unit that fetches microinstructions, interprets them, and
generates control signals accordingly.
Advantages of Microprogrammed Control over Hardwired Control:

• Flexibility: Microprogrammed control allows easier modifications by altering the stored

microinstructions, enabling adaptations to changes in the instruction set or CPU functionalities
without hardware changes.
• Complexity Management: Suited for complex instruction sets or architectures, as it provides a more
straightforward way to generate control signals for diverse operations and instructions.
• Debugging and Testing: Easier to debug and test as changes in control behavior can be achieved by
modifying the microinstructions without redesigning the hardware.
Disadvantages of Microprogrammed Control compared to Hardwired Control:

• Execution Speed: Generally slower execution compared to hardwired control due to the additional
steps involved in fetching and interpreting microinstructions from control memory.
• Complexity in Design: Designing and managing the control memory, control sequencing, and
microinstruction formats can be more complex than hardwired control, especially for large
instruction sets.
• Hardware Overhead: Requires additional hardware elements (control memory) to store
microprograms, potentially leading to increased hardware complexity and cost.

CHAPTER 3 _______________________________________________________________________________
Q. What is Bus arbitration? Explain Centralized arbitration and Distributed arbitration in detail.

Bus arbitration refers to the process of determining which device on a shared bus gets to use it at any
given time when multiple devices or components are contending for access to the bus. This arbitration
ensures proper and fair access to the bus, avoiding conflicts and allowing efficient data transfer.

Centralized Arbitration:

• Description: In centralized arbitration, a single controlling unit or arbiter manages and decides
which device gets access to the bus.
• Arbiter Function: The arbiter receives requests from multiple devices seeking access to the bus
and grants access based on a predefined priority scheme or an algorithm.
Advantages:

• Simplified Control: Clear decision-making by a single arbiter, making it easier to implement and
manage access control.
• Deterministic: Follows a predefined priority scheme, ensuring predictable access patterns.
Disadvantages:

• Single Point of Failure: If the arbiter fails, the entire bus access control collapses, impacting all
connected devices.
• Bottleneck: Potential bottleneck as all arbitration decisions go through a single point, limiting
scalability.

Distributed Arbitration:

• Description: In distributed arbitration, each device contending for the bus has its own arbitration
logic, making local decisions regarding bus access.
• Arbitration Logic: Each device determines its own priority or access rights independently based
on its requirements and local conditions.
Advantages:

• Decentralized: No single point of failure, as decisions are made independently by each device.
• Scalability: Allows for better scalability, as the arbitration load is distributed among devices.
Disadvantages:

• Complexity: Increased complexity due to the need for individual arbitration logic in each device.
• Potential Conflicts: Lack of centralized control might lead to conflicts or contention if not
managed effectively.
Q. Explain the following terms: 1 PCI Bus II. SCSI bus

PCI Bus (Peripheral Component Interconnect Bus):

• Description: PCI (Peripheral Component Interconnect) is a high-speed bus standard used for
connecting hardware devices to a computer's central processing unit (CPU). It provides a
standardized interface for devices like expansion cards, such as network cards, sound cards,
graphics cards, and more.
Features:

• High Speed: Offers high data transfer rates, initially at 33 MHz and later advancements to 66 MHz
and 133 MHz, providing faster communication between the CPU and connected devices.
• Plug and Play: Supports plug-and-play functionality, allowing devices to be automatically
configured upon insertion without requiring manual configuration.
• 32-bit and 64-bit Versions: Initially introduced as a 32-bit bus, and later expanded to a 64-bit
version (PCI-X) for higher performance.
• Backward Compatibility: Offers backward compatibility, allowing newer PCI devices to work on
older PCI slots, although at reduced speeds.
• Advantages: Standardization, high data transfer rates, plug-and-play support, and versatility in
supporting various devices.
• Disadvantages: Limited bandwidth compared to newer standards like PCIe (PCI Express), which
offer significantly higher data transfer rates.

SCSI Bus (Small Computer System Interface):

• Description: SCSI is a set of standards for connecting and transferring data between computers
and peripheral devices, such as hard drives, tape drives, CD-ROM drives, scanners, and printers.
Features:

• Fast Data Transfer: SCSI supports high data transfer rates, making it suitable for devices that
require quick data access.
• Multiple Devices: Allows for the connection of multiple devices (up to 15 or more) to a single
SCSI bus, using a variety of SCSI device types.
• Variants: Different SCSI variants exist, including SCSI-1, SCSI-2, SCSI-3, and Ultra SCSI, offering
improved performance and features with each iteration.
• Wide Compatibility: SCSI offers wide compatibility across various operating systems and devices.
• Advantages: Fast data transfer rates, support for multiple devices on a single bus, and
compatibility with various devices and operating systems.
• Disadvantages: Complexity in setup and configuration compared to other interfaces, higher cost
for SCSI devices compared to some alternatives like IDE (Integrated Drive Electronics) or SATA
(Serial ATA).
Q. Explain the concept of Direct Memory Access (DMA) and its advantages in I/O operations. Explain two channel
DMA controllers.

Direct Memory Access (DMA) is a technique that allows hardware devices to transfer data directly to
and from the system's memory without involving the CPU. DMA controllers facilitate this process,
enabling peripherals like disk drives, network interfaces, and graphics cards to access the system
memory independently.
Functioning of DMA:

• Request Initiation: When a hardware device needs to transfer data to or from memory, it
requests control of the system bus from the CPU via the DMA controller.
• CPU Handoff: Upon approval from the CPU, the DMA controller takes control of the bus
temporarily to perform data transfer operations.
• Data Transfer: The DMA controller coordinates the data transfer directly between the peripheral
device and the system memory without CPU intervention.
• Completion Notification: Once the transfer is complete, the DMA controller signals the CPU,
which can resume control of the system bus.
Advantages of DMA in I/O Operations:

• Reduced CPU Overhead: DMA significantly reduces the load on the CPU by offloading data
transfer tasks to the DMA controller, allowing the CPU to focus on executing other tasks
concurrently.
• Faster Data Transfer: DMA operations are typically faster as they bypass the CPU, enabling
devices to transfer data directly to and from memory at high speeds without waiting for CPU
involvement.
• Improved System Performance: By freeing up the CPU to handle other tasks while data transfer
occurs independently, DMA enhances overall system performance and responsiveness.
• Efficiency in Large Data Transfers: Particularly beneficial for large data transfers (like file copying,
video streaming, etc.) where direct access to memory by peripherals speeds up the process.
• Enhanced Multitasking: Enables efficient multitasking by allowing the CPU to perform other
operations while data transfers occur in the background.
Two Channel DMA Controllers:
A two-channel DMA controller refers to a DMA controller that features two separate DMA channels capable
of handling independent data transfer operations concurrently. Each channel operates independently and
can handle its own data transfer requests without interfering with the other channel's operations.
Advantages of Two-Channel DMA Controllers:

• Parallel Data Transfers: Enable simultaneous data transfers on two different channels, allowing for
higher data throughput and reduced transfer latency.
• Improved Efficiency: Distributes the data transfer load across two channels, optimizing system
performance and resource utilization.
• Increased Flexibility: Provides flexibility in managing multiple data transfer requests, accommodating
multiple I/O devices or handling diverse data transfer needs simultaneously.
Q. Explain the I/O interface for a input device with diagram.

An I/O interface for an input device involves the connection and communication between the input
device and the computer system. Let's consider a basic example of a keyboard as the input device and
its I/O interface with the computer system:
I/O Interface for a Keyboard Input Device:
Components:
1. Keyboard: The input device that sends data (keystrokes) to the computer.
2. I/O Controller/Interface: The interface circuitry that manages the communication between the
keyboard and the computer system.
3. Data Bus: The pathway through which data is transferred between the keyboard and the
computer system's memory or processor.
4. Control Signals: Signals used for coordinating data transfer and controlling the communication
between the keyboard and the computer.
Keyboard to I/O Controller:

• The keyboard sends data (keystrokes) to the I/O interface/controller.

• The I/O interface receives and manages the incoming data from the keyboard.
I/O Controller to Computer System:

• The I/O controller transmits the received data (keystrokes) to the computer system via the data
bus.
• Control signals manage the flow and coordination of data transfer between the I/O interface and
the computer system.
Computer System Processing:

• The computer system's processor or memory receives the data from the keyboard through the
I/O interface.
• The processor may interpret or process the received keystrokes according to the operating
system or application requirements.
Q. What do you mean by Interrupt & Exception? Explain the signification of Interrupt & Exception.

Interrupt:
An interrupt is a mechanism by which a computer's normal flow of instruction execution is temporarily
halted to give special attention to a specific event or condition. Interrupts are used to handle
asynchronous events that require immediate attention, such as input/output requests, hardware
signals, or external events.

Types of Interrupts:

• Hardware Interrupts: Triggered by external hardware devices to signal events like keyboard
input, disk operations, or timer events.
• Software Interrupts: Invoked by software instructions (system calls) to request specific services
from the operating system.
• Exception Interrupts: Generated in response to error or exceptional conditions, often resulting in
the termination of the program.
Exception:
An exception is a condition or event that occurs during the execution of a program, deviating from the
normal execution flow. Exceptions are often caused by errors, such as division by zero, accessing invalid
memory, or attempting to execute an illegal instruction.

Signification of Interrupts and Exceptions:

• Handling Asynchronous Events: Both interrupts and exceptions are crucial for handling events
that occur asynchronously to the normal program execution. They allow the system to respond
promptly to external stimuli or errors.
• Event-driven Execution: Interrupts enable event-driven execution, allowing the CPU to switch its
attention to specific tasks or events as they occur, rather than executing instructions sequentially.
• Error Handling: Exceptions play a significant role in error handling. When an error is detected
during program execution, an exception is triggered, and the system can take appropriate
actions, such as terminating the program or invoking error-handling routines.
• Resource Management: Interrupts are essential for managing system resources, especially in
multitasking environments. They help in efficiently handling I/O operations, allowing the CPU to
perform other tasks while waiting for external events to complete.
• System Calls: Software interrupts are commonly used for system calls, allowing user programs to
request services from the operating system. This facilitates interaction between user programs
and the underlying system.
Q. Explain programmed I/O and interrupt driven 1/0 in detail.

Programmed I/O:

• Description: In programmed I/O, the CPU is directly responsible for managing the data transfer between the
I/O device and memory. The CPU continuously checks the status of the I/O device and transfers data between
the device and memory using programmed instructions.

Workflow of Programmed I/O:

• Polling I/O Status: The CPU continuously checks the status of the I/O device by repeatedly reading status
registers.
• Data Transfer: When the I/O device is ready, the CPU initiates data transfer by reading or writing data between
the device and memory using instructions.
• Control Loop: The CPU manages the entire data transfer process in a loop, continually checking the device
status and transferring data as necessary.

Advantages of Programmed I/O:

• Simple Implementation: Straightforward and easy to implement, especially for simple I/O operations.
• Control Over Data Transfer: The CPU has direct control over the data transfer process.

Disadvantages of Programmed I/O:

• High CPU Overhead: Constantly checking and managing I/O device status can consume significant CPU
resources.
• Inefficiency: Inefficient for devices with irregular or unpredictable data transfer rates, leading to potential
wastage of CPU cycles.

Interrupt-Driven I/O:

• Description: In interrupt-driven I/O, the CPU is not continuously engaged in checking I/O device status.
Instead, the CPU is notified asynchronously via interrupts when an I/O device is ready for data transfer or
when the data transfer is complete.

Workflow of Interrupt-Driven I/O:

• I/O Device Initiation: The I/O device initiates an I/O operation (e.g., data ready for transfer).
• Interrupt Signal: The device sends an interrupt signal to the CPU to notify it of the event (e.g., data ready or
transfer completed).
• Interrupt Service Routine (ISR): Upon receiving the interrupt, the CPU suspends its current task, executes an
Interrupt Service Routine (ISR) to handle the I/O operation, and transfers data between the device and
memory.

Advantages of Interrupt-Driven I/O:

• Reduced CPU Overhead: CPU is not continuously engaged in checking device status, conserving CPU resources.
• Efficiency: More efficient for devices with irregular or unpredictable data transfer rates.

Disadvantages of Interrupt-Driven I/O:

• Complexity: Requires additional hardware support for interrupt handling and requires coordination between
CPU and devices.
• Latency: Handling interrupts introduces a slight delay compared to direct CPU involvement in programmed
I/O.

CHAPTER 4 : __________________________________________________________________________
Q. What is cache coherence problem? Discuss the software and hardware approach for cache coherence.

The cache coherence problem arises in multiprocessor systems where multiple CPU cores or processors
have their caches (smaller, faster memory) storing copies of shared data. When multiple caches hold
copies of the same data, ensuring that these copies remain consistent (coherent) becomes a challenge,
especially when one processor modifies the data.
❖ Cache Coherence Problem:
The cache coherence problem occurs when different processors or cores store local copies of shared
data in their caches. If one processor modifies its cached copy, other processors' cached copies become
stale or outdated. Maintaining coherence ensures that all cached copies of shared data reflect the most
recent update, preventing inconsistencies and ensuring correct program execution.
❖ Software Approach for Cache Coherence:
1. Invalidate Protocol:
Method: When one processor modifies shared data, it sends messages to invalidate or mark as invalid
all other processors' cached copies of that data. When another processor tries to access the invalidated
data, it fetches the updated data from the main memory.
Advantage: Simplifies coherence management by ensuring that only the processor with the updated
data can access it, avoiding conflicts.
2. Update Protocol:
Method: Instead of invalidating, a processor updates the shared data in its cache and propagates the
update to other processors' caches.
Advantage: Reduces main memory accesses as updated data is available in caches, but it requires
additional communication for updates.

• Hardware Approach for Cache Coherence:

1. Snooping-Based Protocol:
Method: Each cache controller monitors (snoops) the bus for memory transactions. When a processor
writes to a location, other caches snoop to update or invalidate their copies.
Advantage: Simplifies coherence by continuously monitoring the bus for changes, allowing immediate
updates or invalidations.
2. Directory-Based Protocol:
Method: Uses a centralized directory that maintains information about which caches hold copies of
which data. When data is modified, the directory coordinates updates or invalidations to relevant
caches.
Advantage: Scales well for larger systems, reducing bus traffic by centralizing coherence management.
Q. Define and differentiate SIMD and MIMD.

Let’s see the difference between SIMD and MIMD:

S.NO SIMD MIMD

SIMD stands for Single Instruction While MIMD stands for Multiple
1.
Multiple Data. Instruction Multiple Data.

2. SIMD requires small or less memory. While it requires more or large memory.

3. The cost of SIMD is less than MIMD. While it is costlier than SIMD.

4. It has single decoder. While it have multiple decoders.

While it is accurate or explicit

5. It is latent or tacit synchronization.
synchronization.

While MIMD is a asynchronous

6. SIMD is a synchronous programming.
programming.

SIMD is a simple in terms of complexity While MIMD is complex in terms of

7.
than MIMD. complexity than SIMD.

SIMD is less efficient in terms of While MIMD is more efficient in terms of

8.
performance than MIMD. performance than SIMD.

Q. Explain:-i. NUMA ii. Cluster lil SMP

i. NUMA (Non-Uniform Memory Access): NUMA is a computer memory design used in multiprocessing
where the memory access time depends on the memory location relative to the processor. In a NUMA
system, each processor can access its own local memory faster than non-local memory, which can result
in non-uniform memory access times.
ii. Cluster: A cluster is a group of interconnected computers that work together as a single system.
Clusters are commonly used in high-performance computing and for providing high availability for
applications and services.
iii. SMP (Symmetric Multiprocessing): SMP is a computer architecture where two or more identical
processors are connected to a single shared main memory and are controlled by a single operating
system instance. In SMP systems, each processor performs the same tasks and has equal access to
resources.
Q. What is Multithreading? Explain Implicit and Explicit Multithreading.

Multithreading is a programming and execution model that allows multiple threads (smaller units of a
process) to exist within the context of a single process. These threads can execute independently,
sharing the same memory space, and they are managed by the operating system or a runtime
environment.
Multithreading plays a significant role in CAO by allowing better utilization of modern multi-core
processors, enhancing system performance by leveraging parallelism, and improving overall system
responsiveness by efficiently handling concurrent tasks. Understanding and effectively using
multithreading techniques are crucial for optimizing system resources and achieving efficient task
execution in complex computing environments.

Implicit Multithreading:

• Description: Implicit multithreading is when the creation and management of threads are
handled by the system or runtime environment without explicit programming by the developer.
• Example: In certain programming languages or environments, operations like I/O or handling
user interface events may automatically create and manage threads in the background without
explicit instruction by the programmer.
• Significance: Implicit multithreading simplifies the programming process for tasks that benefit
from concurrency but don't require explicit thread management by the developer.
Explicit Multithreading:

• Description: Explicit multithreading involves the deliberate creation, management, and

synchronization of multiple threads by the programmer within the code.
• Example: A programmer using threading libraries or APIs (such as pthreads in C/C++ or Java's
Thread class) explicitly creates threads, controls their execution, and synchronizes their
interaction using constructs like mutexes, semaphores, or barriers.
• Significance: Explicit multithreading gives developers more control and fine-grained management
over concurrency, allowing for optimized performance and handling of complex tasks that
benefit from parallel execution.

Comparison:
Implicit: Automates thread creation and management, simplifying development for certain tasks but
offering less control to the programmer.

Explicit: Provides full control over thread creation, synchronization, and management, allowing for
optimized concurrency but requiring more effort and careful handling by the programmer.
Q. What is pipelining? Explain structural hazard, data hazard and control hazard

Pipelining is a CPU design technique that enhances performance by allowing multiple instructions to
overlap in execution stages. It breaks down the instruction execution into smaller stages, allowing
different stages of different instructions to be processed simultaneously.
Understanding and mitigating hazards in pipelined architectures are critical in optimizing CPU
performance. By identifying and addressing these hazards, designers can enhance pipeline efficiency,
reduce stalls or delays, and improve overall CPU throughput, making the execution of instructions more
efficient and faster. Successful hazard management leads to better resource utilization and maximizes
the benefits of pipelining in computer architecture and organization.
Structural Hazard:

• Description: Structural hazards occur when the hardware resources required to execute
instructions are not sufficient or are shared among multiple instructions.
• Example: In a pipeline, if two instructions need access to the same resource at the same time
(e.g., memory or a functional unit), a structural hazard arises, causing a delay or preventing
simultaneous execution.
• Solution: Structural hazards are often resolved by duplicating or adding resources, implementing
hardware interlocks, or scheduling instructions to avoid conflicts.
Data Hazard:

• Description: Data hazards occur when there is a dependency between instructions that prevents
the proper execution order or data availability.
Types:

• Read After Write (RAW): Occurs when an instruction tries to read data before a previous
instruction that writes to the same data has completed.
• Write After Read (WAR) and Write After Write (WAW): Less common but involve similar
dependencies.
• Solution: Data hazards are addressed using techniques like forwarding (bypassing), stalling
(inserting NOPs to delay instructions), or reordering instructions to avoid dependencies.
Control Hazard:

• Description: Control hazards arise from changes in the flow of control (e.g., branches, jumps, or
conditional instructions) that affect the normal sequential execution of instructions.
• Causes: When a conditional branch instruction is being executed, subsequent instructions are in
the pipeline. If the branch outcome is determined later in the pipeline, it might lead to incorrect
instruction fetches and wasted cycles.
• Solution: Techniques like branch prediction, speculative execution, or delayed branching are used
to mitigate control hazards by predicting or preparing for branch outcomes in advance.
Clustering involves the grouping of multiple computers or systems to work together as a single unit,
often interconnected via a network, sharing resources and collaborating on tasks. There are two primary
types of clusters: high-availability clusters and high-performance clusters.
Benefits of Clustering:
High Availability:

• Fault Tolerance: Clustering provides redundancy, allowing continued operation even if one node fails.
• Load Balancing: Distributes workloads among nodes, preventing overload on individual systems.
Scalability:

• Linear Scalability: Adding nodes to a cluster can enhance performance and capacity linearly,
supporting increased computational demands.
Performance Enhancement:

• Parallel Processing: Clusters leverage parallelism, enhancing performance for complex computations
and large-scale data processing.
• Specialized Tasks: Allows for specialization, where specific nodes can handle specialized tasks or
services, optimizing performance.
Resource Sharing:

• Shared Resources: Resources such as storage, memory, or processing power can be shared among
cluster nodes, improving resource utilization.
Configuration and Operating System Design Issues:
Hardware Configuration:

• Homogeneous vs. Heterogeneous Nodes: Choosing between using identical hardware across nodes
(homogeneous) or diverse hardware configurations (heterogeneous) affects compatibility and
performance.
Networking and Communication:

• High-Speed Interconnects: Optimal network infrastructure is crucial for communication between

nodes, often utilizing high-speed interconnects like InfiniBand or Ethernet.
Cluster Management:

• Software Management Tools: Effective cluster management tools are required for node monitoring,
resource allocation, and fault detection.
Operating System and Software Support:

• Compatibility: Ensuring compatibility and support for clustered systems within the operating system
and software applications is vital.
Q. What are some of the potential advantages of an SMP compared with a uniprocessor.

Symmetric Multiprocessing (SMP) refers to a computer architecture that utilizes multiple processors or
cores within a single system, sharing the same memory and bus system.
Understanding the advantages of SMP is crucial for designing systems that can handle increasing
computational demands efficiently. SMP architectures provide a balance between performance,
scalability, and fault tolerance, making them suitable for various applications, from servers and data
centers to desktop computers and high-performance computing environments.

The advantages of SMP over a uniprocessor (single-core/single-processor system) include:

Increased Processing Power:

• Parallel Processing: SMP enables concurrent execution of multiple tasks across multiple
processors, significantly increasing overall processing power.
• Workload Distribution: Dividing tasks among multiple processors allows for efficient workload
distribution, accelerating computations and reducing processing time.

Improved Performance:

• Enhanced Throughput: SMP systems can handle more tasks simultaneously, resulting in higher
throughput and improved system responsiveness.
• Resource Utilization: Better utilization of system resources by effectively utilizing multiple cores
for multitasking, enhancing system performance.

Scalability and Flexibility:

Scalability: SMP systems are scalable; additional processors can be added to increase processing power
without significant architectural changes.
Adaptability: Adapts well to various workloads, offering flexibility to handle diverse computing
demands efficiently.
Redundancy and Fault Tolerance:
Redundancy: Offers redundancy and fault tolerance, as tasks can be migrated or taken over by other
processors in case of hardware failure or errors, ensuring system reliability.

CHAPTER 6 : _________________________________________________________________________