Synthesis

A.Input Transition:-input transition is based on previous cell

output signal performance.
Why input transition vailation?
 The circuit becomes slower.
 It may use more power.
 You might get timing violations (failures in setup/hold
checks).
How to fix input transitions vialation?
 Use a stronger gate to drive the signal faster.
 Add a buffer (a helper gate) in between.
 Make the wire shorter or better (so signal moves faster).
B.Output loads:-output load is based on the total electrical
"weight" that a gate’s output pin has to drive.
Why output loads vialations?
Fanout Load:
o The input capacitance of all gates connected to this
output.
o Example: If 3 gates are connected, their combined
input capacitance is the fanout load.
Wire Load (Parasitic Capacitance):
o The capacitance of the wire (net) that connects the
output to other gates.
 o Longer wires or lower metal layers add more
capacitance.
Via Capacitance:
o If the signal changes layers using vias, it adds a small
load.
How to fix Output Load vialations:
 Use stronger drivers (cells with higher drive strength).
 Add buffers between driver and loads.
 Reduce fanout by splitting or rerouting.
 Optimize wiring (shorter, higher metal layers)
C.Resistance:-Resistance (R) is the opposition to the flow of
current in a circuit. It's directly proportional to the length of
the conductor and inversely proportional to its cross-sectional
area.
Units:Resistance is measured in ohms (Ω).
Why Resistance violations:-
 The resistance of a wire segment or via is too high.
 It causes voltage drops (IR drop) or signal delay beyond
allowed thresholds.
 It can lead to timing failures, setup/hold violations, or
logic errors
How to Fix Resistance Violations:

1. Widen the Metal Wires

 Why: Wider wires have lower resistance.

How: Use wider routing tracks for long or high-current nets (e.g.,
clock, power).

 Tools: Modify routing constraints or manually widen in physical

tools like Innovus or ICC2.

2. Use Higher Metal Layers

 Why: Upper metal layers are typically thicker and have lower
resistance.
 How: Re-route critical nets to higher layers (e.g., from M2 to
M6).
 Use Case: Timing-critical signals, global nets, or high-current
paths.

3. Add More Vias or Via Arrays

 Why: More vias in parallel reduce vertical resistance.

 How: Use via arrays (multi-cut vias) instead of single vias
between metal layers.
 Check: Via resistance violations are common in IR drop or EM
checks.

4. Shorten Wire Length

 Why: Resistance increases with length.

 How: Optimize placement or routing to reduce net length.
 Tools: Use global/local re-routing, or buffer insertion to break
long nets.

5. Strengthen Power Delivery Network (PDN)

 Why: High resistance in power rails causes IR drop.

 How:
o Add more power straps (wider and more frequent).
o Use metal fill as part of PDN enhancement.
 o Add wider tap cells or decap cells.

6. Optimize Cell Placement

 Why: Compact, optimized placement reduces wire length and

resistance.
 How: Re-run placement optimization with better congestion
control.

7. Apply ECO Fixes (Engineering Change Orders)

 Why: Post-route fixes for localized issues.

 How: Use targeted rerouting or metal edits to address specific
violations.

D.Capacitance:-In VLSI Physical Design, capacitance is the

ability of wires, transistors, or interconnects on a chip to store
electric charge when a voltage is applied. It’s a key parasitic
effect that influences timing, power, and signal integrity.
Why Capacitance Violations Matter:
 Timing Delay: High capacitance → slow signal →
setup/hold violations.
 Signal Integrity: Coupling cap → glitches, crosstalk,
wrong logic values.
 Excessive Power: More capacitance → higher dynamic
power consumption.
 Cell Overload: Driver cells may not be strong enough →
signal corruption.
 How to Fix Capacitance Violations:
Fix Method How It Helps
Insert Buffers Break long or high-load nets to reduce
 Fix Method How It Helps
capacitance.
Split a net driving many gates into smaller
Reduce Fanout
branches.
Reroute Critical Use shorter or less congested paths to
Nets reduce wire capacitance.
Increase Wire
Reduces coupling between adjacent wires.
Spacing
Use Higher Metal These layers are thicker and farther from the
Layers substrate, so less cap.
Use stronger drivers that can handle higher
Cell Resizing
capacitance

E.transition:-
In VLSI Physical Design (PD), transition refers to the time it takes for a signal to switch from one
logic level to another logic level.

What Causes Transition Violations?

Cause Description
Weak Driver Cells Small or slow cells can't drive the load quickly.
High Capacitance
Large fanout or long wires slow down the signal.
Load
High Resistance Thin or long metal wires increase resistance,
Wires delaying the signal.
Low Metal Layer Lower metal layers have higher
Usage resistance/capacitance.
Poor Buffering Missing buffers or too far apart.

How to Fix Transition Violations:

 Fix Method Description
Replace weak drivers with stronger ones (e.g.,
Cell Upsizing
INVX1 → INVX4).
Break long nets to improve drive strength and
Insert Buffers
speed.
Reduce Shorten wire length, reduce fanout, use higher metal
Capacitance layers.
Re-route Paths Choose a faster or less loaded routing path.

F.Setup Time:-
The minimum time before the active edge of the
clock, the input data should be stable .data should not be
changed this time.
Causes of Setup Violations:

1. Long or slow data paths (high delay due to logic or

interconnect).
2. Too short clock period (i.e., very high frequency).
3. Large capacitive load on the path.
4. Improper cell sizing or slow cells.
5. Clock skew (clock arriving late at the destination flip-flop).

How to Fix Setup Violations:

Fix Strategy Description

Buffer Insertion Break long nets to reduce delay.
Cell Upsizing Replace slow cells with faster (stronger) ones.
Logic Restructuring Optimize logic to reduce levels of gates.
Path Shortening Change placement to reduce wire length.
Clock Skew Fixing Adjust clock tree to balance data/clock arrival.
Pipelining Add flip-flops to break a long path.
G.Hold Time:-
The minimum time after the active edge of the clock,
the input data should be stable .data should not be
changed this time.
Causes of Hold Violations:
Cause Description
Short/fast data The signal travels too quickly to the next
paths flip-flop.
Clock reaches the destination flip-flop
Clock Skew
before the source flip-flop.
Strong driving
Very fast drivers reduce the delay too much.
cells
Low capacitance Very little load = very fast signal
paths propagation.
How to Fix Hold Violations:
Fix Method What It Does
Add Delay Slows down the data path just enough to meet
Buffers the hold requirement.
Increase Wire
Longer routing paths = more delay.
Length
Use Smaller
Slower cells in the data path add delay.
Cells
Adjust clock tree so that the clock reaches the
Fix Clock Skew
capture flip-flop later.
H.Fanin:-
The fanin means number of inputs to a gate or node.
Why Fanin Violations Are a Problem:
 Increased Input Capacitance → Slows down drivers
(upstream cells).
 Timing Violations → Higher delay from gate input
capacitance.
 Signal Integrity Issues → More chance of noise or
glitches.
 Library Cell Limitations → Standard cells support only
a limited number of inputs (e.g., 4-input NAND, not 10-
input NAND).
How to Fix Fanin Violations:
1. Logic Decomposition:
o Break large logic cones into smaller trees (e.g., 8-

input AND → two 4-input ANDs).

2. Insert Buffers/Inverters:
o To isolate load and reduce capacitance.

3. Change RTL/Logic:
o Modify your code or constraints to reduce wide logic

expressions.
4. Re-synthesize with Constraints:
o Use max_fanin constraints in the synthesis tool.

I.fanout:-
The fanout means number of outputs to a gate or node.
Why Fanout Violations Matter:
1. Increased Capacitance:
o More load → higher capacitive load → slower signal

transitions.
2. Timing Degradation:
o Slower signal rise/fall times → possible setup/hold

violations.
3. Drive Strength Limits:
o A gate may not have enough strength to reliably drive

many loads.
4. Signal Integrity Issues:
o Noise, glitches, or degraded logic levels.

5. How to Fix Fanout Violations:

 Fix Method Description
Add buffers or inverters to break fanout load
Buffer Insertion
and isolate it.
Divide the load into two or more groups,
Load Splitting
each driven by separate drivers.
Stronger Drive Replace the gate with a higher drive strength
Cells version (if available).
Clock Tree Special handling of clock nets to balance and
Synthesis buffer high fanout clocks.
RTL Reduce signal sharing or rework logic to
Optimization distribute the load.

Synthesis topics

1. Reason's for delay:-

Optimization:- Optimization is the step in the synthesis
process that can be implemented a combination of
library cells that can meet the functional, timing, area,
and power requirements of the design.

In this optimization stage that can meet the functional,

timing, area, and power requirements of the design.
During the timing optimization some timing path are
violates setup or hold time because the total delay from
start point to endpoint is too long (or too short, in the
case of hold).
Why a Path Has Delay:-
*in this timing part "svt cells" is place
*in this timing path "drive strengt" have low
*in this timing path "net length" have high(due to
blockage's)
*in this timing path to travel the "congestion" area or not
*in this timing path "Cell delay also depends up on the
input transition and output load"
*wires delay also depends up on the resistance and
capacitance (RC delay)

How to Fix Path Delays:-

*to covert the svt cell's into the lvt cell's or ulvt cell's is
called vt swaping
*increase drive strength
*use better routing
*reorder placement
*pipelining
*Retiming

2.thershold voltage type's or vt types:-

VT (Threshold Voltage) cells are used in VLSI circuits
because of to balance the performance and power
consumption. Different VT cells help to be optimize
speed, leakage, and timing(ppa).
they are few types of vt cell's is depends up on the
technology.

technology node is depends up on the channel length.

channel length means source to drain between the length

svt means standard thershold voltage

lvt means low thershold voltage
ulvt means ultra low thershold voltage
uulvt means ultra ultra low thershold voltage
area like one and gate and not gate to optimized to the
nand gate.
delay means down to up like uulvt cell has low delay svt
cell has high delay.
leackage means up to down like svt cell has low
leackage uulvt has high leackage.

3.multiple instace:-
When we are observing the top level design if we find
any block or module is repeated multiple times, then we
will uniquify the multiple block or module to one and use
multiple time whenever it needed.
That means" create once and use multiple times."

Resolving Multiple Instances:-

*Uniquify Method:-
The tool automatically uniquifies designs during
compilation stage.
You can manually run this "uniquify" command to
enforce this before compilation stage.
Can increase compile runtime since the tool re-uniquifies
during compilation.
*Compile-Once-Don't-Touch Method:-
Uses the set_dont_touch command.
Purpose: To preserve a compiled subdesign, so it's not
altered while compiling the rest of the design.
*Ungroup Method
Uses the ungroup command
pose: To remove the design hierarchy
Benefits of Multiple Instances:-

1.Modularity & Reusability – Allows efficient reuse of

verified design blocks, reducing development time.
2.Optimized Area Utilization – Helps in balancing logic
distribution across the chip, improving floorplanning.
3.Improved Timing Closure – Enables better timing
optimization by isolating critical paths within instances.
4.Power Efficiency – Facilitates multi-VT cell usage,
optimizing power consumption.
5.Scalability – Supports hierarchical design approaches,
making large-scale ASIC designs more manageable.

4.path group or group path:-

Path grouping in synthesis is a technique used to

prioritize different timing paths for optimization. It
ensures that critical paths receive more attention while
less important paths do not interfere with optimization
efforts.
1. advantages of path group:-
Separates Critical Paths ? Ensures high-priority paths get
optimized first.
Improves Timing Closure ? Helps synthesis tools focus
on key paths.
Avoids Blocking ? Prevents less critical paths from
affecting optimization.
Improve Power effience
Area Optimization.
Reduced congestion
2.disadvantages of path grouping:
Debugging Complexity:
  If a timing violation occurs within a grouped path, it
may take extra effort to identify the exact path
causing the issue.
 Can lead to longer debug cycles during timing
closure.
Tool Dependency and Limitations
 The effectiveness of path grouping depends heavily
on EDA tool capabilities.
 Not all tools handle complex grouping scenarios
well, which might lead to analysis gaps or
inefficiencies.
2. Types of Path Grouping
A. Default Path Grouping
The synthesis tool automatically groups paths based
on clock domains.
Includes setup and hold paths associated with each clock.
B. Manual Path Grouping
Designers manually define path groups using
commands like group_path.
Helps prioritize critical paths for better optimization.
C. Weighted Path Grouping
Assigns weights to different path groups to control
optimization effort.Higher weight means more focus on
that path during timing closure.
3. How to Apply Path Grouping in Synthesis
 Using group_path Command in Synopsys Design
Compiler
group_path -name data_bus -from [get_ports in] -to
[get_ports out] -weight 2
group_path -name control_logic -from [get_portsclk] -to
[get_ports enable] -weight 3
data_bus ? Prioritizes paths from input to output.
control_logic ? Focuses on clock-to-enable paths with
higher weight.
5.Critical Path Resynthesis:-

In VLSI design, the critical path is the longest delay

path in a circuit that determines the maximum operating
frequency. If this path has excessive delay, it limits the
overall performance of the chip.Resynthesis involves
modifying the circuit to reduce delay and improve timing
closure.
*Reasons for Critical Path Resynthesis
Timing Violations ? Setup or hold violations due to
excessive delay.
Performance Bottlenecks ? Slow paths limiting the
clock frequency.
Power Optimization ? Reducing dynamic power by
optimizing logic.
Area Constraints ? Minimizing unnecessary logic while
maintaining performance.
*Techniques for Critical Path Resynthesis
 A. Gate Resizing
Adjusting transistor sizes to improve drive
strength.
Larger gates reduce delay but increase power
consumption.
B. Logic Restructuring
Reorganizing logic gates to minimize depth and
reduce propagation delay.
Example: Replacing complex combinational logic
with optimized structures.
C. Buffer Insertion
Adding buffers to balance signal propagation and
reduce transition delay.
Helps in fixing hold violations and improving signal
integrity.
D. Path Replication
Duplicating critical paths to distribute load and
reduce fan-out delay.
Example: Replicating high-fan-out drivers to
improve timing.
E. Multi-VT Cell Optimization
Using Low-VT (LVT) cells for speed and High-
VT (HVT) cells for power savings.
Helps in balancing performance and leakage power.

6.DRC'S concept:-
 Design Rule Check (DRC) in VLSI ensures a chip
design meets the manufacturing constraints defined by
the process technology

drc's divided in to two types

a.physical drc
b.timing drc
this drc's divided in to subdivideds
a.physical drc's
.open's
.short's
.danglings

b.timing drc's
A.maximium transition's: Transition time (also
called slew) is the time it takes for a signal to change
from low to high or high to low.
Why Maximum Transition Matters in Physical Design:
1. Signal Integrity Risks:
o Slow (large) transitions increase sensitivity to noise

and crosstalk.
2. Timing Accuracy:
o Transition time affects propagation delay. If it’s too

large, timing models (e.g., NLDM) become

inaccurate.
3. Power Issues:
o Long transitions increase short-circuit power as

transistors remain in the linear region longer.

How to fix maximum transition violations:-
*buffer insertion
*cell upsizing
*wire optimization
B.maximium capacitance
.maximium resistance
.fan_in
.fan_out

7.compile strategies:-

compile means:-to convert the rtl code into gate

level netlist. we can use the following strategies in
Design Compiler for compiling hierarchical designs
*Top-Down Compile:
the top-level design and all its subdesigns are
compiled together
*bottom-up compile:
the individual subdesigns are compiled separately
startins from the bottom of the hierarchy and proceeding
up through the levels of the hierarchy until the top-level
design is compiled
*mixed compile:
the top-down or bottom-up strategy which ever is
most appropriate is applied to the individual subdesigns.
8.process of synthesis (or) synthesis flow:-

DEFINITION:
Synthesis is a process of converting RTL/HDL code
into gate level netlist.that can be implemented on silicon.

Rtl: register transfer level

Hdl: hardware description language
Gate level netlist:-the gate level netlist is a logical
connectivity information of the design.like standard
cell’s,macro’s,pin’s,wire’s,port’s,module’s related
information is present.,

INPUTS FOR LOGIC SYNTHESIS:

RTL/HDL code (Designer)
Library(lef)– contains cell characteristics (Foundry)
Synopsys Design Constraints –(SDC) (Designer)
Unified Power format –(UPF)(Designer)
Scan config file
DEF

OUTPUTS FOR LOGIC SYNTHESIS:

Gate - level netlist
Scan def – information of scan flop
s and their connectivity in scan chains
SDC
UPF
 synthesis flow:-translation+mapping+optimization

translation:-Convert the code into Generic tech library

cells which are technology independent cells .This
process is called Translation.

mapping:-The Generic tech library cells converts into

technology dependent cells.

optimization:-Optmization is the step in the synthesis

process that implements a combination of library cells
that meet the functional, timing, area, and power
requirements of the design.

types of synthesis:-
a.physical aware synthesis(with .def)

b.logic-aware synthesis(with out .def)

Logic-Aware Synthesis (LAS):-

Converts RTL code into a gate-level netlist without
considering physical constraints.
• Focuses on functional correctness, timing, and area
optimization using standard cell libraries.
• One-Pass Approach: The synthesis process primarily
focuses on timing, area, and power in a single step,
treating physical constraints as secondary.
• Uses wire-load models to estimate interconnect delays.
• Tools: Typically performed using Design Compiler
(DC).
• Output: After LAS, the design might need further
physical optimization or multiple iterations with place-
and-route tools for improved timing closure.

Physical-Aware Synthesis (PAS):-

•Incorporates floorplan information to improve timing
correlation with physical design.
• Focus: Integrates physical constraints (such as
congestion, placement, and routing) from the start.
• Two-Pass Approach: 1. First pass – Optimizes logic
functions similar to LAS. 2. Second pass – Adjusts
design considering placement, congestion, and routing
impacts.
• Tools: Performed using Innovus (Cadence) or IC
Compiler II (ICC2 - Synopsys), which account for both
logical and physical optimizations.

9.auto ungrouping:-

In Very-Large-Scale Integration (VLSI) design, auto-

ungrouping is a technique that removes hierarchical
boundaries within a design, effectively flattening the
design hierarchy during the synthesis process. This
flattening can lead to improvements in timing, area
efficiency, and overall design optimization.
Benefits:-
Improved Timing: By reducing logic levels, ungrouping
can lead to faster signal propagation and better timing
performance.
Enhanced Area Efficiency: Ungrouping allows for better
sharing of logic elements across different blocks,
potentially leading to more efficient utilization of chip
area.
Streamlined Optimization: A flattened design hierarchy
can facilitate more effective optimization by synthesis
tools.
‘
10.magnet placement:-

the magnet placement is used to whole hierchi.

11.retiming:-
Retiming in synthesis is a sequential optimization
technique that rearranges registers in a circuit to improve
performance without altering the input/output behavior.
Why Retiming is Important:-
Improved Timing:-Retiming can significantly
reduce the clock period by distributing timing delays
more evenly across the circuit. It shifts registers to
reduce the longest path delay, allowing for faster
operation.
Optimized Resource Utilization:-By strategically moving
registers, retiming can sometimes lead to a smaller
overall design area, requiring fewer resources.
Enhanced Performance:-It's a powerful optimization
technique that can improve performance by reducing
critical path delays and balancing timing slacks.

How Retiming Works:

1. Timing Analysis:-The synthesis tool first analyzes the

design, identifying critical paths (those with the longest
delays) and their associated slack.
2. Slack Calculation:-The timing slack on each register
is calculated, revealing areas where timing delays can be
redistributed.
3. Register Relocation:-The synthesis tool then
intelligently moves registers, either forward (towards the
input) or backward (towards the output), to balance the
slack and reduce critical path delays.
4. Iteration:-Retiming can be performed iteratively, with
the synthesis tool continuously analyzing and optimizing
the circuit until the desired performance goals are met.

Backward Retiming:
Moving registers towards the output of a combinational
logic block (called backward retiming)

Forward Retiming:
Moving registers towards the input of a combinational
logic block (called forward retiming)

12.scan insertion:-
is a key step in Design for Testability (DFT), where scan
chains are added to a design to improve testability by
enabling controllability and observability of internal flip-
flops.
Steps in Scan Insertion
1.Replace Flip-Flops with Scan Flip-Flops
Standard flip-flops are replaced with scan-enabled flip-
flops that include a multiplexer for test mode.
2.Connect Scan Chains
Flip-flops are linked into scan chains, forming shift
registers for test pattern application.
3.Define Scan Mode
The design operates in functional mode during normal
operation and scan mode during testing.
4.Insert Test Access Points
Dedicated scan-in and scan-out ports allow test patterns
to be shifted in and out.
5.Timing Optimization for Scan Paths
Ensure scan paths do not introduce excessive delays
affecting functional timing.
Example Scan Chain Connection
always @(posedge scan_clk)
if (scan_enable)
scan_out <= scan_in;
This ensures that during scan mode, test patterns
propagate through the scan chain.

13. PIPELINING:-
Pipelining in synthsis is a technique used to improve
circuit performance by breaking long combinational
paths into multiple stages with registers. This reduces the
critical path delay and allows higher clock frequencies.

Steps for Pipelining in Synthesis

*Identify Long Combinational Paths

Use timing analysis to find paths with excessive delays.
Focus on paths that limit the achievable clock frequency.

*Insert Pipeline Registers

Place registers at intermediate points in the logic path.
Ensure that data dependencies are maintained.

*Modify RTL Code

Introduce additional registers in the design manually.
Use synthesis directives to infer pipeline stages.

*Use Synthesis Tools for Optimization

Enable automatic pipelining in tools like Synopsys
Design Compiler or Xilinx Vivado.
Example command in Synopsys
set_pipeline true
compile_ultra –pipeline

*Verify Timing and Functionality

Check setup and hold time constraints
Perform logic equivalence checking to ensure
correctness.