Module 1: The Intel Microprocessors 8086 Architecture

Q.1 Draw and explain Write operation and Read operation Timing diagram of 8086 Processor in
Maximum mode. (May 2024) (10M)

*Q.2 Draw and explain the interrupt structure of the 8086 processor(IVT) and differentiate between
Hardware and Software interrupts. (May 2024) (10M)

Q.3 Draw and explain architecture of 8086. (May 2024) (10M)

Q.4 Explain the maximum mode of 8086. [10M] (May 2023)

**Q.5 Draw the timing diagrams for Read and Write operations in minimum and maximum mode.
[10M] (May 2023)

Q.6 What are the advantages of Memory banking in 8086. [5M] (Dec 2023)

Q.7 Explain the interrupt structure of 8086. [10M] (Dec 2023)

Module 2: Instruction Set and Programming

Q.1 Explain the following instructions: STOSB, DAA related to 8086. [5M] (May 2023)

Q.2 Explain the following instructions: XLAT, DAA, LAHF, AAA related to 8086. (May 2024) (5M)

Module 3: Memory and Peripherals interfacing

*Q.1 Design 8086 microprocessor-based on following Specifications: (May 2024) (10M)

**Q.2 Explain the Initialization command words (ICWs) and Operational command words(OCWs) of
the 8259 PIC. (May 2024) (10M)

Q.3 Explain Modes of 8255 with a neat block diagram. Show the CWR initialization. (May 2024)
(10M)

Q.4 Interface DMA controller 8257 with 8086 MP. Explain different data transfer modes of 8257
DMAC. [10M] (May 2023)

Q.5 Explain 8255 with a block diagram and its operating modes [10M] (May 2023)

Q.6 Design 8086 microprocessor-based on following Specifications: (May 2024) (10M)

Q.8 Explain 8257 DMA Controller with the help of neat diagram and explain its control register
format. [10M] (Dec 2023)

Q.9 Design 8086 microprocessor based system working in minimum modewith the following
specifications.
I. 8086 microprocessor working at 8 MHz.
II. 16 KB EPROM using 8K devices.
Clearly show memory map with address range. Draw a neat schematic [10M] (May 2022)

Module 4: Intel 80386DX Processor

*Q.1 Differentiate between real Mode , Virtual Mode and Protected Mode of 80386 Processor
.Explain the Floating point Pipeline of Pentium Processor. (May 2024) (10M)

*Q.2 Discuss in brief the protection mechanism of 80386DX. [5M] (May 2023)

Q.3 Explain the Register organization of 80386. [10M] (May 2023)

Q.4 Draw and explain the master slave mode of 8259 Processor with suitable example. Consider
Slave 8259 connected to IR0 and IR4 of master. [10M] (Dec 2023)

Q.5 Explain segment descriptor in 80386. [10M] (Dec 2023)

Q.6 Explain the EFLAG register of 80386. [10M] (Dec 2023)

Q.7 Explain descriptors and paging mechanism in protected mode of 80386? [10M] (May 2022)

Module 5: Pentium Processor

*Q.1 Explain MESI Protocol. (May 2024) (10M)

Q.2 Explain in brief cache organization of Pentium processor. [10M] (May 2023)

Q.3 Explain the floating point pipeline of pentium processor. [5M] (Dec 2023).

Q.4 Explain the branch prediction mechanism of 80386 processor. [10M] (Dec 2023)

Q.5 Explain Integer and Floating-Point Pipeline of Pentium. [10M] (May 2022)

Module 6: Pentium 4

*Q.1 Comparison 80386 ,Pentium 1 ,Pentium 2 and Pentium 3 Processor. (May 2024) (10M)

*Q.2 Draw and explain Pentium 4: Net burst microarchitecture. (May 2024) (10M)

*Q.3 Explain hyper threading technology and its use in Pentium 4. [10M] (May 2023)
Codes: ALP – Assembly Line Program.
*Q.1 Write an assembly language program for searching a Character in a Given String.(Consider your
own String). (May 2024) (5M)

Q. 2 Write an ALP for 8086 to transfer the block of data. (May 2024) (10M).

Q.3 Write an assembly language program for 8086 to exchange contents of two memory blocks.
[10M] (May 2023)

Q.4 Write an ALP for 8086 to reverse a string of 10 characters. [10M] (May 2023).

Q.5 Write an ALP for 8086 to arrange 10 numbers in ascending order. [10M] (Dec 2023)

Q.6 Write an 8086 assembly language progran to print the flag registers. [10M] (May 2022)
Module 1: 8086 Architecture

1. Timing Diagrams for Read/Write in Min & Max Mode

Always appears. Learn both diagrams clearly.

2. Interrupt Structure of 8086

Learn the IVT and hardware vs software interrupts.

3. Architecture of 8086

Appears every alternate year.

4. Minimum vs Maximum Mode

Sometimes asked alone or as part of a design question.

5. Memory Banking in 8086 (5M)

Short but asked previously.

Module 2: Instruction Set & Programming

1. ALPs (Assembly Language Programs) — must prepare these:

o Transfer block of data

o Search character in a string

o Exchange two memory blocks

o Reverse a string

o Sort 10 numbers in ascending order

o Print flag register

2. Instruction Explanations

o DAA, STOSB, LAHF, XLAT, AAA — Repeated short 5M questions

Module 3: Memory & Peripherals Interfacing

1. Design 8086-based System (with Memory Map)

Very frequent. Learn steps, address map, and chip select logic.
 2. 8259 PIC: ICWs & OCWs

Guaranteed 10M question

3. 8255 PPI: Modes, Block Diagram, CWR

4. 8257 DMA Controller: Diagram + Transfer Modes

5. Mode 2 of 8255 with Block Diagram

6. Master–Slave 8259 (IR0, IR4 connection)

More recent trend — good to prepare.

Module 4: 80386DX Processor

1. Real Mode vs Protected Mode vs Virtual Mode

2. Protection Mechanism in 80386

3. Descriptors and Paging Mechanism

4. Segment Descriptor & EFLAGS

Module 5: Pentium

1. MESI Protocol

2. Cache Organization

3. Integer & Floating-Point Pipeline

4. Branch Prediction Mechanism

Module 6: Pentium 4

1. Comparison: 80386, Pentium I/II/III

2. NetBurst Microarchitecture

3. Hyper-threading Technology
 Smart Preparation Strategy

Priority Topic Reason

Must Timing Diagrams, Interrupt Structure, ALPs, Memory Repeated and high-
Do Design, 8259 ICW/OCW, MESI, Hyper-threading weight

80386 Protection, Pentium Pipeline, 8257 DMA, Flag Recent trend or appears
Medium Register ALP, 8255 CWR every 2–3 years

STOSB, DAA, AAA etc., Comparison topics Short questions / backup