1.
)TMOD SFR
For Timer-1:
GATE-1: If this is 1 then timer will run only when INT1(P3.3) is 1; If 0 timer will
work normally
C/T1: If this is 1, counter (counts events on P3.5) else timer
T1M1, T1M0: Timer mode bits
For Timer-0:
GATE-0: If this is 1 then timer will only run when INT0(P3.2) is 1; If 0 timer will
work normally
C/T0: If this is 1, counter (counts events on P3.4) else timer
T0M1,T0M0: Timer mode bits
Points to remember:
a.) Timer-1: Gate is INT1(P3.3) and counter pin is (P3.5)
b.) Timer-0: Gate is INT0(P3.2) and counter pin is (P3.4)
c.) INT1 => External Interrupt-1; INT0 => External Interrupt-0
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2.)Timer Modes
MSB LSB
0 0 13 Bit Timer
0 1 16 Bit Timer
1 0 8 Bit auto-reload
1 1 Split Timer Mode
--------------------------------------------------------------------------
3.)TCON SFR
TF1,TF0: Timer Overflow
TR1, TR0: Timer Run; Make this 1 to start the timer
IE1,IE0: External interrupt Edge flag. Set to 1 when a high-to-low edge signal is
received on port 3.3 (INT1) and 3.2 (INT0) {Respectively}. Cleared by hardware when
processor services the interrupt routine at program address 0013h, 003h
{Respectively}.
IT1, IT0: Interrupt Type Control Bit. Set to 1 using program to enable external
interrupt pins (INT1,INT0 respectively) to be triggered by a falling edge signal.
Set to 0 using program to make the interrupt level sensitive i.e. if input to INT1,
INT0 is low (i.e. 0), treat it as an interrupt
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4.) Timer Modes Details:
Timers increment every machine cycle while counter increment after every two
machine cycles (given that there was an event in those two machine cycles)
4.1) 13-Bit Timer
All 8 bits of THx used while lower 5 bits of TLx is used. Higher 3 bits of TLx are
indeterminate. Everytime TLx overflows 32, THx is incremented. Overflow triggered
when THx is overflowed
4.2) 16-Bit Timer
Both THx and TLx are cascaded with THx as the higher byte. When THx overflows, the
overflow flag is set
4.3) 8-Bit Auto Reload
THx is set to a given value via the program. When TLx overflows, the overflow flag
is triggered and the vale stored in THx is loaded into TLx
4.4) Split Timer Mode (HERE TIMER-0,1 BEHAVE SEPARATELY)
TL0 and TH0 operate as separate 8-bit. TL0 uses the Timer 0 control bits C/T0# and
GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0
is locked into a
Timer function (Normal Increment per machine cycle) and takes over use of the Timer
1 interrupt (TF1) and run control (TR1) bits. Thus, operation of Timer 1 is
restricted when Timer 0 is in Split Timer Mode
Placing Timer-1 in mode-3 will cause it to Halt and hold its count
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5.) Explanation of Code given in slides
5.1) Square Wave Generator
| MOV TMOD, #01
| LOOP: MOV TL0, #0EEH
| MOV TH0, #0FFH
| CPL P1.0
| ACALL DELAY
| SJMP LOOP
| DELAY: SETB TR0
| AGAIN: JNB TF0, AGAIN
| CLR TR0
| CLR TF0
| RET
TMOD set to #01 => Timer-0 Mode-0 = 1 rest all bits =0 => Timer-0 in 16 Bit
counting mode
The codes sets TL0 to 238 and TH0 to 255 and then starts the timer. Thus after 256-
238 = 18 machine cycles, TF0 will be set to 1. Once this is done it will clear the
timer run flags and the overflow flag and then again load 255,238 into TH0,TL0 and
start the timer again. Ignoring instruction delays, the time period of square wave
will be 36 machine cycles
5.2) Measurement of Execution Time
| ORG 0H
| MOV TMOD, #16H ;initialization
| SETB TR0 ;starting timer 0
| … ;main
| … ;program
| CLR TR0 ; stop timer 0
| MOV R7, TH0 ; reading timer 0
| MOV R6, TL0
TMOD set to #16H => Timer-0 Mode bit = 6 = 0110 => 8 Bit Auto Reload Counter?!
(Sus, Doubt)... ideally it should set Timer-0 to a 16-bit timer and then simply
start it
