ww Ak QUESTION BANK SOLUTION OF MICROPROCESSOR S.ESEMAV BRANCH: COMPS/AIML/DS/IOT |UMMER SESSION 2025 ‘Ans: Minimum Mode The working of min mode can be easily understo All processors bus cycle is of at least 4 T- focessor in the T1 state. It is available on the bus © In Tz, the bus is tristated for changing the cycle.) © The data transfer takes place be and Ta. ALE Add/Status Read timing diagram is slower, then the wait state is inserted between Ts and Ts. indicate that valid address is latched on the address bus also M/I0 =1, licates the memory is in progress, ress is removed from the local bus and is sent to the address devices. Then bus is. tristated, ‘© During T2 DEN = received. ), which enables transceivers and DT/R = 0, which indicates that the datas © During Ts, data is put on the data bus and the processor reads it.= The output devices makes the READT line high. This means the output devices has performed the data transfer process. When the processor makes the read signal to 1, then the output evices wil again trstate its bus drivers ee pag L seursi wre Den" tes of memory or 1/0 word. , which indicates that the data is Read Operation1cessors to 8086 (8087/8089), lementation of allocation of global resources and passing second processor in the system), because two processors, bbus at same instant. their own program. Circuit Explanation |) When MIN/MX = 0 , 8086 works in max mode, li) Clock is provided by 8284 clock generator. iii]8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three such latches are required because address bus is 20 bit. The ALE (Address latch enable) is connected to STB(Strobe) of the latch. The ALE for latch is given by 8288 bus controller. a_iabe es eel ee i iv) The data bus is operated through 8286 because data bus is 16-bit. Thestransceivel data is controlled by the OT/ T. Both DEN and DT/R are given bus controller. Mode, when MN/MKX = 1 the only processor in the system. The Minimum Mode circuit of 8086 iv) Address from the address bus is latched into 8282 8-bit latch. Three such latches are needed, as address bus is 20-bit. The ALE of 8086 is connected to STB of the latch. The ALE for this latch is given by 8086 itself. vv) The data bus is driven through 8286 8-bit trans-receivers. Two such trans-receivers are needed, as the data bus is 16-bit. The trans-receivers are enabled through the DEN signal, while the direction of data is controlled by the DT/R signal. DEN is connected to OE and DT/R is connected to T. Both DEN and DT/R are given by 8086 itself.DEN | OT/ Action 1 X__| Transreceiver is disabled 0 0 Receive da o 1 Transmit data vi)Control signals for all operations are generated by decoding M/"IO , “RO and “WR signals. mio | RD | we Action 1 0 | 1 [Memory Read 1 1 [0] Memory Write 2 0 {1 {io Read o [0 [vo wine: decoder like IC 741: vii) M/"I0 , “RD and “WR are decoded by a 3: Using the HOLD and HLDA signals. vill) “INTA is given by 8086, in response to an interrupt on INTR line. mn —_ AL ya S} ADA bee se vi) Any of the ICW commands can not be repeated, but the entire initialization process can be repeated if required Initialization sequence of 8259:(1) ICWs command: ‘© The control word is recognized as ICW: w) ‘+ Ithas the control bits for Edge and level interval and whether ICW4 is required ‘+ Address lines Ay to As are ust (2) Icws command: IcW3 commal In one 8259 present in the system i.e. when ad &-bit slave register. of interrupt mode is selected, a special fully nested mode is selected. Operating command words (OCW): i) OCW is given during the operation of 8259 i.e. microprocessor starts using 8259. ii) OCW commands are not compulsory for 8259. ill) The sequence order of giving OCW commands is not fixed. iv) The OCW commands can be repeated.(1) cw ts used to set and reset the mask bits in IMRlinterrupt mask register). My ~ Mo deseribe mask bits oom, [As Tor Joe Jos fou _fos_z__[os_[oe_] (2) ocws: It is used for selecting the mode of operation of 8259, Here L; to Laat level on which action need to be performed. _ nd of ntrapt a ‘Specie rtaion ecial mask mode ) bitis set, then the SMM bit is don’t care. If 3259 will enter in Special mask mode. 9 will return into normal mask mode. Loa =‘Ans: The integer pipeline of the Pentium processor consists of five stages: i) Instruction Fetch (IF): Fetches the instruction from memory. li) Instruction Decode (ID): Decodes the instruction and determines the required operations. lliJExecution (EX): Executes the operation specified by the instruction. Iv)Memory Access (MEM): If necessary, accesses memory for data. vv) Write Back (WB): Writes the result back to the register file. Floating point Pipeline of Pentium processor: ‘The floating-point pipeline of the Pentium processor is responsible for e} arithmetic operations. It consists of several stages thathandle different asp computation i) Instruction Decode: In this stage, the pr instruction and prepares it for executior sto the main routine where it was interrupted. different typ \terrupts present in the 8086 microprocessor are given by: Hardware pts and Software Interrupts pterrupts: Hardware interrupts are those interrupts that are caused by any ice by sending a signal through a specified pin to the microprocessor. There are peripheral two hardware interrupts in the 8086 microprocessor. They are: © NMI (Non-Maskable Interrupt): Itis a single pin non-maskable hardware interrupt that cannot be disabled. It is the highest priority interrupt in the 8086 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt. IP is loaded from word location (00008 H, and CS is loaded from the word location 0000A H. ‘* INTR (interrupt Request): It provides a single interrupt request and is activated by the I/O port. This interrupt can be masked or delayed. It is a level-triggered interrupt. It canterrupt type, so the value of IP and CS will charge an the interrupt 2) Software Interrupts - These are instruction inserted within the program to generate interrupts. There are 256 software interrupts in the 8086 microprac the format INT type, where the type of range fram 00 to FF. The starting address ranges from 00000 H O03FF H. these are 2-byte instructions. IP is loaded fram type *04 H, anid C5 is landed from the following address given by (type ° 04) + 02 H. Some Important software in ot. The instru frupts ar * TYPE 0 corresponds to division by zero(0), ‘* TYPE 1 is used for single-step execution for debugging the pro} ‘© TYPE2 represents NMI and is used in power failure conditions, ‘© TYPE3 represents a break-point interrupt. TYPE 4 is the overflow interrupt. ‘Ans: DMA stands for Direct Memory Access. If the CPU. The functional Block Diagram of DMA: follows: It consists of five fu a) Data bus buffer Sd ream fF OROe oe fo08 | oxexy me St nan Lol ea ore =e oR | ome Aol ee urn is & a aia [cpa o eat x 828 |p oexe B Heol cone ie wana ol Bay foros EER Soon ERS} soon | pox ci eo 1c ra wan ane rate, It allows the device to transfer ference of1) Data Bus Buffer: Iisa tristate, bi-directional, eight-bit buffer which interfaces the 8257 to the system data bus. Inthe slave mode, itis used to transfer data between microprocessor and internal registers of 8257. In master mode, it's used to send higher byte address (A8-A15) on the data bus. li) Read/Write logie: When the CPU is programming or reading one of the internal registers of Pin Diagram of 8257 (ie, when the 8257 isin the slave mode), the Read/Write logic accepts the /0 Read (IOR) or /0 Write (OW) signal, decodes the least significant four address bits (AO ~ 3) and either writes the contents of the data bus into the addressed register ((fIOW is low) or places the contents of the addressed register onto the data bus (ifIORis low) IMA cycles (Le. when ‘the 8257 isin the master mode) the Read/Write logic generates th (OMA write cycle) or/0 write and memory read {OMA read cycle) si transfer between peripheral and memory device. iti) DMA Channels: ‘The Pin Diagram of 8257 provides four identical two sixteen bit registers: 1. DMA address register, and 2. Terminal count register. ‘most significant 2 bits of the terminal med. Itis necessary to load count 1 terminal count register before nificant four bits allow four different options for the Pin Diagram of 1¢d by the CPU after initializing the DMA address registers and fs cleared by the RESET input, thus disabling all options, inhibiting al eventing bus conflicts on power-up. Vil) Status 9: As said earlier, it indicates which channels have reached a terminal count condition and includes the update flag described previously. The TC status bit, if one, indicates terminal count has been reached for that channel. TC bit remains set until the status register is read or the 8257 is reset. The update flag, however, is not affected by a status read operation. The update flag bit, if one, indicates CPU that 8257 is executing update cycle. In update cycle 8257 loads parameters in channel 3 to channel 2 vill) Priority Resolver: It resolves the peripherals requests. It can be programmed to work in two modes, either in fixed mode or rotating priority mode.Control Register Format of 8257: ‘The control register isan 8-bit register used to configure the DMA's behavior. Here's the format: Bit Description 7 Memory-to-memory transfer enable ( able, 6 Channel priority (1 = Fixed, O= Rotating). Elian Extended write enable (ised for cescodine 4 Enable or disable auto-initialization mode (1 = Enable). 3 Reserved (always 0). 2-0 Channel mask bits (1 = Mask channel, Enable channel), ‘Ans: Interface of 8257 with 8086 Microproce: Note: You can draw the diagram To interface the 8257 DMA controller followed: |) Connection of Cor Juest from the 8086 microprocessor. After the transfer, the controller waits for the next request. + Block Transfer Mode: This mode allows the 8257 DMA controller to transfer a block of data from the memory to an I/O device or vice versa, The block size and the number of blocks to be transferred are pre-programmed+ Demand Transfer Mode: Also known as the "Auto-initialized DMA mode," this mode is similar to the block transfer mode, but the 8257 DMA controller automatically reinitializes itself after each block transfer. tis useful for continuous data transfer operations. + Cascade Mode: In this mode, multiple 8257 DMA controllers are cascaded to extend the number of DMA channels available, This allows for more complex and simultaneous data transfer operations, ‘Ans: MESI Protocol Stands for (Modified, Exclusive, Shared, Invall ‘The MESI protocol is a cache coherence protocol used in multiproce: consistency between processor caches and main memory. It ensures that with inconsistent copies of the same memory block. Each cache block can exist in one of four states: 1, Modified (M) 2. Exclusive (E) 3. Shared (S) 4. Inwalid (1) 41, Modified (M) n of the data, which, from the data in 1e block is replaced or evicted, it must ii) Any Bccess to this block results in a cache miss, requiring the block to be fetched from main memory or another cache. Working of MESI Protocol: 1. Read Request: i) Ifa cache blocks in the Invalid state, a read request triggers a cache miss, and the block is fetched from memory or another cache.li) The block transitions to the Shared or Exclusive state, depending on whether other caches also have the block. 2. Write Request: i) Ifa processor writes to a block in the Shared or Exclusive state, the state changes to Modified. li) If another cache has the block in the Shared state, it transitions to Invalid (write- invalidate mechanism) 3. Coherence Maintenan When a processor modifies a block in the Modified state, invalidate their copies of the block to maintain consistency. Advantages of MESI Protocol: i) Data Consistency: Ensures all pro shared memory, li) Efficient Cache Usage: Reduces u data fetching. Disadvantages of MESI Protocol 1) Complexity: Managing multip complexity ii) Overhe performance. In this mode, Port A and Port B are configured as bidirectional das a control port for setting various operational modes. ‘only port A will work, port B can either is in mode O or 1 nal. The outputs as well as inputs are latched. It has PA mode selection ir + Vo function of PB 00: mo 1/0 fune of Pcu| 0:0 OR es O1:m1 yofunction of pA 9+0/P Lor ave 1X:m2— oop, Lie PB mode selection O:mo Limist bit (07) is 1for the /0 mode and 0 fo The most sit the port A mode. D6 D5 Mode 00) m1 Ooxean2 pais used to tell whether port Ais taking input or displ input otherwise displaying output. 13 is used to tell whether port C higher bits is ta taking input otherwise displaying output. 2. Reduces Port C availabilty. +3, Limited speed for high-performance systems. ing the result the BSR mode, DG & DSIt is used t0‘Ans: Branch prediction logic: To avoid this problem, Pentium uses a scheme called Dynamic Bran Prediction In this scheme, a prediction is made for the branch instruction currently in the pipeline The prediction will either be taken of not taken. If the prediction is true then the pipeline will not bbe flushed and no cock cyties will be lost. If the prediction is false then the pipeline is flushed and starts over with the current instruction. it is implemented using 4 way set associated cache with 256 entries. This is called Branch Target Buffer (TB). The directory entry for each line con + Valid bit: Indicates whether the entry is valid or not, + History bit: Track how often bit has been taken. Working of Branch Predicti i) BTBis a lookaside cache that sits to the side of. monitors for branch instructions. li) The first time that a branch instruction The diagram is explained by the following table:If branch taken if branch not taken Resulting Prediction Description made ‘Strongly Taken BranchTaken Remainsinsame Downgraded to weakly state taken Weakly Taken Branch Taken Downgraded to weakly not taken Upgraded to strongly ‘Weakly Not Taken Branch Not Taken Downgraded to strongly Branch Not Taken Strongly Not Taken not taken ‘Advantages of branch prediction in the Pentium: ) Improved performance ii) Increased instruction throughput Reduced branch misprediction penalty iv) More efficient use of processor resource: tages of branch predictio eased complexity (creased power consumption It is designed to interface the CPU an program the device according to Port-B, and Port-C, These ports are assigned a The block diagr‘There are two different modes of 8255. These modes are: 1. Bit Set Reset (BSR) Mode 2. Input/Output Mode 1. Bit Set Reset (BSR) Mode: This mode is used to set or reset the bits of the Port-C only. For BSR mode always D7 will be 0. The control register is looking like this The (D3, D2, D1) will be 000 to 111. In this mode it affects only one bit user set the bit, it remains set until user unset it. The user needs to load register to change the bit. 2. Input/ Output Mode: This mode is selected This mode has also three different modes. Th i) Mode 0~ Simple or basic I/O Mode jandshiaking. In this handling capability, anc Yo function of PB 70 function of PCL 1/0 func of PCU 0:0 on 0:0/° 1:0/P “e ae PA mode selection 00; m0 01:m1 4/0 function of PA 1X: m2 0:0/° vel PB mode selection 0:mg ami.12) Explain hyper threading technology and its we in Pet 4 ‘Ans: I) Hyper-Threading Technology (HTT) Is a technology developed by Intel to improve parallelization of computations performed on x86 microprocesiors Ii)italiows a single physical processor core to behave like two logical processors, enabling better performance for multi-threaded applications. ology was introduced to improve the by duplicating certain | piicating the main | {i in the context of Pentium 4, hyper threading techné processor's efficiency in handling multiple tasks simultaneously. It wa sections of the processor—those that store the architectural state execution resources. jv) His allows the processor to schedule the execution of multiple threat improved overall performance. -v) Hyper-Threading Technology (HTT) was partic ithelped to mitigate the performance limitati known for its relatively long pipeline and high vi) By enabling better utilization of the process king on active tasks costs performance in multithreaded applications like video rendering, utilizing idle CPU resources. 2) Limited Performance Gains: n CPU-intensive tasks, the performance improvement Is minimal as both threads share the same physical resources. b) Software Dependency: Applications must be optimized for multithreading to fully benelit (rom HT; otherwise, there may be no noticeable improvement,‘Ans: The Net Burst Microarchitecture was introduced in Inte!’s Pentium 4 processors high performance and higher clack speeds. It focuses on deep pipelines and efficient exec achieve System Bus Bus Unit Level 1 Data Cache Integer and FP Execution Units £ os Out-of-order Fetch’ Decode He execution —P Revrement stomente ROM ms BIB Branch Prediction setae Ourofonter Engine 1) System Bus and Bus Unit: {) Connects the processor to the rest stem (e.g., RAM, chipset). ii) Handles data t |) Include Integer and Floating-Point (FP) execution units for mathematical operations. li) Connected to the Level 1 Data Cache, which provides faster data access compared to L2 Cache. 5) Out-of-Order Execution Engine: 1) Allows instructions to be executed in a different order from their program sequence. ii) Optimizes resource utilization by reducing idle time for execution units.ii) Once executed, instructions are reordered back into sequence before retirement, 6) Retirement Unit: i) Ensures instructions are retired (committed) inthe original program order. i) Updates the processor's architectural state based on completed instructions. Key Features 1. Deep Pipeline: i) The Pentium 4 had 2 20-stage pipeline, allowing higher ii) Helps in better instruction handling but increases penalty 2. Trace Cache i) Unique to the NetBurst architecture. i) Stores decoded instructions, enabii ‘execution without de repeatedly. 3. Out-of-Order Execution: ’) Improves performanc dependencies to resolve. 4. Hyper-Threading: bling two threads the same ii) Uses 2-way set associativity for efficient data management. ill) Directly connected to the processor, providing extremely fast access. 3) Level 2 (L2) Cache: |) Unified cache that stores both instructions and data. ) Size ranges from 256 KB to 2 MB, with higher associativity (typically 4-way or more).liActs as an intermediate storage layer, faster than main memory but slower than L cache, 4) Write-Back Policy: Data is written to main memory anly when necessary, reducing memory accesses and improving performance. 5) MESI Protocol: Ensures eache coherency in multiprocessor environments by maintaining data consistency using Modified, Exclusive, Shared, and Invalid states 6) Data Access Hierarchy: i) The processor first checks the L1 cache for data. li) Nf data isnot found, checks the L2 cache, Ui) Only if data is absent in both caches does the processor access mi 7) Performance Optimization: This multi-level caching system minimizes used data, significantly improving overall system, ‘Ans: Memory Banking of 8086 In Micropro 1emory banking allows the microprocessor to access multiple banks of {can improve the performance of memory-intensive applications by I) Cost-Effective: Memory banking can be a cost-effective way to increase the memory capacity of a microprocessor. Instead of using expensive, high-density memory modules, memory banking allows the use of multiple, smaller memory modules.Ans: The 80386DX microprocessor indudes a rabust protection mechanism to ensure the integrity and security of system operations, 1. Segmentation-Based Protection: ‘The 80386DX uses segmentation to divide memory into segments, each with specific attributes like base address, size, and access rights. This ensures that processes cannot access ‘memory outside their allocated segments. 2. Privilege Levels: ‘The processor supports four privilege levels (0 to 3), where leve (kernel mode) and level 3 is the least privileged (user mode). Thi: system resources based on the privilege level of the executing code, 3, Descriptor Tables: ’) Global Descriptor Table (GOT): Contains descriptors for global seg tasks, ‘These tables define sey 4, Paging Protection: its own access jemory regions.Ans: Descriptor Mechanism in Protected Mode: 1. In protected mode, the 80386 microprocessor uses descriptors to manage memory segments. Each segment is defined using a Segment Descriptor, which provides details about the segment's location, size, and access permissions, 2. A Segment Descriptor is a 64-bit entry stored in the Global De: Descriptor Table (LOT). It contains: Table (GOT) or the Local i) Base Address: Indicates the starting address of the segment ii) Segment Limit: Defines the size of the segment. i) Access Rights: Specifies the type of se allowed (read, write, execute). fe, data, or syste iv) Flags: Includes additional properti¢s like granularity and privilege le 3, Tables for Descriptors: ii) LOT (Local Descriptor Table} 4, Role of Descriptors: ining pointers to Page Tables. jins entries mapping virtual pages to physical frames. i) Page Directory Index: Identifies the entry in the Page Directory. ii) Page Table index: Identifies the entry inthe Page Table. il) Page Offset: Points to the exact location within the page. 4, Paging is enabled by setting the Paging (PG) bit in the CRO control register. The CR3 register holds the base address of the Page Directory. 5, Benefits of Paging|) Virtual Memory: Allows the use of more memory than physically vailable by swaoping pages between RAM and secondary storage. fi) Memory Protection: Ensures processes cannat access pages belonging to other Processes, {il) Non-Contiguous Allocation: Reduces fragmentation by allocating pages independently 6. Role in Protected Mode: Paging works alongside segmentation to provide a robust memory management system, enabling multitasking, isolation, and efficjgnt use of memory ‘Ans: Addressing modes are important in assembly language program Is located and accessed by instructions. These modes describe how an it operands, whether they are immediate values, memoryaddresses, or reg) ‘Types of Addressing Modes: i) Register Mode ii) Immediate Mode Displacement or Direct Mode iv) Register Indirect Mode v) Based Indexed Mode vi) Indexed Mode vil) Based Mode 1e operands are registers. ADD AL, 45 ‘AND AX, 0000 ill) Displacement or Direct Mode: In this type of addressit given in the instruction as displacement. mode the effective address is directly Example:MOV AX, [DISP] MOV AX, (0500) iv) Register Indirect Mode: In this addressing mode the effective address Is in SI, DI or BX Example: Physical Address = Segment Address + Effective Address MOV AX, (0!) ‘ADD AL, [BX] MOV AX, [Si] v) Based Indexed Mode: In this the effective address is sum of bas Base register: BX, BP Index register: SI, DI vi) Indexed Mode: In this type of addressing mode. and displacement. Example: MOV AX, [SI+2000] Mov Al, [01+3000] vii) Based Mode: in this the effecti Example: MoV AL, [BP+ 0100} vill) Based Indexed ment Mode: In this the sum of index regist. register and displaces ‘effective address is structions. In this the value of SI and DI in the value of directional flag. is addressing mode is related with input output operations, ‘Ans: The 80386 microprocessor has a rich set of registers divided into various categories to support multitasking, memory management, and arithmetic operations. These registers are categorized as General Purpose Registers (GPRs), Segment Registers, Control Registers, Debug Registers, Test Registers, and Instruction Pointer. 1. General Purpose Registers (GPRs): These 32-bit registers are used for arithmetic, logical, and data transfer operations. They can be accessed as 32-bit, 16-bit, or 8-bit parts:|) EAX (Accumulator Register): Used for arithmetic operations. i) EBX (Base Register): Used as a pointer to memory locations: iil) ECX (Counter Register): Used for loop counters and shift operations. iv) EDX (Data Register): Used in multiplication, division, and 1/0 operations, Each register can be divided: + 16-bit part: AX, BX, CX, DX. + Sit part: AH/AL, BH/BL, CH/CL, DH/DL. 2. Segment Registers: These 16-bit registers store segment selectors ‘segmentation. They are used to access different memory segments: 1) CS (Code Segment): Points to the segment cor 3. Control Registers: These 32-bit re ‘memory management and protection: operation. |) Status Flags: Indicate results of operations (e.g., Zero Flag, Sign Flag, Carry Fag). li) Control Flags: Control processor operations (e.g., Interrupt Enable Flag, Direction Fiag). lil) System Flags: Manage advanced features (e.g,, /0 Privilege Level),Ans: The EFLAG register in the 80386 DX is a 32-bit register, which is divided into 16 individual bits that represent specific status flags. These status flags provide information about the result of the previous arithmetic or logical operation performed by the processor. ificant byte of the result of an arithmetic or logical for parity checks. 3. Auxiliary Carry fl ): This i i i ‘carry or borrow between bits 3 and F logical operation is zero. logical operation is negative. 15. Virtual interrupt flag (VIF): This flag is used to control the execution of virtual interrupts. 16. Virtual interrupt pending flag (VIP): This flag is used to indicate the presence of a pending, virtual interrupt,‘Ans: i) In the Protected mode, Memory management uses the segment selector to access 3 descriptor, segment descriptors are a part of the segmentation unit, which provides the processor with the data it needs to translate a logical address into a linear address li) A segment descriptor is a special structure that describes the segment. ili) Exactly one segment descriptor must be defined for each segment of the memory. iv) Descriptors are eight types of quantities that contain attributes ven region of linear address space, vi) These attributes include the 32-bit base linear address of the segm and granularity of the segment, the protection level, read, write, or execute of the operands (16-bit or 32-bit, and the type of segment. SEGMENT BASE 15.0 SEGMENT LIMIT 15..0 a nse 31.24 umris16 |p| on |s]o| rye ‘Accesnightt ‘and location of as limit, access rights, a of segment operation, such as granularity, ial role in memory management and protection in the ess and protect different segments of memory based on addressed by the DI register ii) Operation: a) [DI}=AL bb) If the Direction Flag (DF) = 0, DI is incremented; if OF , Dl is decremented. iil) Syntax: STOSB iv) ExampleMOV AL, ‘A’; Load 'A’ into AL MOV DI, 2000H ; Set DI to memory address 2000H sTosB | Store 'A’ at [2000H] and increment DI 2. DAA (Decimal Adjust for Addition}: i) Definition: Adjusts the result of adding two BCD numbers in AL to form a valid BCD result ii) Operation: a) Ifthe lower nibble of AL > 9 or Auxiliary Carry is set, 6 is b) Ifthe upper nibble of AL > 9 or Carry is set, 60H is added t ii) Syntax: DAA iv) Example’ MOV AL, 25H; Load BCD number 25 into AL, ADD AL, 34H; Add 34H (BCD) DAA. ; Adjust result to BCD (AL = 59h 3. XLAT (Translate): ') Definition: Replaces the value in a byte from a lookup table in = [BX +AU) of lookup table table) 1¢ of the flag register (status flags) into the AH register, || Adjust After Addition): \djusts the result in AL after adding two ASCIl-coded decimal numbers. i) Operation the lower nibble of AL > 9 or Auxiliary Carry is set, 6 is added to Al, and AK Is incremented by 2. li) Syntax: AAA iv) Example MOV AL'S’ ; Load ASCII for 5 ADDAL,'3' ; Add ASCII for3AAA Adjust AL (Result » 08H, valid BeD) 6, PUSH: |), Definition: Pushes @ word (16 bits) from a register or memary onto the stack Wi) Operation: The SP (Stack Pointer) is decremented by 2, and the value Is stored at the new stack location Wil) Syntax: PUSH reg/mem v) Example MOV AX, 12341; Load AX with data PUSH AX | Store AX on stack {) Definition: Removes a word (16 bits) fror memory. he stack and load i) Operation: The SP is incremented by 2 al Ui) Syntax: POP reg/mem iv) Example POPAX —— ; Retrieve the value from th 8, MUL (Multiply): ; Load AX with data Load 8X with data XCHG AX, BX —_; Swap contents of AX and BX 10, NOP (No Operation): |) Definition: Performs no operation except incrementing the instruction pointer. li) Syntax: NOP iil) Example: NOP Do nothing (used for timing delays)The architecture is divided into tw 1. Bus Interface Unit (BIU) 2. Execution Unit (EU, 1d by 10H (16d), to give the 20-bit physical address of the Code be modified by executing any instruction except branch i (164), to give the 20-bit physical address of the Stack Segment. 4) ES Register: ES holds the base (Segment) address for the Extra Segment. It is multiplied by 104 (16d), to give the 20-bit physical address of the Extra Segment. ji) instruction Pointer (IP register): Itis a 16-bit register. It holds offset of the next instruction in the Code Segment. Address of the next instruction is calculated as CS x 10H + IP. IP is incremented after every instruction byte is fetched. IP gets a new value whenever a branch occurs.lil) Address Generation Circuit: The BIU has a Physical Address Generation Circuit. It generates the 20-bit physical address using Segment and Offset addresses using the formula: Physical Address (20 bit) = Segment Address (16 bit) X 10H + Offset Address (16 bit) {v) Pipelining: itis a 6-byte FIFO RAM used to implement Pipelining, Fetching the next instruction while executing the current instruction is called Pipelining, BIU fetches the next "six instruction- bytes” from the Code Segment and stores it into the queue. Execution Unit (EU) removes instructions from the queue and executes them. 2) Execution Unit (EU): It fetches instructions from the Queue in BIU, d@tades and executes them: li) It performs arithmetic, logic and internal data transfer operations. I |) General Purpose Registers: 8086 has four 1¢ These are available to the programmer, for st iress of the top of the Stack, Stack is a set of LIFO manner. SP is used with the SS Register to calculate ment. It used during instructions like PUSH, POP, CALL, RET ler segments using Segment Overriding. It holds offset address of gata in Data Segment, during String Operations. destination in Extra Segment, during String Operations. Il) c) ALU (16-Bits): It has a 16-bit ALU. It performs 8 and 16-bit arithmetic and logic operations iv) Instruction Register and Instruction Decoder (Present inside the Control Unit): The EU fetches an opcode from the queue into the Instruction Register. The Instruction Decoder decodes it and sends the information to the control circuit for execution.i) Compare 80386, Pentium 1, Pentium 2, and Pentium 3 processor. 12 MHz —- 40 | 60 MHz - 300 tt 0 lee | = Pe ee Foie See, Pl Nie Ss Transistor on | Count Fabric Process Power >| Consu on | sé Ve ct ra itimedia, Gaming, | Advanced Multimedia, 0 Workstations Gamingli) Differentiate between Real mode, Protected mode and Virtual mode. ‘Addressing | 20-bit addressing, 32-bit addressing, Virtual 8086 mode allo Capability | supports upto 1MB | supports up to 4. GB each program to address memory. memory, MB ina protected No memory protection. Programs can overwrite each other. Not supported Not available. Not available. Provides memory protection using segment descriptors. (Operatesin Ring 3 (lowest Similar to protected mode but slightly slower due to virtual machine emulation. Each virtual machine has its own IVT, managed by the os. Used to run real-mode programs (e.g., DOS programs) in a protected environment. operating systems, multitasking, and large programs. 8086, 8088, 80286 | 80386, 80486, Pentium 80386 and above (in protected mode) i WiIll) Software and Hardware interrupts ‘Ans: Source Examples (Generation Dependency Figgered by a software nstruction | Triggered by an erternal hardware signal or (e.g, INT instruction) device (eg, keyboard, timer) Comes from the program or [Games from external hardware devices software Used for system cal, debugging, or [Used to hand requesting 05 services. input/output or INT 21H (008 service), INT BOH board interrupt (Linux syscall). Ore. y Slower because it depends on Faster as ts handled airecl program execution Priory is fixed by thesoftware 0 determi program. Manually generated by —— generated By Fardware when programmer. an event occurs Dependent one hardware signals lo L Vim fie address space for both | Uses separate address space for n devices. VO devices, distinct from memory. | res a largeFqUinber of address | Uses fewer address Ines (usually fegular memory instructions (MOV, | Uses special instructions (IN, OUT) ete. \/O operations. for 1/0 operations. ci 1/0 devices are accessed as memory __| I/O devices are accessed via locations. specific /0 ports ‘Speed Faster access as the same address bus is [Slightly slower since special /O used for memory and i/0. instructions are required. Hardware ‘Complexity ‘More complex, as both memory and 70. | Simpler, as memory and 0 are mapped into the same address devices have separate address space. spaces.Flexibility More flexible, allows easy integration of [Less flexible, designed mainly for memory and |/0. ‘simpler 1/0 operations. 80386, Pentium series (Memory-mapped | 8085, 8086 (IN and OUT display, audio cards). instructions for I/O operations).