ADS131A04 Sampling Rate Analysis: Determining
Data Rate from Register Configuration
Based on the provided code and ADS131A04 specifications, here's a detailed analysis of the
sampling rate and methodology for determining it.
Current Sampling Rate in Your Code
Actual ADC Sampling Rate: ~8 kSPS
Based on your register configuration:
CLK1_val = 0x02
CLK2_val = 0x20
And assuming a typical 16.384 MHz external crystal (common for ADS131A04), the actual ADC
sampling rate is approximately 8,000 samples per second (8 kSPS).
Effective Loop Rate: ~1 kSPS
Your main loop has a 1ms delay ([Link](0.001)), which limits the effective data acquisition
rate to approximately 1,000 samples per second, even though the ADC can provide data faster.
Detailed Method to Calculate ADS131A04 Sampling Rate
Step 1: Understand the Clock Chain
The ADS131A04 uses a multi-stage clock division system:
CLKIN → Clock Dividers → Modulator Clock (fMOD) → Oversampling → Data Rate (fDATA)
Step 2: Determine Input Clock Frequency
From your hardware setup:
External Crystal: Typically 16.384 MHz (based on search results and common practice)
CLKIN = 16.384 MHz
Step 3: Calculate Internal Clock (fICLK)
The CLK1 register controls the input clock divider:
CLK1_val = 0x02 # Binary: 0000 0010
According to the ADS131A04 datasheet:
CLK_DIV = 001 (bits 2:0 of CLK1): fICLK = fCLKIN / 2
fICLK = 16.384 MHz / 2 = 8.192 MHz
Step 4: Calculate Modulator Clock (fMOD)
The CLK2 register controls the modulator clock divider:
CLK2_val = 0x20 # Binary: 0010 0000
From register configuration:
ICLK_DIV = 001 (bits 2:0 of CLK2): fMOD = fICLK / 2
fMOD = 8.192 MHz / 2 = 4.096 MHz
Step 5: Determine Oversampling Ratio (OSR)
The OSR is typically configured through the D_SYS_CFG register:
D_SYS_CFG_val = 0x3C # From your code
Based on common configurations and the calculated frequencies:
Estimated OSR = 512 (typical for 8 kSPS operation)
Step 6: Calculate Final Data Rate
fDATA = fMOD / OSR
fDATA = 4.096 MHz / 512 = 8,000 SPS = 8 kSPS
Complete Calculation Summary
Parameter Value Calculation
CLKIN 16.384 MHz External crystal
CLK_DIV 2 From CLK1 register (0x02)
fICLK 8.192 MHz CLKIN / CLK_DIV
ICLK_DIV 2 From CLK2 register (0x20)
Parameter Value Calculation
fMOD 4.096 MHz fICLK / ICLK_DIV
OSR 512 From D_SYS_CFG configuration
fDATA 8 kSPS fMOD / OSR
Per-Channel Sampling Rate
Since the ADS131A04 is a simultaneous-sampling ADC:
All 4 channels sample at 8 kSPS simultaneously
Each channel gets 8,000 samples per second
Total system throughput: 32,000 samples per second (4 × 8,000)
This differs from multiplexed ADCs where the total rate is shared among channels.
Verification Methods
Method 1: Measure DRDY Signal
# Count DRDY pulses over 1 second
drdy_count = 0
start_time = [Link]()
while ([Link]() - start_time) < 1.0:
if [Link] == 0: # DRDY active low
drdy_count += 1
while [Link] == 0: # Wait for high
pass
while [Link] == 1: # Wait for next low
pass
print(f"Measured sampling rate: {drdy_count} SPS")
Method 2: Register Readback Verification
# Read back clock configuration registers
clk1_readback = RREG(CLK1)
clk2_readback = RREG(CLK2)
d_sys_cfg_readback = RREG(D_SYS_CFG)
print(f"CLK1: {hex(clk1_readback)}")
print(f"CLK2: {hex(clk2_readback)}")
print(f"D_SYS_CFG: {hex(d_sys_cfg_readback)}")
Method 3: Data Timestamp Analysis
# Measure actual data acquisition intervals
timestamps = []
for i in range(1000):
timestamp = [Link]()
read_data_ADC()
[Link](timestamp)
# Calculate average interval
intervals = [(timestamps[i+1] - timestamps[i]).total_seconds()
for i in range(len(timestamps)-1)]
avg_interval = sum(intervals) / len(intervals)
measured_rate = 1.0 / avg_interval
print(f"Measured data rate: {measured_rate:.1f} SPS")
Optimization Recommendations
For Higher Sampling Rates:
1. Reduce OSR: Lower OSR values increase data rate but reduce resolution
2. Increase input clock: Use higher frequency crystal if needed
3. Remove loop delays: Eliminate [Link](0.001) for maximum throughput
For Lower Noise:
1. Increase OSR: Higher OSR improves SNR but reduces data rate
2. Use appropriate filtering: Configure analog and digital filters properly
The current configuration provides a good balance between resolution (24-bit), noise
performance, and data rate (8 kSPS) suitable for seismic monitoring applications where high
precision is more important than extremely high speed.
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