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10G UDP - IP Protocol Stack IP Core User Guide

The 10GbE UDP Protocol Stack IP Core is designed for high-speed networking, supporting protocols like ARP, IPv4, ICMP, and UDP, compliant with IEEE 802.3 standards. It operates at 10 Gbps with a 64-bit data bus width and is compatible with AMD's Kintex and UltraScale devices using Verilog and Vivado 2020.1. This IP core is ideal for applications requiring high bandwidth and low latency, such as data centers and scientific research.

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167 views2 pages

10G UDP - IP Protocol Stack IP Core User Guide

The 10GbE UDP Protocol Stack IP Core is designed for high-speed networking, supporting protocols like ARP, IPv4, ICMP, and UDP, compliant with IEEE 802.3 standards. It operates at 10 Gbps with a 64-bit data bus width and is compatible with AMD's Kintex and UltraScale devices using Verilog and Vivado 2020.1. This IP core is ideal for applications requiring high bandwidth and low latency, such as data centers and scientific research.

Uploaded by

mijoke8910
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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10GbE UDP Protocol Stack IP Core Product Introduction

IP Information

Alinx Electronic Limited Documentation 10G UDP Protocol Stack IP Core User Guide

Contact: [email protected] IP Provided Format Encrypted Netlist

Phone: +86-021-67676997
Design Language Verilog

Development Tool Vivado 2020.1

Supported Devices AMD Kintex 7

AMD UltraScale

AMD UltraScale+

AMD Zynq UltraScale+

Product Features

• Developed in compliance with the IEEE 802.3 standard based on the OSI layered model, supporting the ARP
(Address Resolution Protocol), IPv4, ICMP (Internet Control Message Protocol), and UDP (User Datagram
Protocol) stacks.
• ARP (Supports the Address Resolution Protocol) to acquire or send MAC addresses.
• ICMP (Supports the Internet Control Message Protocol) to respond to Ping commands.
• ARP responds to all incoming requests, only stores 10 ARP tables.
• No UDP packets are sent if the ARP table is not established.
• 10Gbps Ethernet connection, supporting UDP/IP checksum processing, calculating CRC by the MAC IP.
• Developed based on Xilinx 10G MAC IP, supporting MTU up to 9000 Bytes and a minimum 64 Bytes data
transmission size.
• AXI4 Stream interface for users, with the protocol stack using a clock of 156.25 MHz generated by the MAC IP,
and a 10 Gbps data bus width of 64 bits.

IP Resource Utilization Table

Frequency
Device Series Chip Model CLB Regs CLB LUTs CLB BRAM Tile Design Tools
(MHz)

Zynq Ultrascale+ XCZU7EV-FFVC1156-2-I 156.25 8616 4761 1279 18 Vivado2020.1

Note: Actual IP resource consumption is affected by the consumption of other logical resources during instantiation.

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10GbE UDP Protocol Stack IP Core Product Introduction

Application Scenarios
10 Gigabit Ethernet (10GbE) is a high-speed network standard with a theoretical transmission rate of up to 10
Gbps (Gigabits per second), which is ten times faster than Gigabit Ethernet. This network standard is primarily
used in scenarios requiring high bandwidth, low latency, and high-speed data transfer, such as in data centers,
scientific research, and high-definition video transmission. In some situations where data transmission systems
need to handle large volumes of high speed, real-time data scenarios, traditional data transmission methods
often fail to meet requirements. 10 Gigabit Ethernet, with its high bandwidth and low latency characteristics,
ensures fast data transmission and real-time processing, while UDP (User Datagram Protocol) stack, with its
connectionless nature, ensures data transmission at maximum bandwidth.

Example of Application Structure Diagram


The diagram below shows the position of the UDP protocol stack IP core within the system design.

The UDP protocol stack IP core uses standard AXI4-Stream interfaces for both the user interface and the Ethernet
MAC + PCS/PMA IP interface. The Ethernet MAC + PCS/PMA can be any third-party IP. In the provided design
example, Xilinx's 10G/25G Ethernet Subsystem IP is used.

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