10G TCP/IP protocol stack IP Core User Guide
IP Information
Alinx Electronic Limited Documentation 10G TCP/IP protocol stack IP Core User Guide
Contact: [email protected] IP Provided Format Encrypted Netlist
Phone: +86-021-67676997 Design Language Verilog
Development Tool Vivado 2020.1
Supported Devices AMD Kintex 7
AMD UltraScale
AMD UltraScale+
AMD Zynq UltraScale+
Product Features
• Developed in compliance with the IEEE 802.3 standard based on the OSI layered model, supporting the ARP
(Address Resolution Protocol), IPv4, ICMP (Internet Control Message Protocol), and TCP (Transmission Control
Protocol) stacks.
• ARP (Supports the Address Resolution Protocol) to acquire or send MAC addresses.
• ICMP (Supports the Internet Control Message Protocol) to respond to Ping commands.
• Acts as a TCP server, responding to client connection and disconnection requests, with the ability to actively
initiate a disconnection request.
• ARP responds to all incoming requests but maintains only a single ARP table dedicated to active connections.
• Connection requests are not responding if the ARP table is not established.
• Connection requests are only accepted after receiving the configured TCP listen request when the ARP table is
established.
• 10Gbps Ethernet connection, supporting TCP/IP checksum processing, calculating CRC by the MAC IP.
• Developed based on Xilinx 10G MAC IP, supporting MTU up to 9000 Bytes and a minimum 64 Bytes data
transmission size.
• Handles sending, receiving, and responding of TCP data packets, and keeps maintenance on heartbeat
messages.
• Ensures in-order delivery, retransmission, acknowledgment, and fast retransmission in TCP transmission.
• Flow control is based on receiving and sending windows in TCP transmission.
• After establishing a TCP connection, immediately disconnect upon receiving an RST packet from the client.
• Up to two TCP connections in maximum
• AXI4 Stream interface for users, with the protocol stack using a clock of 156.25 MHz generated by the MAC IP,
and a 10 Gbps data bus width of 64 bits.
• The internal data of the TCP/IP protocol stack IP core is processed with 8-byte alignment.
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10G TCP/IP protocol stack IP Core User Guide
IP Resource Utilization Table
Frequency
Device Series Chip Model CLB Regs CLB LUTs CLB BRAM Tile Design Tools
(MHz)
Kintex-UltraScale XCKU040-FFVA1156-2-i 156.25 9689 9853 1989 82 Vivado2020.1
Note: Actual IP resource consumption is affected by the consumption of other logical resources during instantiation.
Application Scenarios
10 Gigabit Ethernet (10GbE) is a high-speed network standard with a theoretical transmission rate of up to 10
Gbps (Gigabits per second), which is ten times faster than Gigabit Ethernet. This network standard is primarily
used in scenarios requiring high bandwidth, low latency, and high-speed data transfer, such as in data centers,
scientific research, and high-definition video transmission. In some situations where data transmission systems
need to handle large volumes of high speed, real-time data scenarios, traditional data transmission methods
often fail to meet requirements. 10 Gigabit Ethernet, with its high bandwidth and low latency characteristics,
ensures fast data transmission and real-time processing, while the TCP (Transmission Control Protocol) stack
further enhances data transmission efficiency and accuracy.
Example of Application Structure Diagram
The diagram below shows the position of the TCP/IP protocol stack IP core within the system design.
The TCP/IP protocol stack IP core uses standard AXI4-Stream interfaces for both the user interface and the
Ethernet MAC + PCS/PMA IP interface. The Ethernet MAC + PCS/PMA can be any third-party IP. In the provided
design example, Xilinx's 10G/25G Ethernet Subsystem IP is used.
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10G TCP/IP protocol stack IP Core User Guide
Throughput Overview Table
MTU Sizes TCP throughput
1496 Bytes
9000 Bytes
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