MICROPROCESSOR & MICROCONTROLLER Microprocessor 8085 & 8086 interfacing with Peripherals instruction Set & Assembly Language Programming Microprocessor 8051 Systems Introduction to RISC Processor NOTE: 40 117 162 183 MAKAUT course structure and syllabus of 4" semester has been changed from 2020. Previously MICRGPROCESSOR & MICROCONTROLLER was in 5" semester, This subject has-been completely redesigned and shifted in 4" semester in present curriculum. Few new topics have been introduced also. Taking special care of this fatter we are providing the relevant MAKAUT university solutions and some model questions & answers for newly introduced topics, 80 that students can get an idea | about university questions patterns.POPULAR PUBLICATIONS MICROPROCESSOR 8085 & 8086 MICROPROCESSUK oor oer ® Chapter at a Glance Archi’ f 8085: = riléandlbclow: Th mal a cuir of 8085 is best understood from the picture Ie interna RST TNT AAG Sgr RAP SID SOD CONTROL POWER MACHINE: +5V CYCLE SUPPLY GND DING N am /DECREMENTER ADDRESS LATCH (16) ck TIMING AND CONTROL Gen ConmROL STATUS DMA RESET DATATADDRESS BUFFER (8) l ADDRESSBUS 4D7~ ADO DATA/ ADDRESS BUS RESETOUT ATs — Ay HOLD RESET IN of the microprocessor is fepresented by the box titled the-sequential “Timing and Control ; machine that we have talked. about earlier. Note that the ‘input’ to the timing a" "comes from the next “instruction” of the currently running program. M&M-2B 8 B & SOR f& MICROCONTROLLER pag revster of SD86: Direction Interrupt D1 ~tiawsea Sign ere ‘Auwiliary Carry lag register of 8085: lz Ts Tac 1 x Pox [ey J architecture of 8086: ‘The Intel 8086 is @ 16-bit microprocessor intended to be used as the CPU in a microcomputer. The yerm “16-bit” means that its arithmetic logic unit, internal registers, and most of its instructions are designed to work 16- inary words. It has 16-bit data bus and 20-bit address bus, Words will be stored in two consecutive memory locations, If the first byte of a word is at an even address, the 8086 can read the entire word in one operation. If the first byte of the word is at an odd address, the 8086 will read the first byte in one operation, and the second byte in another operation. Following figure shows the internal block diagram of 8086 microprocessor. M&M-3IBLICATIONS 7 (sneer | { E | aw ' | wstaucrioy | | STREAM | ' BYTE \ i QUEUE I i #Bus \ t sesiecaneesns—_.) 1 { 1 1 ' | 1 1 ' | ' bees, \ i i ' | ev 1 t ' | ' 1 1 1 1 t 1 | 1 ! | i 1 i ey | ! “OPERANDS | CLAS I | ta moe neneennn nana ane nnaeannen nnn ecend 8086 Internal Block Diagram Multiple Choice Type Questions 1. The chip select signal for even memory bank of 8086 microprocessor is [WBUT 2007, 2009, 2018] a) A, b) BHE ¢) ALE d) either (a) or (b) Answer: (a) 2. If ready pin is grounded, it will introduce tu States into the bus cycle of 8086/8088 microprocessor. WBUT "2008, 240 a) wait b) idle c) wait and remains idle ) all of thes® Answer: (a) 3. The segment and off-set address of the instruction to be executed by 8085 microprocessor are pointed by 6 i UT 20 , 2010, 2016) iF a) CS and SI b) DS and IP cs pane s ere and IP nswer: (d) ) M&M-4MICROPROCESSOR & MICROCONTROLLER 4. The instruction register holds [WBUT 2008, 2010, 2016] a) flag conditions b) instruction address c) opeades d) none of these Answer! (C) 5, Which Is the BSR control word to set PC4? (WBUT 2011] 2) 09H b) 07H ©) 04H d) 05H Answer: (8) ¢. How many address lines are there in 8086 microprocessor? [WBUT 2011] a) 16 b) & c) 20 d) 42 Answer: (C) 7, Amicroprocessor is said to be a 8 bit, 46 bit etc. depending on its [WBUT 2012) a) data bus b) address bus c} ALU d) control bus Answer: (C) 8, The number of register pairs of 8085 microprocessor are [WBUT 2012) a)3 b)4 cy2 ds Answer: (a) 9, The number of programmable 8-bit registers of 8085 microprocessor is [WBUT 2013] a) 5 b)6 c)7 ds Answer: (c) 40. The 8086 microprocessor addressing capacity is [WBUT 2013) a) 64 kB b) 1 MB c)2MB d)1GB Answer: (b) 44, Which of the following signals indicates an 8-bit data transfer from odd address bank? [WBUT 2014] a) Ay =0 and BHE =0 b) Ao = 1 and BHE=1 vc) As =O and BHE=1 d) Ao= 1 and BHE =0 Answer: (b) 12, What are the conditions that BIU can suspend fetching instruction? ; . [WBUT 2014] a) current instruction requires access to memory or I/O port b) a transfer control (jump or call) instruction occurs ¢) transfer queue is full d) none of these Answer: (all of these) [WBUT 2014] 13.The program counter (PG) in a microprocessor a) keeps the address of the next instruction to be fetched b) counts the number of instructions being executed on the microprocessor M&M-5POP| PI :ATIONS ¢) count the number of program being executed on the microprocessor ) counts the number of interrupts handled by the microprocessor “Answer: (a) 14. The stack and stack pointer [weuT 2014) a) both reside in memory b) both reside in CPU ; c} former reside in memory and the later in CPU d) former reside in CPU and the latter in memory Answer: (c) 45. The instruction register holds [WBUT 2014) a) flag condition b) op-code c)instruction address d) hex code Answer: (b) 16. 8086 exchanges data word with odd memory bank when: [WBUT 2015) a) (BHE)' = O.and Ao = 0 b) (BHE)' = 0 and Ao =4 ¢) (BHE}' = 1 and Ao d) (BHE)’ = 1 and Ao =1 Answer: (b) 17. How many segments are present in 8086 1MB memory space? = [WBUT 2015) a)12 b) 10 c) 18 d) 16 Answer: (d) 18. Length of physical address in 8086 is [WBUT 2015} a) 16 bit b) 4 bit c) 24 bit d) 20 bit Answer: (d) 19. Segment memory capacity of 8086 is (WBUT 2017] a)1MB b) 64KB c) 2MB d)4MB Answer: (b) 20. A microprocessor is an [WBUT 2017] a) SSI device b):MSI device c) LSI device d) VLSI device Answer: (c) 21.PSWisa______—rregister [WBUT 2018] a) 8 bit b) 16 bit c) 20 bit d) 32 bit Answer: (b) Short Answer Type Questions. 1. Specify the frequency provided by the crystal network of 8085 microprocessor. I [WBUT 2007] Answer; ‘The frequency provided by the crystal network of 8085 microprocessor is 2 MHz. M&M-6»,indloat] swe? AMpetions of BAU: icroP" following StCPS MICROPROCESSOR & MICROCONTROLLER, the functions of BIU in brief. ch the next instruction from memory, posd a" Reecure the instruction, t aperand (if required by the instruction). Page the result (i required by the instruetion) In previous CPUs, most 0} bus cycle ihe same SI exectti@ instructions, ' The bwo teps, allocates them to n unit (EU) executes instructions; ads operands and writes results. units can operate independently of or circumstances, 10 extensively overlap instruction fetch overlap. The architecture of the 8086 and 8088 CPUs, lwo separate processing units within the CPU, The the bus interface unit (BIU) fetches in most eases, the time normally required to fetch instructions " EU executes instr illustrates this over! cr seCOND GENERATION MOROPROCESSOR es/eee, wicROPROCESSOR uctions that have already been lap and compares it with tradition: example, overlapping reduces the elapsed time require allows two additional instructions to be prefetched as well a ES Ea Es INSTRUCTION STREAM su NSTRUSTION JALREADY FETCHEDY: EXECUTE AND WRITE RESULT ang INSTRUCTION. EXECUTE ONLY misrnucrion REIN SRARMD ano EXECUTE ‘ath INSYAVETION: (UNDEFINED) sth INSTRUCTION: (UNDEFINED) M&M-7 [WBUT 2007] ms Score generally execute a program by repeatedly eycli ra ycling th th + (this description is somewhat simplified): pe fF these steps have been performed serially, or with anly a single while performing ne another and are able, under most fetch with execution The result is that, ppears” because the fetched by the BIU. The Figure al microprocessor operation. In the .d to execute three instructions, andMICROPROCESSOR & MICROCONTROLLER » the buffer, Hence, the data from the buffer actually goes to the data bus only gnats ; when the buffer is enabled by appropriate 1/0 input addressing, 5 Ere function of the following pins of 8085: [WBUT 2008, 2014] READY, Ih “Answver! Ready? e This is an active high input control signal. Iv is used by microprocessor to detect whether a peripheral has completed (or is ° Ready for) the data transfer or not. Daw The main function of this pin is to synchronize slower peripheral to faster microprocessor. ¢. Ifready pin is high the microprocessor will complete the operation and proceeds for the next operation. If ready pin is low the microprocessor will wait until it goes high. INTR is an active high, level triggered general purpose interrupt. When INTR is active 1p generates an interrupt acknowledge signal. o IPINTR is active, the Program Counter (PC) will be restricted from incrementing and an will be issued. During This eyele a RESTART or CALL instruction can be inserted to jump to the interrupt Service routine. © The INTR is enabled and immediately afier an interrupt Is accepted. disabled by software. It is disabled by Reset and 6. What is the use of HOLD and HLDA pin of 8085 up? [weuT 2008) Answer: HOLD (pin 39) requests a direct memory access (DMA). When |, microprocessor stops and places address, data and control bus in high-impedance state. HLDA (pin 38) Hold ‘Acknowledge indicates that the microprocesss hold state, or has entered the 7. What do you mean by addressing mode? What are the different addressing Modes supported by B086? Explain each of them with suitable examples. * [WBUT 2008, 2011) M&M-9POPUL, UBL 1ONS Answer: fferent ways an 3086 instruction can seleg The term addressi sto the di 86 is an 1-1/2 tah Many instructions can address two operands a 1" Ot mode, we refer in tl happens, one of the operands musi be a register. BY ® the ‘second’ (i.c., non-repister) operand in such CA5°S: win brief! The different (data) addressing modes are explained BST, May ax. Bx Register Addressing: The (second) operand is @ Lait operand. Example: MOV Immediate Addressing: The instruction itself contains iP VAX, S000H. ind, B Direct Addressing: The instruction specifies the address of the operand. Example: Moy Peed an fied using one of SI and DI as index repiste, iniexed Addressing: The operand is spesi along with an optional offset. The addres: ‘contents’ of the index register with the offset, if pres MOV AX, [SI + 1000H]. Based eatin The operand is specified using one of BX and BP on baa register, along with an optional offset. The address of-the operand is obtaine y adding the ‘contents’ of the base register with the offset, if present. Example: MOV AX, [BX] or MOV AX, [BP + 1000H]. | Based-Indexed Addressing: The operand is specified using one of SI and DI as index register AND one of BX and BP as base register, along with an ‘optional offset. The address of the operand is obtained by adding the ‘contents’ of the index register with the “contents” of the base register and the offset, if present. Example: MOV AX, [SI + BX] or MOV AX, [DI + BP + 1000H]. 8. What is the difference between the physical address: and the logical address? [WBUT 2008, 2017] s of the operand is obtained by adding the ent. Example: MOV AX, [SI] of Answer: The 8086 has 20 address lines. However, any program statement addresses a memory location using an address that is divided into two parts. The first part, called the “segment” part, is the content of one of the four 16-bit segment registers selected implicitly or explicitly. The second part, called the “offset” part, is the ene specified by the statement using some addressing mode and is also 16-bits long, In 8086 parlance, “logical address” is specified in “segment: offer” form. Such an address ‘maps to" the physical address 16 * segment + offset. 9. How many flags are there in 8086 microprocessor and what are they? [WeUuT 2008] Answer: Although the flags register of 8086 is 16 bits wide, the 8086 uses only nine of those bits Out of these flags, four flags are used all the time -— zero, carry, sign, and overllow: These flags are the 8086 condition codes, The flags register appears below: M&M-10ROU ELL Overfiow Direction Inter pe C1 = Unused Aunifiary Carry cary 40. What do you mean by 16-bit microprocessor? [WBUT 2009) Answer: ; A 16 bit microprocessor is a microprocessor that can handle 16 bits ef data, 41. Write down the difference between flag register of 8085 microprocessor and flag register of 8086 microprocessor. [WBUT 2010] Answer: in 8085, there are five flag register zero, sign, parity, carry& AC. But in 8086, there are nine flag register ~ carry, parity, AC, zero, sign, trap, Interrupt, Direction, Overflow Flag register of 8086 & 8085: Refer to Chapter at ¢ Glance. is it implemented in 8086 42, a) What is pipelined architecture? How [WBUT 2010, 2011, 2012, 2014] microprocessor? Answer:- The fundamental idea of pipelined architec! instruction into a series of independent steps (lik "Execute", ete.) with storage at the end of each step. circuitry to issue instructions at the processing rate | faster than the time needed to perform all steps at one fact that each step is carrying data at once (like water), next (like the links ofa pipe.) In 8086, there are two separate units ture is 10 split the processing of a computer e "Prefetch", “Fetch, "Decode", This allows the computer's control f the slowest step, which is much -e, The term pipeline refers to the and each step is comnected to the the "Bus Interface Unit" (BIU) and the "Execution Unit” (EU). The BIU performs all bus operations for the EU. Dara is transferred between the CPU and memory or YO devices upon demand from the EU. During periods when the EU is busy executing instructions, the BIU "looks ahead” and fetches more instructions from memory. This way, a (ype of "Fetch-Execute-pipeline" is implemented in 8086. In 8086, an added advantage is pipe! status lines QS, and QSq gives the inform queue. These are shown below: QS: _| O50 o 0 No operation M&M-I1 lining processing of the instructions. The Queue ation about the status of the eode-prefetch IndicationFrom the queue use ei at byte rom the queue. i hitecture of a convent This is a modified architecture of simple fetch and oan Therefore even the Tancey microprocessor. 8086 has prefetch queue of 6 bye ey and stored in the queue, This instruction (6 bytes) can be prefetched from the mel 7 8085, an instruction (opcode ang the execution of the instructions is faster. In case © the execution of this instructio operand) is fetched, decoded and xccute aa ore there is a cotsldershlt the next one is fetched. Thus, by prefetching T 4 ing i i speeding up in instruction execution in 8086. This 1YPe of processing is known as instruction pipelining. i i d WO technique in the context of b) How many address lines are used for /O mappe! interfacing with 8086? [WBUT 2010, 2014] Answer: ; : The processor 8086 has 20 address lines. The 1/0 mapped interfacing may use at most 16 address lines Ao— Aus or even 8 address lines for address decoding. 43. How does the microprocessor differentiate between data and instruction? [WBUT 2010) Answer: In reality, a microprocessor (of Von-Neumann architecture) cannot distinguish a byte in memory from instruction to data. However, it always treats the byte of the memory location pointed at the Program Counter (PC) as (a part of) an instruction, 44. Give the bit configuration of 8085 flag register. [WBUT 2011] R, How many flag bits are there in 8085 microprocessor? Explain each of them. [WBUT 2015) Answer: The five flags are: * Zor Zero Flag. SET when the result of last operation leaves all zeroes: * Sor Sign Flag. SET when the last operation makes bit-7 (.e.,-thi t significant bit) of the result |. HAL ee eas -P os Puy Flag. SET when the last operation leaves an ever number of I-s inthe result. « C or Carry Flag, SET when the last arithmeti ion i s a carry of borrow out of the most significant bit, lic operation involves a 6amy © AC or Auxiliary Carry Flag, Dy De Ds Dy Ds x Csb2t« paey Do D; D, [oP [x [Eee M&M-12ICROPRO! & MICROCONTROLLI The fees ie actually @ part of an internal 8-bit register referred to as “Flags”. The layout is MORE. The only two instructions that refer to the flags register directly are POP PSW and PUSH PSW. vee 45. Explain the memory segmentation scheme with reference to 8086 microprocessor, [WBUT 2012] Answer: Microprocessor 8086 has 20 address pins, so maximum numbers of memory location, which can be connected with 8086 are 2” =1MB locations or 16 blocks of 64K locations, The memory connected with 8086 is always divided into following four segments: |. Code memory segment: It is used to store instructions code of a program. 2. Data memory segment: It is used to store data bytes / words 3. extra memory segment: It is an additional segment for storing data. 4, Stack memory segment: It is used to store stack of data using PUSH / POP instruction. Starting memory location address of any memory segment is called as its base address (BA). The four LSBs of base address should be always (0), rest of the 16 MSBs of base address is always stored in corresponding 16-bit segment register CS, DS, ES, SS. The actual 20-bit address of any memory location is called as physical address (PA) to select any memory location. Microprocessor has to transfer 20-bit physical address on address pins. Fig. 1 shows the following: 1. Register CS contains 2500h, so the base address of code memory is 25000h. 2. Register DS contains 4000h, so the base address of data memory is 40000h. 3. Register ES contains 5000h, so the base address of extra memory segment is 50000h. 4, Register SS contains 7954h, so the base address of stack memory segment is 79540h, NA ReMA_Aia MICROPROCESSOR de MICROCONTROLLER The flags are actually a part of an internal 8-bit register referred to as “Flags”. The layout is MORE. The only two instructions that refer to the flags register directly are POP PSW and PUSH PSW. 45, Explain the memory segmentation scheme with reference to 8086 microprocessor. [WBUT 2012] Answer? Microprocessor 8086 has 20 address pins, so maximum numbers of memory location, which can be connected with 8086 are 2”°=1MB locations or 16 blocks of 64K locations. The memory connected with 8086 is always divided into following four segments: ], Code memory segment; It is used to store instructions code of a program. 2, Data memory segment: It is used to store data bytes words. 3. extra memory segment: It is an additional segment for storing data. 4. Stack memory segment: It is used to store stack of data using PUSH / POP instruction. Starting memory location address of any memory segment is called as its base address (BA). The four LSBs of base address should be always (0), rest of the 16 MSBs of base address is always stored in corresponding 16-bit segment register CS, DS, ES, SS. The actual 20-bit address of any memory location is called as physical address (PA) to select any memory location. Microprocessor has to transfer 20-bit physical address on address pins. Fig, 1 shows the following: 1. Register CS contains 2500h, so the base addtess of code memory is 25000h 2, Register DS contains 4000h, so the base address of data memory is 40000h. 3. Register ES contains 5000h, so the base address of extra memory segment is 50000h. 4. Register SS contains 7954h, so the base address of stack memory segment is 79540h. i M&M-13POPULAR PUBLICATIONS i i t 2 3 4 os Sagmentation of meenocy Fig: | Segmentation of microprocessor 8086 The internal address of each memory segment will be of 16-bits, hence the maximum number of memory location in one memory segment will be 2° =64 K, so for fixed base address, microprocessor 8086 can use maximum four blocks of 64K at a time far the four-memory segment, but if the base address of the segment is changed, then all the 16 blocks of 64K can be used by the microprocessor. The four-memory segment can be completely isolated or partially overlapped or completely overlapped. 16. Explain how 20-bit physical address is generated in 8086 microprocessor. [WBUT 2012] Answer: We have already seen that the 8086/88 has a 20-bit address bus, allowing it to output 2" or 1'048.576, different memory addresses. As you can see, 524.288 words can also be visualized, Still another view of the 8086 memory'space could be as : inning at hex address 000000h and ending at addross OPE oe =e Bots begins blocks is an arbitrary-but Convenient choice. This is because the most significant hex digit increments by | with each additional f ificant hex dig higher in memory than address 10000h, block. That is, address 20000h is 65.536 bytes Note that five hex digits are required to represent a memory address M&M-14MICROPROCESSOR & MICROCONTROLLER ROM BFFFFH AGHGOH SEFFPh 0000h Memory Map The diagram is called a memory map. This is because, like a road map, it is a guide showing how the system memory is allocated. This type of information is vital to the programmer, who must know exactly where his or her programs can be safely loaded. Note that some memory locations are marked reserved and others dedicated. The dedicated locations are used for processing specific system interrupts and the reset function. 17. Explain the concept of memory segmentation in 8086 microprocessor. _ [WBUT 2013] OR, Explain Memory segmentation in 8086 microprocessor. [WBUT 2048] Answer: The process of dividing total available memory size into different part is simply known as memory segmentation. 8086 has twenty line address bus with 2* byte of memory. The range of memory location can vary from 00000H to FFFFFH. It has four different types of segmentation, These are: Code segmentation Stack segmentation Data segmentation Extra segmentation Each of these segmentations is addressed by different addresses stored at different 16 bit registers.POPULAR PUB! iS 48, List the 8086 addressing modes and briefly explain the same. = [WBUT 2013) Answer: i, 8086 Register Addressing Modes This instruction copies the data from the source operand to the destination operand, The cight and 16 bit registers are certainly valid operands for this Instruction. The only restriction is that both operands must be the same size 7 Ex. moy destination, source ti, 8086 Memory Addressing Modes Displacement Only Addressing Modes The most common addressing mode, and the one that's easiest to understand, is the displacement-only (or direct) addressing mode. The displacement-only addressing mode consists of'a 16 bit constant that specifies the address of the target location. Ex. mov al,ds:[8088h] loads the al register with a copy of the byte at memory location 8088h. Register Indirect Addressing Modes The 80x86 CPUs let you access memory indirectly through a register using the register indirect addressing modes. There are four forms of this addressing mode on the 8086, best demonstrated by the following instructions: ‘ mov al, [bx] mov al, [bp] mov al, [si] mov al, [di] As with the x86 [bx] addressing mode, these four addressing modes reference the byte at the offset found in the bx, bp, si, or di register, respectively. The [bx], [si], and [di] modes use the ds segment by default. The [bp] addressing mode uses the stack segment (ss) by default, Indexed Addressing Modes The indexed addressing modes use the following syntax: mov al, disp[bx] mov al, disp[bp} mov al, disp[si] mov al, disp[di] If bx contains 1000h, then the instruction mov cl,20h[bx] will load al from memory location ds:1020h. Likewise, if bp contains 2020h, mov dh,lO00h{bp] will load dh from location ss:3020, ‘The offsets generated by these addressing modes are the sum of the constant and the specified register. The addressing modes involving bx, si, and di all use the data segment, the disp[bp] addressing mode uses the stack segment by default, Based Indexed Addressing Modes The based indexed addressing modes are simply combinations of the register indirect addressing modes, These addressing modes form the offset by adding together a base register (bx.or bp) and an index register (si or di). The allowable forms for thes¢ addressing modes are M&M-16, mov al, [bx]{si] mov al, [bx] [di] moy al, [bp][si] moy al, [bp][di] Suppose that bx contains 1000h and si contains 880h. Then the instruction mov al,[bx][si] would load al from location DS:1880h. Likewise, if bp contains 1598h and di contains 1004, mov ax,[bp+di] will load the 16 bits in ax from locations $8:259C and $8:259D. MICROPROCESSOR & MICROCONTROLLER Based Indexed Plus Displacement Addressing Mode These addressing modes are a slight modification of the base/indexed addressing modes with the addition of an eight bit or sixteen bit constant. The following are some examples of these addressing modes: mov al, disp[bx][si] mov al, disp[bx+di] mov al, [bp+sitdisp] mov al, [bp][di][disp} You may substitute di in the figure above to produce the [bx+di+disp] addressing mode. 19. Describe MIN/MAX mode operations of 8086 microprocessor. [WBUT 2015] Answer: Refer to Question No. 9(a) af Long Answer Type Questions. 20. What is the function of BHE pin in 8086 microprocessor? [WBUT 2015) Answer: ‘The Bus High Enable (BHE) is used to indicate the transfer of data over the higher order (D15-D8 ) data bus . It goes low for the data transfer over DI5-D8 and is used to derive chip selects of odd address memory bank or peripherals, BHE is low during TI for read, write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of data bus. The status information is available during T2, T3 and T4, The signal is active low and tristated during hold. It is low during T1 for the first pulse of the interrupt acknowledge cycle. 21. What are the function of ALE, HOLD and READY? [WBUT 2015] Answer: Address latch Enable (ALE): * Itis an output signal used to give information of ADO-AD7 contents, © It is a positive going pulse generated when a new operation is started by microprocessor. * When pulse goes high it indicates that ADO-AD7 lines are address. * When it is low it. indicates that the contents are data, HOLD: * HOLD indicates that another Master is requesting the use of the Address and Data Buses. M&M-17UBLICATION: * The CPU, upon receiving the Hold request, will withdraw the use of buses as soon as the completion of the current machine eycle, Internal processing can continue. * The processor can regain the buses only after the Hold is removed. * When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are tri-stated. Ready: © This is an active high input control signal. * It is used by microprocessor to detect whether a peripheral has completed (or is Ready for) the data transfer or not. 22. a) Which register pair is the memory address register of 8085 Microprocessor. [WBUT 2017] Answer: The 8085 has six general-purpose registers to store 8-bit data; these are identified as- B, C, D, E, H, and L. These can be combined as register pairs - BC, DE, and HL, to perform some 16-bit operation. These registers are used to store or copy temporary data, by using instructions, during the execution of the program. b) Explain with examples why auxiliary carry flag is not user defined? [WBUT 2017] Answer: The auxiliary flag is set when there is a carry from the d3 bit of the data to the d4 bit of the data. So auxiliary carry flag is not ser defined. i.e., for e.g, Ifu add 290010 1001 (41) base 10 39-0011 1001 (57) base 10 an ~01110 0010 (98) base 10 Here the auiliary flag is set 23. What is meant by pipelining? What are the advantages and disadvantages of it? [WBUT 2016] Answer: 1 part: As mentioned earlier, pipelining offers an economical way of realizing Parallelism in computer systems. The concept. of pipelining is similar to that of an assembly line in an industrial plant wherein the task at hand is subdivided into several subtasks and each subtask is performed by a stage (segment) in the pipeline, In this context, the task is the processing performed by the conglomeration of all the stages in the pipeline. In this context, the task is the processing performed by the conglomeration ‘of all the stages in the pipeline and the subtask. is the processing done by a stage, For example, in the car assembly line described earlier, “building a car” is the task and it was Partitioned Into four subtasks, The tasks are streamed into the pipeline and all the stages Operate concurrently, At any given time, each stage will be performing a subtask belonging to different task. That is, if there are N stages in the pipeline, N different tasks will be processed simultaneously and each task will be at a different stage of processing. M&M-18MICROFRt & ONTROLLER : w is reduced; increasing the instruction throughput. ~ pipelining doesn't reduce the time it takes to complete an instruction; instead. it increases the number of instructions that can be Processed simultaneously ("at once") and reduces the delay between completed instructions (called ‘throughput’. ‘The more pipeline stages a processor has, the more instructions it can process “at once" and the less of a delay there is between completed instructions. Every predominant general purpose microprocessor manufactured today uses at least 2 stages of pipeline up to 30 of 40 stages, 2. If pipelining is used, the CPU Arithmetic logic unit can be designed faster, but more complex. 3, Pipelining in theory increases performance over an un-pipelined core by a factor of the number of stages (assuming the clock frequency, also increases by the same factor) and the code is ideal for pipeline execution. 4, Pipelined CPUs generally work at a higher clock frequency than the RAM clock frequency, (as of 2008 technologies, RAMs work at a low frequencies compared to CPUs frequencies) increasing computers overall performance. Disadvantages of Pipelining: Pipelining has many disadvantages though there are a lot of techniques used by CPUs and compilers designers to overcome most of them: the following is a list of common drawbacks: 1, The design of a non-pipelined processor simpler and cheaper to manufacture, non- pipelined processor executes only a single instruction at a time. This prevents branch delays (in Pipelining, every branch is delayed) as well as problems when serial instructions being executed concurrently. 2, In’ pipelined processor, insertion of flip flops between modules increases the instruction latency compared to a non-pipelining processor, 3. A non-pipelined processor will have a defined instruction throughput, ‘The performance of a pipelined processor is much harder to predict and may vary widely for different programs. Many designs include pipelines as long as 7, 10, 20, 31 and even more stages; a disadvantage of a long pipeline is when a program branches, the entire pipeline must be flushed (cleared). The higher throughput of pipelines falls short when the executed code contains many branches: the processor cannot know in adyance where to read the next instruction, and must wait for the branch instruction to finish, leaving the Pipeline behind it empty. This disadvantage can, be reduced by predicting whether the @ conditional branch instruction will branch based on previous activity. After the branch is resolved, the next instruction has to travel all the way through the pipeline before its result becomes available and the processor restimes “working” again. In Such extreme cases, the performance of a pipelined processor could be worse than non-pipelined processor. 24.a) How physical address will be generated from logical address? [WBUT 2017] M&M-19PU! Answer: “ Using the paging process physical address can be generated from logical address, 'b) Write down the bit pattern of Flag register of 8086 jp. (WeuT 2017) Answer: There are 9 flag register in 8086 microprocessor (a) Status Flags — There are 6 flag registers in 8086 microprocessor which become seu(|) or reset(0) depending upon condition after either 8-bit or 16-bit operation. These flags are conditional/status flags. $ of these flags are same as in case of 8085 microprocessor ang their working is also same as in 8085 microprocessor. The sixth one is the overflow flag, The 6 status flags are: Sign Flag (S) Zero Flag (Z) Auxiliary Cary Flag (AC) Parity Flag (P) Carry Flag (CY) Overflow Flag (O) Aw ewne Dis Dis Dis Di Dn Dio Dy Ds Dy De Ds Dy Ds Dr Dr Dy ovTovTil[T[s[z AC PT Tey] Control Flags ~The control flags enable or disable certain operations of the microprocessor. There are 3 control flags in 8086 microprocessor and these are: 1, Directional Flag (D) 2. Interrupt Flag (1D 3. Trap Flag (T) 25. What is the function of READY, ALE, So, S: pins? [WBUT 2018) Answer: Ready: his is an active high input contro! signal. * It is used by microprocessor to detect whether a peripheral has completed (or is Ready for) the data transfer or not, Address latch Enable (ALE): * [tis an output signal used to give information of ADO-AD? contents. © Itisa positive going pulse generated when a new ‘operation is started by microprocessor * When pulse goes high it indicates that ADO-AD7 lines are address. * * When it is low it indicates that the contents are data. Sp & Sy: 8085 provides a set of two output pins So, S (Pin-29, Pin-33) through which indicates its intemal state as follows: 10/4 S [Si Control Logie ] M&M-20ICROPROCES Mik OLE! Memory Read Memory Write VO Read VO Write 0 0 1 I 0 ‘Op-code Fetch 1 Interrupt Acknowledge 2/—]-|-|o]-]o e}-|-|oj-jo}— Tri-state Halt 26, What are the differences between 8085 ip and 8086 yp? Answer [MODEL QUESTION] 8085 8086 7) Basically 8085 is a 8-bit processor with 8- pit internal and external data bus. 1) 8086 is a bit processor with 16-bit internal and external data bus. b) The intemal architecture of 8085 15 not divided into functional parts. 3) The concept of segmentation is absent in 8085. @) The address bus in 8085 Is of 16- bits and hence it is capable of addressing 64K or 65, 536 memory locations. 2) The architecture of $086 is divided into two funetional pats i) BIU and fi) EU. Dividing work between these two speeds up rocessing. 3) In 8086, IMB of memory is segmented into 4 segments, each of 64K. The segmentation is achieved using segment registers CS, DS, ES, 8S. 4) The address bus in case of 8086 is of 20- bits and hence it is able to address [MB or 1,048,576 memory locations. '5) The clock frequency in 8085 3.0707MHz. 5) In 8086, the clock frequency ranges from 4.77 MHz to 1OMHz, depending upon different versions. 6) In 8085, there are 5 hardware interrupt pins svailable externally. They are: i) INTR ii) TRAP iii) RST 7.5 iv) RST 6.5 and v) RST) 5.5. 7) Concept of pipelining is absent. 8) The concept of memory banking is absent, ‘Therefore the memory map of 8085 is intact. 8) IM: When this pin goes low memory Operation is performed, While [/O operation is done when signal on this pin is high, 6) In 8086 there are only 2 hardware interrupt pins available they are i) (NTR and ii) NML. 7) Hi involves pipe-lining while execution the programs, - 8) The concept of banking of memary ICs is involved in 8086 interfacing, therefore| memory map of 8086 is divided into two) |i) upper bank ii) lower bank. 9) Mi 10; The signal on this pin is inverted as| compared to 8085 fer I/O and memory operations. 1. What are the main functions of BIU and EU units of 8086 microprocessors. M& [WBUT 2008, 2009, 2011, 2014, 2015, 2017] ‘M-21LAR PUBI NS OR, 086 microprocessor. Explain the operations of BIU and EU present in (WELT 2012, aie Answer: a program by repeatedly cycling through the jeroprocessors generally execute by fallow ig steps (this description is somewhat simplified): * Fetch the next instruction from memory. * Read an operand (if required by the instruction). * Execute the instruction. © Write the result (if required by the instruction). s | In previous CPUs, most of these steps have been performed serially, or with only a single bus cycle fetch overlap. The architecture of the 8086 and 8088 CPUs, while performing the same steps, allocates them to two separate processing units within the CPU. The execution unit ‘(BU) executes instructions; the bus interface unit (BIU) fetches instructions, reads operands and writes results. : The two units ean operate independently of one another and are able, under most circumstances, to extensively overlap instruction fetch with execution. The result is that, in most cases, the time normally required to fetch instructions "disappears" because the EU executes instructions that have already been fetched by the BIU. The Figure illustrates this overlap and compares it with traditional microprocessor operation. In the example, overlapping reduces the elapsed time required to execute three instructions, and allows two additional instructions to be prefetched as well sichorscecsson HNSTAUCTION STREAM [gh muction va neacee SCCTTE AAD waite neauLE TeHERe zee marnweTioN: EXCCUTE ORLY ANSTAUET On, OFenaMD AND EXECUTE sesravc iocrineay Hmmstnucron: (anaeANEGy O™ Execution Unit The execution units of the 8086 and 8088 are (ALU inthe BU maintains the CPU status and contol egy eesti wk ontrol flags, and manipulates the general M&M-22Mk "ROCESSOR & MICROCONTROLLI registers and instruction operands, All registers and data paths in the EU are 16 bits wide for fast internal transfers, ‘The EU has no connection to the system bus, the "outside world." It obtains instructions from a queue maintained by the BIU, Likewise, when an instruction requires access to memory or toa peripheral device, the BU requests the BIU to obtain or store the data. All addresses manipulated by the EU are 16 bits wide. The BIU, however, performs an address relocation that gives the EU access to the full megabyte of memory space. Execution Unil (EU) Bus Interface Unit (BIU) Segment Registers ‘General Registers Tratraction Pointer ‘Address Generation ‘And Bus ‘Coniro! Multiplexed Bus Flags Bus Interface Unit The BIUs of the 8086 and 8088 are functionally identical, but are implemented differently to match the structure and performance characteristics of their respective buses. The BIU performs all bus operations for the EU. Data is transferred between the CPU and memory or I/O devices upon demand from the EU. In addition, during periods when the EU is busy executing instructions, the BIU "looks ahead” and fetches more instructions from memory. The instructions are stored in an internal RAM array called the instruction stream queue. The 8088 instruction queue holds up to four bytes of the instruction stream, while the 8086 queue can store up to six instruction bytes. These queue sizes allow the BIU to keep the EU supplied with prefetched instructions under most conditions without monopolising the system bus, The 8088 BIU fetches another instruction byte whenever one byte in its queue is empty and there is no active request for bus access from the EU. The 8086 BIU operates similarly except that it does not initiate a fetch until there are two empty bytes in its queue. The 8086 BIU normally obtains two instruction bytes per fetch; if a program transfer forces fetching from an add address, the 8086 BIU automatically reads one byte from the.odd address and then resumes fetching two-byte words from the subsequent even addresses. Under most circumstances the queues contain at least one byte of the instruction stream and the EU does not have to wait for instructions to be fetched. The instructions in the queue are those stored in the memory locations immediately adjacent to and higher than M&M-23RPI INS * the next logical instructig, ia ail an instruction that ftir ne EU fetches the instruction from the yo" hon begins refilling the queue from te instruction fetching whenever the BL pt that a fetch already in progres; is the instruction currently being executed. TI long, as execution proceeds serially. If control to another location, the BIU resets the als address, passes it immediately to the EU, and @! new location, In addition, the BI suspends requests a memory or I/O read or write (excel completed befare executing the L's bus request) microprocessor. 2. Describe the different addressing modes of 8086 [WBUT 2008, 2014, 2015) oR, Describe different addressing mode of 8086 with example? [WBUT 2013 Answer: ie Each instruction performs an operation on the specified oe foe at Ct & operand must be specified for an instruction to be executed. The oes _ sh reside in the accumulator, in a general purpose register or in 4 memory Se es A Way: By. which an operand is specified for an instruction is called addressing moc - There are in total eight addressing modes for 8086 instructions to specify operands, Out of eight addressing modes mere two addressing modes are provided for instructions which operate on the contents of a register or immediate operands, There two addressing modes are, < . Register Addressing: In this mode of addressing an 8-bit or 16-bit general purpose register contains an operand, Some examples are: (i) MOV BX, CX; move the content of CX register to BX register. Gi) ADD AL, CH; add the content of CH to the content of AL. (ii) ADD CX, DX; add the content of DX to the content of CX. Immediate Addressing: In the immediate addressing mode, the operand is contained in the instruction itself. The operand forms a part of the instruction, Some examples are: (i) MOV AL, 58H; move 58H to AL register. (ii) MOV BX, 0354H; move 0354H to BX register, (iii) MOV [offset address}, data: such as MOV [0400], 5238H; This instruction will move 38H to the offset address O400H and 52 to the offset address 0401H (iv) ADD AX, 0395H; Add 0395H to the content of AX register, ‘The remaining six addressing modes are for specifying an operand stored in the memory. The memory address of an operand consists of two 16-bit components: the starting address of a memory segment and an offset. The starting 16 MSBs of the address of @ memory segment resides in the corresponding segment register. The operand is placed at an offset within the segment with reference to the starting address of the segment. An offset is also called an effective address. The offset is determined by adding any combination of the following three offiet address elements. displacement, base and index. The combination depends on the addressing made of the instruction to be executed, The actual memory address is given by: Memory address = Starting address of the memory segment + Offset. M&M.-24$086 uses 20-bit memory address, The segment register gives 16 MSBs of the esting address of the memory segment. The BIU generates 20-bit starting address of the emory segment BY shifting the content of the segment register left by 4 bits In other wis, it puts 4 Zeros in LSBs positions. The offset is added to the starting address of the sory segment to gel the memory address. pisplacement: It is an 8-bit or 16-bit immediate value given in the instruction, se: It is the content of the base register, BX or BP. {ndex: Its the content of the index register, $ or DI. The combinations of these three address elements result in the following six addressing modes: ‘ ‘ vrect Addressing: In this mode of addressing an effective address (oF offset) is given in the instruction itself. Some examples are: (i) MOW AL, [0.00H] This instruction will move the content of the offset address 0300H (relative to data segment register DS which contains the starting address of the data segment) to AL (ii) MOV [0401H}, AX | This instruction will move the content of AL to the offset address O401H and the content of AH to 0402H relative to DS register. Register Indirect Addressing: The operand’s offset jn the base register, BX or base pointer BP or in an index register (SI or DI) specified in the instruction, Some examples (i) ADD CX, [BX] ‘ This will add the contents of memory locations addressed by register BX to the register CX. For example BX contains 0301H. The content of 0301 H is 64H and the content of next memory location. 0302H is 50H. Now S064H will be added to the content of CX register and the result will be placed in CX. (ii) MOV DX, [SI] The content of the memory location addressed by SI will move to DL and the content of next memory location will move to DH. Based Addressing: The operand’s offset is the sum of the contents of the base register, BX or BP and an 8-bit or 16-bit displacement. Offset (effective address) = [BX or BP + 8-bit or 16-bit displacement] Some examples are: (i) ADD AL, [BX + 04]; case of 8-bit displacement Suppose, BX contains 0301H, So 0301 + 4 = 0305H. The content of [BX +4] will be added to the content of AL and the result will be placed in AL. (ii) ADD AL, [BX + 1243H]; case of 16-bit displacement Indexed Addressing: The operand’s offset is computed by adding an 8-bit or 16-bit displacement to the contents of an index register SI or DI. Offset = [SI or DI + 8-bit or 16-bit displacement] Some examples are: a) ADD AX, [SI + 08] M&M-25IPULAR. b) MOV CX, [SI + 1523H] Based Indexed Addressing: The operands offset is computed by adding the contents og a base register to the contents of an index register. 1 = [BX or BP] + [SI or DI] ; raps BX is ee a register for data segment. BP is used as a base register for stacy segment. Some examples are: (i) MOV AX, [BX + SI) (i) ADD CX, [BX+S1] Based Indexed with Displacement: The operand’s offset is computed by adding a base register’s contents, an index register’s contents and an 8-bit or 16-bit displacement. Offset = [BX or BP] + [SI or DI] + Displacement BX is used with data segment, whereas BP is used with stack segment Some examples are: (i) MOV AX, [BX + 81 +04] (i) ADD CX, [BX +SI+ 1523H] 3. a) What is interrupt vector table? Explain its structure. Explain the interrupt response sequence of 8086. [WBUT 2010) Answer: The 8086 microprocessor can be interrupted by holding the INTR pin HI. 8086 “acknowledges” by issuing two back-to-back LO pulses on the INTA’ pin, Synchronized with second pulse, the interrupting device must put an 8 bit value called the “type of the interrupt” on Do- D; of the data bus. “The type of the interrupt” is an index into the “Interrupt Vector Table”, which is 256- entries, 4 bytes per entry table located in memory locations 00000 EI till OO3FF H. Each 4 byte entry called a “vector” holds the offset and the segment addresses of the interrupt service routine ---- the first two bytes correspond to offset and the next two bytes correspond to segment. The 8086 then “pushes” the current CS and IT values onto the stack and saves CS:IT to the above mentioned vector, The ISR then starts executing from the location specified in the vector Ideation. Interrupt Vectors: interrupt vectors and vector table are erucial to an understanding of hardware and software interrupts. The interrupt vector table is located in the first 1,024 bytes of memory at addresses 0000000H-0003FFH, It contains 256 different 4-byte interrupt vectors. An interrupt vector contains the address (segment and offset) of the interrupt service procedure. M&M-26MICROPROCESSOR & MICROCONTROLLER Fig. 1 depicts the intermupt vector table for WP. tenant e a as | ‘The Type} vn ee —_— - : cout | syatestep 2 [7 Searentiow) | Te | ~ 0 [eee (a) For microprocessor (b) Contents of an interrupt vector Fig: | Interrupt vector table ‘The imerrupt vectors shown in Fig. | are identical in all Intel microprocessor family members from 8086 to Pentium. Each vector is four bytes long and contains the starting address of the interrupt service procedure. The first two bytes of the vector contain the offset address and the fast two bytes contain the segment address, : The following Table 1 describes the function of each dedicated interrupt in the microprocessor: Table 1; Function of Interrupt Function or Ocours whenever the result of a division overflows or whenever am attempt is made to divide by zero. Single-Step or Trap-Occurs afer the execution of each instruction if the trap TF flag bit is set. Upon accepting this interrupt, the TE-bit is cleared so that the interrupt service procedure executes at full speed, more detain is provided about this interrupt later in this section of the chapter. Non-maskable Hardware Interrupt — A result of placing a togic 1 on the NMI input pin to the microprocessor, This input ig non-maskable, which means that it cannot be disabled ‘One-Byte Interrupt — A special I-byte instruction (INT 3) that uses this vector to acess its interrupt service procedure. The INT 3 insteuction is: often used to store a breakpoint in a program for debugging. M&M-27PULAR PUBLICATIO: INTO instruction. The INTG fr the : Pray condition exists, as reflected by flo will Gverflow — A special vector oe instruction interrupts the prograr ii the overflow flag (OF). lowing interrupt in the 8086 IVT? b) What is the interrupt vector address of the foll TWBUT 2010) i) INTO ij) NMI ii) INT 21H. Answer: for INT 21 The required vector addresses are: INT 0- 10H, NMI-8H and of course for H, the vector location is 21Hx4 = 84H. il the interfacing circui ¢) How will you interface a stepper moter with 80867 Brew [WEUT 2040, and flow-chart. Answer: Hardware: P - Figure shows the typical 2 phase motor rated 12 V/.67A/ ph interfaced with the 8086 micropracessor system using 8255. Motor shown in the circuit has two phases, with center-tap winding, The center taps of these windings are connected to the 12 V supply. Due to this, motor can be excited by grounding four terminals of the two windings. Motor can be rotated in steps by giving praper excitation sequence to these windings. The lower nibble of port A of the 8255 is used te generate excitation signals in the proper sequence. These excitation signals are buffered using driver transistors. The transistors are selected such that they can source rated current for the windings. Motor is rotated by 1.8° per excitation, ‘ FSP IPPee MICROPROCESSOR & MICROCONTROLLER 4 pisouss the hardware and software of any microprocessor based industrial application. (weuT 2011) answer? Fesaprocessor based industrial application: - Microcomputer whe simplest and cheapest general purpose microprocessor-based systems are erferocompuiers” with minimum possible hardware & sofware con figuration The microprocessor comprises of all the functional elements of CPU of any general- purpose computer. A microprocessor with all finctional clements ie. ALU, control unit, pd recister section is fabricated on a single IC. As a result it has inherited all the characteristics of an IC. Components of a microcomputer: fa) Memory Unit Its purpose is to store both instructions & data. It is also called the Random-Access Memory (RAM) because the CPU can access any memory location at random, (hy) CPU Vracis as the brain of the computer and performs the bulk of data processing operations in computer. The two main units of a CPU are the Arithmetic Logie Unit and the Program Control Unit. The important parts of CPU are: () Arithmetic Logic Unit (ALU): |t performs instructions related to arithmetic operations like ADD, SUB, MUL ete. and logical operations like AND, OR etc. (ij) Program Control Unit (PCU): It interprets & sequences instructions i.e. interpret & sequences which instruction in a program is to be executed first. (iii) Register Sets: These are collections of registers that store data. (ec) Input-Output (1/0) Unit This unit provides an efficient mode of communication between the central system (computer) & the outside envirenment. Through the /O unit, programs & data must be entered into computer memory for processing & results obtained from computations must be recorded or displayed to the user. Microcomputers are designed to serve onl modified with software or hardware to concurrent! ed in 8086 microprocessor? [WBUT 2014, 2015, 2046) ly one user at a time, although they can often be y serve more than one user. 5. a) How is pipelining achiev M&M-29POPULAR PUBLICATIONS [ 4, Overflow — A special vector .s of the following interrupt in the 8086 IVT? instruction interrupts the program if an the averflow flag (OF). dd b) wnat tla interrupt vector addres: Sed IVT 0 Taed with the INTO instruction, The INTO overflow condition exists, as reflected by The required vector addresses are: INT 0-10H, NMI-8H and of course for INT 21 H, the vector location is 21Hx4 = 84H. c) How will you interface a stepper moter with 80867 Draw the Ore and flow-chart. Answer: Hardware: Figure shows the typical 2 phase motor rated 12 W/.67A/ ph interfaced with the 8086 microprocessor system using 8255. Motor shown in the circuit has two phases, with center-tap winding, The center taps of these windings are connected to the 12 V supply. Due to this, motor ean be excited by grounding four terminals of the two windings. Motor can be rotated in steps by giving proper excitation sequence to these windings. The lower nibble of port A of the $255 is used to generate excitation signals in the proper sequence. These excitation signals are buffered using driver transistors. The transistors are selected such that they can source rated current for the windings. Motor is rotated by 1.8° per excitation, . a a _ ars o sig. a 0 Ens os * A jBG2 gg) PSPsosee a B 33 PrP LP eS oeOPROCESSOR é& MICK LER . Discuss the hardware and software of any microprocessor based industrial application. (weuT 2011] Answer! . . fieroprocessar based industrial application: - Microcomputer Mlenfanplest and cheapest general purpose microprocessur-based systems are mum possible hardware & software configuration, The microprocessor comprises of all the functional elements of CPU af any general- urpose computer. A microprocessor with all functional elements ie. ALU, control unit, and register section is fabricated on a single IC, As a result, it has inherited all the characteristics of an IC, Components of a microcomputer: (a) Memory Unit is purpose is to store both instructions & data. It is also called the Random-Access Memory (RAM) because the CPU ean access any memory location at random (bp) CPU jtacts as the brain of the computer and performs the bulk of data processing operations in acomputer. The two main units of'a CPU are the Arithmetic Logic Unit and the Program Control Unit. The important parts of CPU are: (i) Arithmetic Logic Unit (ALU): It performs instructions related to arithmetic operations like ADD, SUB, MUL etc, and logical operations like AND, OR etc. (ii) Program Control Unit (PCU): It interprets & sequences instructions Le. interpret & sequences which instruction in a program is to be executed first. (iii) Register Sets: These are collections of registers that store data. (ce) Input-Output (1/0) Unit This unit provides an efficient mode ‘of communication between the central system (computer) & the outside environment. Through the I/O unit, programs & data must be entered into computer memory for processing & results abtained from computations must be recorded or displayed to the user. Microcomputers are designed to serve only one user at a timey although they can often be modified with sofiware or hardware to concurrently serve more than one user. 5. a) How is pipelining achieved in 8086 microprocessor? [WBUT 2014, 2015, 2016] M&M-29pop! UBL IS Answer: Tstction: ‘queve Tnvietion register Fig: | Function units of 8086 The 8086 contains two functional units: a bus interface unit (BIU) and an execution unit (EU), as shown in Fig. 1. The BIU handles all interfaces with the external bus and generates external memory and I/O addresses. It fetches instruction codes from the memory and keeps them into a 6 byte instruction queue. It fills up the queue whenever the bus is idle and 2 bytes of the queue are vacant. In case of JUMP and CALL instructions, the BIU reads data from the memory and ports and writes data to the memory and ports. The execution unit (EU) receives prefetched instructions from the queue, decodes them and then executes them, The queue acts as the first-in-first-out for EU, If the queue is empty, the EU waits till the queue gets at least one byte. Such situation arises after the execution of a jump instruction. The EU also informs BIU where to fetch instructions of read data from. While the EU executes instructions, the BIU fetches instruction codes from the memory. Thus, there is an overlap between instruction execution and instruction fetching. The design feature of a processor which provides overlapping among the various operations t be performed by the processor is. called pipelining, To achieve pipelining, several functional units can be employed in a microprocessor. They work simultaneously if parallel. Each functional unit performs one type of operation, In 8086, BIU and EU are two functional units and they work independently in parallel, ; ° b) What is the difference between 8086 and 808g microprocessor? [WBUT 2014] M&M-30MICROPROCESSOR & MICROCONTROLLER OCONTROLLI anster difference between an 8088 microprocessor an neon the 8088, the BIL data bus path is 8 hits wide pi! “airterence 18 that the 8088 instruction queue is f i i u 8 four bytes I . pate stant point 10 note, however, is that because the Eu is ie ne te ak ‘ogramming instruction 2) : essot, the een se ie aus ail are exactly the same for each. Programs written rr the 086 can without any changes dan 8086 microprocessor is the versus the 8086's 16-bit data bus. jain how 20-bit physical address is generated i a Mat I the purpose of queue? How many words teen in the 9098 microprocessor? [WBUT 2016) er: 7 g086/8088 microprocessor there are 20-bit address lines of IGbits in length. fore to obtain 20-bit addresses from the available 16-bit registers, all BOBG/R088 mory addresses are: computed by summing the contents of a segments register and a afiective memory address. The effective memory address is computed via a variety of addressing modes, The process of adding to obtain 20-bit address can be analysed as under. 3 3 First selected segment register contents are shifted-left four bits (i.e., the contents are multiplied by 16 decimal) and then added to the effective memory address to generate the actual physical address output. Table below, depicts 16-bit of segment registers CS, DS, ES or S$ which are displaced by 4-bits to left. Segment Register value | XXXXXXXXXXXXXXXXH (CS, DS, ES or SS Effective Memory yyyyyyyyyyyyyyyyH Address Physical Address WWW WWW WWW WWW Www wow wow ow WL Effective address is calculated depending on the type of addressing mode, shown as “yyyyyyyyyyyyyyyy”. The 20-bit physical address “wwwwwwwwwwwwwwwww www" is obtained later adding the segment register value and effective address. (Physical address in 20-bits wide). To know how the segmentation is used, it demands to know the memory structure of the 8086/8088 microprocessor. b) 1" part: The 8086 instruction queue is a buffer that holds opcode bytes that have been prefetched by the bus interface unit. This speeds up operations of the processor by helping to reduce fetch latency, i.e. to improve the probability that an opcode byte fetched by the processor is already available, This works best when there is no branching, &a branch would invalidate the queue. a 2 part: 8086 queue contains 6 bytes or three words. The queue was shortened to Prevent overuse of the bus by the BIU when prefetching instructions. This was required use of the additional time necessary to fetch instructions 8 bits at a time. M&M-31POPULAR PUBLICATIONS - in 8086 mw Buy 21g ‘what are the flags 7. a) How 8086 achieve pipelining? y Answer: the BIU fetches instruction codes fr Ure While thelU etecuies inet erocion execution and instruction feat ie i rlap betw i ing amoi ing. he deen Rane ofa po whieh provider Ore cats achieree aton, operstions to be performed by the processor iscalled’ PPE NT Oo Seis several functional units can be employed in @ eee pnetation in B86, BIL wateougy in parallel. Each functional unit performs one Haat parallel EU are two functional units and they work independent!y 2" Parts Refer to Question No. 3 Short Answer Type Questions. b) What are the various interrupts in 80867 Give example of swan meshaty interrupt in 8086. : 18) Answer: I" Part: : . / The differemt types of interrupts present in 8086 microprocessor are given by: Hardware Interrupts: Hardware interrupts are those interrupts which are caused by ayy peripheral device by sending a signal through a specified pin to the microprocessor There are two hardware interrupts in 8086 microprocessor. They are: (A) NMI (Non Maskable Interrupt) —It is a single pin non maskable hardware interrupt which cannot be disabled. It is the highest priority interrupt in 8034 microprocessor. After its execution, this interrupt generates a TYPE 2 interrupt, IP is loaded from word location 00008 H and CS is loaded from the word location 000A H. (B) INTR (Interrupt Request) —It provides a single interrupt request and is activated by I/O port. This interrupt can be masked or delayed. It is a level triggered interrupt. It can receive any interrupt type, so the value of IP and CS will change on the interrupt type received. Software Interrupts: These are instructions that are inserted within the program to generate interrupts. There are 256 software interrupts in 8086 microprocessor. The instructions are of the format INT type where type ranges from 00 to FF. The starting address ranges from 00000 H to 0O3FF H. These are 2 byte instructions. IP is loaded from type * 04 H and CS is loaded from the next address give by (type * 04) + 02 H. Some important software interrupts are: (A) TYPE 0 corresponds to division by zero (0). (B) TYPE 1 is used for single step execution for debugging of program. (C) TYPE 2 represents NMI and is used in power failure conditions (D) TYPE 3 represents a break-point interrupt, (E) TYPE 4 is the overflow interrupt, 2™ Part: The interrupt initiated through NMI pin and all software interrupts are 0" maskable. M&M-32ICROPR MICROCO; 1 ibe Min/Max mode of operation in 8086, a wer: Refer 10 Question No. 9.a) of Long Answer type Questions. ig. what #8 addressing mode? How many addressing mode are in 8085? Give 8. ample for each mode. [WweuT 2018) swe! ; s jaressing Mode: The term addressing mode refers to the way in which the operand of Ad‘ jatruction is specified, The addressing mode specifies a rule for interpreting, or modifying the address field of the instruction before the operand is actually executed. so, the Way of specifying data to be operated by an instruction is called addressing ty of addressing modes: 11 8085 microprocessof there are 5 types of addressing modes: 1 Immediate Addressing Mode - jnimmediate addressing mode the source operand is always data, If the data is 8-bit, then the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes. mples: MVE iy 45 (move the data 45H immediately to register B) EX H 3050 (load the H-L pair with the operand 3050H immediately) JMP address (jump to the operand address immediately) 1, Register Addressing Mode — In register addressing mode, the data to be operated is available inside the register(s) and register(s) is(are) operands ‘Therefore the operation is performed within various registers of the microprocessor. 2 Examples: MOV A, B (move the contents of register B to register A) ADD B (add contents of registers A and B and store the result in register A) INR A (increment the contents of register A by one) 3, Direct Addressing Mode ~ In direct addressing mode, the data to be operated is available inside a memory location and that memory location is directly specified as an operand. The operand is directly available in the instruction itself. Examples: LDA 2050 (load the contents of memory location into accumulator A) LHLD address (load contents of 16-bit memory Jocation into H-L register pair) IN 35 (read the data from port whose address is 01) 4, Register Indirect Addressing Mode — IN register indirect addressing mode, the data to be operated is available inside a memory location and that memory location is indirectly specified b a register pair. Examples: ss MOV A, M (move the contents of the memory location pointed by the H-L pair to the accumulator) LDAX B (move contains of B-C register to the accumulator) M&M-33POPULAR PUBLICATIONS 5 of the location 9570) 5 ie addres LXTH 9570 (load immediate the HL pa wih aaa eG -ssing Mode — iad and the data to be opera th implied/mplic dressing rede the operand BUEN ia available in the instruction itself. Examples: CMA (finds and stores the 1°s complement of the © RRC (rotate accumulator A right by one bit) RLC (rotate accumulator A left by one bit) [MODEL QUESTION, ontains of accumulator A in A) 8. Draw the architecture of 8086. Answer: 5 The Intel 8086 is a 16-bit mnicropt oo Apter microcomputer, The term “16-bit” means that its arms” . and most of its instructions are designed to work 16-bit binary were Tee a 54 data buts and 20-bit address bus. Words will be stored in two consecutive Ory locations. If the first byte of a word is at an even address, the 8086 can read the entire word in one operation. If the first byte of the word is at an odd. address, the 8086 will read the first byte in one operation, and the second byte in another operation. Following figure shows the internal block diagram of 8086 microprocessor. tended to be used as the CPU in 4 thmetic logic unit, internal registers, 8086 Internal Block Diagram: Refer to Chapter at a Glance. 10. Explain with diagram the hardware architecture of 8085 microprocessor. [MODEL QUESTION] Answer: The internal architecture of 8085 is best understood from the picture below. The “brain” of the microprocessor is represented by the box titled “Timing and Control”. This is the sequential machine that we have talked about earlier. Note that the ‘input’ to the timing and control logic comes from the next “instruction” of the currently running program. Data movement inside 8085 in achieved through an internal bus. From a user's point of view, there are two sub-units that are interconnected through this bus: « The Arithmetic and Logic Unit (ALU) with Accumulator and Flags * The Register Bank Arehitecture of 8085 (diagram): Refer to Chapter at a Glance, The ALU is a component of the microprocessor that carri ic (like add, subtract, ete.) and logical (like bit-wise AND, bit-wise OR. sein vauins ee inp operands and produces an output. The 8085 is basically an “one address machine” al arithmetic/logical instruction mentions or identifies one of the two input operands, The first operand, which is also the storage location of the output, is implted ee case of 8085, this is the Accumulator, In order to carry out an ADD operation (sa ), at first, the first operand is loaded on to the accumulator and the second operand to a internal B-bit Fegister. An instruction then mentions the operation (in this ase ADD) as well as the second operand. For 8085, the second operand has to be an internal 8-bit register. The Mana ayas the operation and stores the result back to the A we TADD C (where C is an internal 8bit register) therefore fan ans ins alaior © Accumulator + (C) see flags Are sue PT og Zero Flag. SET when the result of last operation leaves all zeroes, gor Sign Flag. SET when the last operation makes bit-7 (i.c., the most significant pit) of the result 1. por Parity Flag. SET when the last operation leaves an even number of I-s in the result. C of Carry Flag. SET when the last arithmetic operati borrow out of the most significant bit. sree Involves a Sey" or ‘AC or Auxiliary Carry Flag. bp? D6 SA ao $ Zz x Tac T= TP *_ Ley] ioe: The flags are actually a part of an intemal 8-bit register referred to as “Flags”. The jayout 8 MORE. The only two instructions that refer to the flags register directly are POP pay, and PUSH PSW, See LATER for deuals jster Bank . ‘pee ate seven internal 8-bit registers that can be referred to by instructions. They are called B, C, D, E, H, L and A, The A register is actually the Accumulator that we have faked about in the discussion on ALU. We know that three bits are required to encode ‘even entities. Indeed, the bit encoding of the registers in the relevant instructions is as follows: Bit-2 Bit-l Bie | Register 000 B ool c O10 D oll E 100 H LoL L. eo aes Deer ee Additionally, several 8085 instructions treat the first six of the registers as three 16-bit registers which are referred to as “register pairs”. Thus we have the BC register pair (C lower 8 bits, B --> higher 8 bits), DE register pair and HL register pair. hhstructions that refer to register pairs are also grouped in two classes. One class treats the PSW, a pair constituted of Flags and Accumulator (Flags > lower 8 bits, A > higher 8 a register pair while the ather class treats the Stack Pointer at par with the register Is, j ‘1. Write short notes on the following: 4) MinMlax mode i ti if 8086 microprocessor es m [WBUT 2010, 2012, 2014, 2016) M&M-35POPULAR PUBLICATIONS [WBUT 2011, 204 b) Designing 0 ports [weur 2) intel 8086 programming model 2013 4 Wrirerence betwee into 8086 & 8088 processors at 201 6) Difference of 8086 and 8085 mocks oun f) Tri state devices TION Answer! . i jeroprocessor a) Min/Max mode operations of 8086 microp! ae ee ifthe MNIMX’ pin iy bitsy Minimum Made: ‘The 8086 operates in Minimum Moe 5 reset, Pins 24 through 31has meaning as deseribed in the table above, This mode js cheaper since all control signals for memory and W/O are generated by the microprocessor. . + ist Maxineun “Mode: The 8086 operates in Minimum Mode if the MN/MX' pin is Low during reset. Pins 24 through 3 thas meaning as described in the table above. Quite a few of the control pins are not available directly but rather, has to be generated by decoding the $0, $! and 82 pins. Maximum mode is designed to be used when other processors, for example, a math coprocessor (8087), exists in the system. Some of the control signals must be generated externally, due to redefinition of certain control pins on the 8086. This requires an external bus controller, normally the 8288 Bus Controller. A typical Maximum Mode configuration using 8288 is shown below. my ‘am RESMICROPROCESSOR i& MICR( LLL pesigning VO ports: oe amnred 1/O: 'n programmed 1/O the data transfer is accomplished through an 1/0 ‘controlled by software supe driven 2/0: In interrupt driven WO, the 1/0 device will interrupt the processor, and initiate data transfer. iret mernory access (DMA): In DMA, the data transfer between memory ard WO can te performed by bypassing the microprocessor, vo Programmed 1/0 Intersupt A)—_irect Memory Access Standard 11 Memory Black Cycle Demand or Mapes 110 transfer stealing weanaler Isolated VO DMA DMA DMA Pott Lo Extemal Internal, Maskable Non-maskable Due 10 Software exceptional interrupts conditions ¢) Intel 8086 programming model ‘The programming model of an microprocessor includes i) Addressing modes, i) Register set, ii) Memory segments iv) Segment registers, v) I/O space ‘8086/8088 Register Set 108i “Generar Regie: 0 Accurnuator (S| CLE) | 1 Counter Dx{DH (6) | BLE) | 20st exam A) ate 8F <4 Stack Pointer ppl] SBasePoimar si Source tte Destination Index Sogmen Rogizieis Es OExtra Segment cs 1 Code Segment, 38 2 Stack Sagmont DS) ‘2 Data Segment ram Flagisters Pr Instruction Pointer eo) em Programming Model of 8086 M&M-37POPULAR PUBLICATIONS ) Difference between f Refer to Question No. ¢) Difference of 80 in the changing wor look at the changes be 86 and BOBS: : Jd of technologies. the devi tween 8085 series 0! ntel 8086 & 8088 processors 5 (b) of Long Answer Type Questions. ces used are also changing. Let us take { microprocessors and 8086 series of 8086 Microprocessor microprocessors. i cessor a ria The data feu ur bis. ‘The data bus is af 16 bits. 2. The address bus is of 16 bits. ‘The address bus is of 20 bits. 3. ‘The memory capacity is 64 KB. ‘The memory capacity is | MB 4. The input/output port addresses are of & ite input/output port addresses are of g it its. 5 ae operating frequency is 3 MIIz. ‘The operating frequency is 5 MHz, & not has mulliplication and division [thas multiplication and division instructions. instructions. 7 It does not support pipe-lining. It supports pipe-lining as it has two independent units Execution Unit (BU) and Bus Interface Unit (BIU). 8 It does not support instruction queue. It supports instruction queue. 9, Memory space is not segmented. Memory space is segmented. It consists of 9 flags (Overflow Flag, f) Tri state devi consists of $ flags (Sign Flag, Zero Flag, Auxiliary Carry Flag, Parity Flag, Carry Flag). Direction Flag, Interrupt Flag, Trap Flag, Sign Flag, Zero Flag, Auxiliary Carry Flag, Parity Flag, Carry Flag). The tri-state logic devices have three states: logic 1, logic 0 and high impedance. Tri-state logic devices are essential for proper functioning.of the bus-oriented system, in which the same bus lines are shared by several components. a tri-state logic device has an additional control line called an “Enable” line. When this ie ae the tri-state device function the same way as ordinary logic devices. And 2 om is line is deactivated, thé logic device goes into a high impedance state, and it acts if it were disconnected from the system. In the high impedance state, no current is required practically, to drive the device, , Examples of tri-state devices: i) Tri-state buffer: 4) Tri-state inverters: ve Guta “ (Active low) Enable G (Active high) {Active low) (a) (ii) (b) M&M-38, In the figure @), when the enable line is active high the logic device works like a normal inverter ‘And when this enable line is kept low the device goes into high impedance state. In the figure (b), the enable line has a bubble, which indicates active low enable input. ‘This logic device works as ordinary inverter whén enable input is tow, and stays in high jmpedance stare when enable input is high. i MICROPR CR OU Need of tri-state devices: ‘The tri-state devices are critical to. proper functioning of the microcomputer. Ina microcomputer system, peripherals are connected in parallel between the address bus gnd the data bus. Since the tri-state logic devices are used in the system, these peripherals do not load the system buses. Hence to avoid loading of the system buses, it is necessary jo use tri-state logic devices in the system. The microprocessor communicates with one peripheral at a time by enabling the tri-state line ofthe interfacing device. M&M-39PUI UBI wiTH PERIPHERALS INTERFACING Chapter at a Glance A/D & D/A converter: An A/D & like below. j Wok #) mt Ve (4) i ¥oal-) 3 — n= | Dex ir ADCOSO! 10k CLK IN ore Tare @ converter can be interfaced with a DB; 8085 microprocesss, a i To Data Bus To 8085 RST 6S From address decoder iow M&M-4010) perfacins of 8255 with 8085: In ouT First, let us look at the interface between the 8253 and the microprocessor. The 8255 is connected to the microprocessor through an 8-bit data bus, 2-bit address-bus, the RD’ and WR’ pins, the RESET pin and a CS’ pin. Reset A *high’ on this input initializes the control register 9BH and all ports are set to input mode. The last mentioned pin is called'the “Chip Select" pin and all activities between $255 and microprocessor can happen only if this pin is LO. Typically, in an 8085 based system, one would decode some value A2 through A7 and 1O/M’ in 10 mode, to generate the chip-select logic for an 8255. ‘The table below explains that. Al [Ae [RD [WR [CS_ | Operation 0 0 {0 u 0__| Port-A © Data Bus | 0 1 [0 1 0 | Por-8 € Data Bus i oo i 0 | Port-C € Data Bus I 1 {0 1 0 | Control Word € Data Bus 0 ofa 0 [0 | Data Bus € Por A 0 1 1 0 0 Data Bus © Port B | 1 oii o {0 1 Data Bus € Port C LL L i jo 10 Data Bus € Control word Interrupts: The external interrupt flags are cleared on branching to Interrupt Service Routine (ISR), provided the interrupt is negative edge triggered. For low level triggered external interrupt as well as for serial interrupt, the corresponding flags have to be cleared by software by the programmer. M&M-41POP! ATIONS i interrupts is as follows: ‘The schematic representation of the interrupt tices, Insesrupt {19 }-—* noo TFO- oO ors intl i wae Lal site cr n 002311 RI Fig: 8051 Interrupt Details Interrupt Enable register (IE): Address: ASH vs 6 5 4 3 2 1 0 EA] — Jers] es [erifexi] ero] exo] EXO ————+INTD interrupt (External) enable bit ETO ———— Timer-0 interrupt enable bit EX] ————+INT1 interrupt (External) enable bit ET| ————* Timer- | interrupt enable bit ES ————>Serial port interrupt enable bit ET2 ————+Timer-2 interrupt enable bit EA —————P Enable/Disable all Setting 'I' ————* Enable the corresponding interrupt Setting 0 ————* Disable the corresponding interrupt Multiple Choice juestions 1. Which of the following is hardware interrupt? [WBUT 2007] a) INTA b) TRAP c) RSTn 4) INT Answer: (b) 2. An 8-bit A/D converter ie aresolution of {WBUT 2007] 1 I 1 a) = b) — ae ) # ) sr <) 7 9 oe Answer: (b) . 3. For 8255 PPI, the bi-directional mode of operation is supported in [WBUT 2007, 2008, 2010, 2016, 2018] a) Mode 4 b) Mode 2 ianewer: (6) ¢) Mode 0 d) Either (a) or (b) M&M-42MICROPROCESSOR & MICROCONTROLLEI request is sent to the micro om Processor with a hi 4 fre microprocessor acknowledge the roquoat rere anel toe a pity after completing the present cycle 2008 201052 mediately after receiving the signal im by Kor completing the program G} none of these pane 2) contro! signal, ‘HOLD’ Is sent to 8086 in order to [weut 2008} hes i a) inform 1/0 device that the address is bei . 2) (ipleve separation of address from data Bent cette AC Sine ¢) synchronize with low speed peripheral q) to activate DMA answer: (4) 6, The number of bytes of RAM contained in 8155 is. [WUT 2008) a) 256 b) 512 ¢) 1024 d) 2K Amswer: (a) 7.1n 8085 microprocessor, which of the following is non-maskable interrupt? BUT 2009, 2017] a) RST 7.5 b) TRAP c) Hold d) INTR ‘Answer: (b) 8. RST 7.5 interrupt is [WBUT 2009] b) vectored& non-maskable a) vectored & maskable 5) direct & maskable Answer: (2) 4) direct& non-maskable 9, The stack and the stack pointer [WBUT 2009] a) both reside in memory b) both reside in the CPU ¢) former resides in memory but the latter in the CPU d) former resides in CPU but the latter chip in the memory. Answer: (¢) 10. The number of I/O lines for 8255 chip is (WBUT 2009), a) 16 bb) 32 c)8 d) none of these Answer: (¢) 11. 8259 is [WBUT 2009, 2012] a) programmable DMA controller b) programmable interval timer c) programmable interrupt controller d) none of these Answer: (c) M&M-43PO! AR P ‘ATIONS DWBUT 20%9) in order to 12. The control signal, HOLD is sent by $ne° ting sent over the AD line a) inform W/O device that the address is Di b) achieve separation of address from fo ¢) synchronize with low speed periphé! d) to activate DMA Answer: (d) 7 — ‘ 1 by default is 2010) 13. For 8257 controller, the highest priority Char°h y d)any channe, a) CH-0 b) CH-3. Answer: (a) an VO operation and memor, 14. The control signal used to distinguish between [BUT 2010) operation is io 4) SOD a) ALE b) 1O/M oS! Answer: (b) 15. Machine cycles in “CALL” instruction of 8085 CPU are a 2046] a6 b) 5 4 Answer: (b) s [WBUT 2011] 46. RST 7.5 interrupt is a) Vectored ond Maskable b) Non-vectored png Mest c) Non-vectored and Non-maskable d) Vectored and Non-maskable Answer: (a) 47. An 8 K * 8 ROM, holding the monitor program in a microprocessor trainer kit has the end address. [WBUT 2011] a) 8000 H b) 4000 H c) 1 FFF H d) 3 FFF H Answer: (c) 18. The total I/O space available in 8085 if used peripheral mapped WO [WBUT 2011] a) 64 c) 256 d) 512 Answer: (c) ‘ 19. 8251 is a [WBUT 2011) a) USART IC b) Counter ¢) interrupt controller d) none of these Answer: (a) 20. In DMA operation data transfer takes place between {WBUT 2012) a) memory & CPU b) CPU & 1/0 c) 0 memory d) different CPUs Answer: (c) [wut 2012] 21. The programmable interval timer is a) 8253 b) 8251 c) 8250 d) 8275 Answer: (a)MI Py MICROPROCESSOR & MICROCONTROLLER ay flag registers are in 8051? 2. per Y b)8 ae [waut 2012] oe (None of these) ays AP Is an 088, Trnaskable cantina weuT 2012] i a ‘ ies ster iomporry powertaure —) ona zag svmoune Answer (c) 24, How Auld hardware interrupt requests a single interrupt controller IC82Z59A can proc {UT 2012) a8 beats ¢) 16 dies ‘answer: (8) 25. The interrupt masks in 8085 can set or reset by the instruction _ [WBUT 2042] a} El b) DI c) RIM d) SIM Answer: (4) 36. The vecter address corresponding to software interrupt command RST7 in g085 microprocessor IS [WBUT 2012, 2016] a) 0017 H b) 0027 H c) 0038 H d) 0700 H Answer: (C) 27. The interfacing device used with an output port is [WBUT 2013, 2016] a) buffer b) priority encoder —_c) latch d) none of these Answer: (a) 28. The signal which has the highest priority is [WBUT 2013] a) TRAP. b) RST 7.5 c) RST 6.8 d) HOLD Answer: (d) 29. The mode 3 operation of 823 timer is [WBUT 2013, 2017] a) Square wave generator b) rate generator c) software triggered strobe d) hardware triggered strobe Answer: (a) 30, 8253 has [WBUT 2014, 2016] a) 6 modes of operation b) 5 modes of operation ¢) 4 modes of operation d) 3 modes of operation Answer: (a) (WBUT 2014] b) parallel-to-serial converter d) all of these 41. The USART perform 4) A serial-to-parallel conversion ©) control and monitoring function Answer: (c) M&M-45i amin the following —[WBUT 2914 fh one of ) 32. The bit Sct Reset mode in 8268 is used oy port C d) none Of these a) port A b) port B deere (0) f 8036 microprocesso,> Which one of the following is the software interrupt o QWBUT 2044 33. ich on d) Trai ST 7.5 b) EI c) RST 4 eae a) RST 7.! Answer; (c} ble interrupt of go 34, Which one of the following is not @ NON-Mask 2 [wauT 2015, microprocessor? ii ¢) RST7.5 d) RST3 a) TRAP b) I Answer: (a) memory chip is [WBUT 2015) 35, Address lines require for 64 k-byte ae 4) 16 a) 13 by 14 Answer: (d) [WBUT 2018) 36. How many modes are there in 82537 aya ] a)s b) 6 7 Answer: (b) 37. The port of 8255 which can be used in /O mode is sar aa a)PortAonly —_b) Port B only ¢) Port C only pol Answer: (d) 38. For 8255 PPI, bi-directional mode of operation is supported in _ [WBUT 2046] a) Mode 4 b) Mode 2 c) Mode 3 d) Either (a) or (b) Answer: {b) 38. Which is the BSR control word to set PC4? [WBUT 2016} a) OSH b) O7H c) 04H d) 05H Answer: (a) 40. The call location of RST 7.5 interrupt is [WBUT 2017] ana! ae a b) 002CH c) 00344 ) 0000H nswer: (a 41. To select Port B of 8255m AO and At are [waur 2017] a) 00 b) 01 c} 40 Answer: (b) d) none of these 42. Data i 5 ata bus of a microprocessor is [WBUT 2016) freee ’ ie b) bi-directional ¢) Both (a) & (by d) None of these M&M-46yo MICROPROCESSOR & MICROCONTROLLE gress lines required for 32 k-byte memory chi : ip ari a) 13 by14 6) 15 ° en ane] ase © which is the highest priority interrupt? 2018) a) TRAP b) RST6.S c) RSTS.5. eats: 4 answer? oe ww order to enable TRAP interrupt, which of the following instruction are needed? [waurT 2018] a) El b) SIM c) El & SIM d) None of these answer: (2) ag. The ing an 1 MHz clock is: a)t microsecond ¢)-4096 microsecond ‘Answer; (b) 47. The number of 16 bit timer/counter register present in 8054 is a)2 b) 3 Answer: (2) conversion time of a 12 bit successive approximation type A/D converter {MODEL QUESTION] b) 12 microsecond d) 4085 microsecond [MODEL QUESTION] 4 a) Short Answer juestions: 4. Distinguish between S/W interrupts microprocessor. Answer: Software Interrupts Software interrupts are software instruction when they are executed, CPU branches to interrupt service routine. ‘They are similar to CALL instructions and generally the length of software intertupts are less than CALL. i) Software interrupls are slower hardware inteerupts than’ Example of software interrupts are RST 0, RST 1, RST 2, RST 3, RST4, .... RST? 2. What do you mean by Vectored & Non call location. What is vectored and non: OR, What are vectored and non-vectored interrupts? vectored interrupt? Give examples. in Intel 8085 [WBUT 2007] Hardware Interrupts if 7) Hardware interrupts are physical inputs \ from extemal devices which causes CPU to branch to interrupt service routine. and HW interrupts | Ty Hardware interrupts are faster tan | software interrupts. | iii) Example. of hardware interrupts all TRAP, INTR, RST 5.5, RST 6.5, RST 7.5. .vectored interrupt? Also write down their [WBUT 2007, 2011] [WBUT 2014] [WBUT 2018] M&M-47POPULAR PUBLICATIONS Answer: ts Vectored interrupted are those 11 whi and semi hardwired, ae 68 0) Non vector are those in which the addres externally. : oat Vectored int cation in HEX ie ae of the service routine is Hatin Md f the service routine needs to be Supp led Interrupts 024 food [TRAP ___—1 993 RST a5 we 7 RST65 a RST5.5 (aoe verre intert x Call location if [_Intermupts __——--g RSTO RST I 0008. RST? 0010 fests «iO 0020 RST 4 RSTS 0028 fRsté” 0030 [Rst7— 0038 3. What are the functions of RESET, HOLD, INTERRUPT & READY pins? [WBUT 2007, 2011} Answer: RESET: When the reset pin is activated by an external key (also called a reset key), all internal operations are suspended & the program counter is cleared (it holds 0000H), Now the program execution can again begin at the zero memory address. HOLD: When the HOLD pin is activated by an external signal, the microprocessor relinquishes control of buses and allows the external peripheral to use them. INTERRUPT: The microprocessor can be interrupted from the normal instructions and asked to execute some other instructions called a service routine. The microprocessor resumes its operation after completing the service routine. READY: The 8085 has a pin called READY. If the signal at this READY pin is low, the microprocessor enters into a Wait state. This signal is used primarily ta synchronize slower peripherals with the microprocessor, execution of 4. What is Fixed Priority Mode and Rotating Priori i and Non-Maskable Interrupt. Ss SHonky Move? Defing Twat 200" Answer: The TRO has the highest priority while the IR7 has the lowest one, normally in fixed priority mode. The priorities however be we rotating priority mode. fae) Delica propreraaing the Be M&M-4gICROPR f& MICROCO! LE riority Mode: These ar ‘ ‘ oy lowest. fe general purpose mode in which all IRs arranged from ‘The 1RO has ee while the IR7 has the lowest one. ting Priority Mode: Here the priorities | i BG " ee, rotting prlortty moda: pI however may be altered by programming askable interrupt (IRQ): Itis a hardware interrupt that may be i i : a): d ignored by setting a bit jan interrupt mask Tepistet’s CMR) bit mask. Maskable interrupt is that ae Seenigk Mpich ean be enabled or disabled using El and DI instructions, Example; RST7.5, RST G5. RST SS : 7 nossmaable interrupt NM It is a hardware interrupt that lacks an associated bit- raask, so that it can never be ignored, Non-maskable interrupt is that type of interrupt wnitich eannot be enabled or disabled using El and DI inatructlgss Example; TRAP. igh 5. What are two key lockout and N-key roller mode in 82797 [WBUT 2008] Answer: In 8279, when the input mode is programmed to be “Scanned Keyboard Mode”, the two keyboard modes “2-Key lockout” and “N-Key Rollover” modes apply Inthe “Scanned Keyboard Mode”, when a key is pressed, a debounce logic comes into operation. During the next twa scans, other keys are checked for closure and if no other key is pressed, the first key is identified and entered into the FIFO. If the first key is released before the others pressed with two scans, the first key is ignored, If two keys are pressed within @ debounce cycle, no key is recognized till one of them is released while the other remains closed. In that case, the last key that remains depressed is returned in the FIFO. : In“N-Key Rollover mode, each key depression is treated independently. Whena key is sed, the debounce logic waits for 2 scans and checks whether the key is still depressed and if'so, it is returned to the FIFO, In this mode, any number of keys can be pressed simultaneously (i.¢., another pressed while one or more of the previous keys still pressed), all the keys are returned to the FIFO in the order they were pressed. ~ [WBUT 2008} pres 6, a) Write the BSR control word for setting PC4 in 8255 A. Answer: BSR control word for setting PC4 in 82534 is 89H. b) Explain the burst mode data transfer and cycle stealing in context of DMA data transfer scheme. [WBUT 2003] Answer: Burst Mode: The CPU is kept in the HOLD state while peripheral transfers several bytes of toffrom memory. The CPU may remain ‘inactive’ for a arbitrary and not of time depending on the amount of data transfer. Data transfer is fastest possible. Cycle stealing Mode: The CPU is kept in the HOLD state exactly during its “bus-idle” (Le. instruction decode/execution) time. During this time, the peripheral transfers ONE byte of data directly to/from memory. No CPU time is wasted. However, data transfer is slower, M&M-49POPULAR PUBLICATIONS [WBUT 2008 2014 7. What is polling in 8259? , nitigtiae Answer: pet jn OCWS IS used when tl : led th; ( ‘The Polled mode, enabled by seting P 73959 (by not eres ane bin i T output 0! wpead” of the ated as suing hecrope wie cr aa a in there has been a request and Puls on interrupt acknowledge, sets the appropriate erupting line. see ie is useful jp - ded IR-level © that the sequence j ire peieune ce common to several levels ne cone ik ion Ga on ‘ needed. Sometimes, if several devices send Lasuaruiees and find out which one REL poll command can be used to individually examine servicing al the 8085 pP to periodically tum On and off ee mmodies The duty cycle is 50%. 8. Write a program in assembly languag' [WBUT 2008, 2015) two switches by setting up 8255 PP! to B: Answer: F We assume that the 8255 is connected to VO address 80H. We mse oe = tates are connected to PC4 and PCS of $255. We also assume that the as been programmed to operate in Mode-I or Mode-2. BACK:MVLA,89H 5 (A) € 10001001 OUT 83H ; Turn on switeh at PC4 MVIA,8BH — ;(A) € 10001011 OUT 83H : Turn on switch at PCS CALL DELAY; Introduces séme delay = 0.5 time-period MVIA, 88H. + (A) © 10001000 OUT 83H : Tum off switch at PC4 MVIA, 8AH 3 (A) © 10001010 OUT 83H ; Turn off switch at PCS CALL DELAY; Introduces some delay = 0.5*time-period JMP BACK 9. An 8 bit binary number (e.g., 9FH) is stored in memory location 8050H. Write a program in assembly language for 8085 uP to a) transfer the byte to the accumulator. b) separate the two nibbles (as 09 and OFH). c) call the subroutine to convért each nibble into ASCII Hex code. d) store the codes in memory locations 8060 and 8061H. [WBUT 2008) Answer: We _ the program for all the four parts as a contiguous piece of code. We store the two nibbles as bytes in B and C registers. Also, we store hex of | ibble in 8060H and hex of higher nibble in 8061H, ee LDA 8050H ; For first part HOY GA ; Temporarily store the original value RRC RRC M&M-50- MICROPI OR & MICROCONTROLLER ; Shifted the higher nibble to lower nibble se } Mask out the higher nibble eee ; Store in B. HOES | Get original byte wen a ; Mask out the higher nibble a A ; Store in C WiC: Gettower nibble ae NIBBLE2HEX CAL" Call subroutine 60 sk E « Get higher nibble cal NIBBLE2HEX. + Call subroutine gra 8061 40, Specify the entire memory map of the schematic shown in the figure and explain the significance of the don’t care address line on memory address. [WBUT 2008] 2B 4 wo vo Answer: Here All isa “don’t care” address line, ie., it can. be either 0 or 1. 0000H - 07FFH. If Al] =0, the address map of the RAM is If All = 1, the address map of the RAM is Q80OH-OFFFH. The significance of the All don’t chre address line is to “alias” the physical memory bank to the portions of the 8085 CPU's address map as shown above. 41, How does the ALE signal demultiplex the ADO-7 bus? Explain with diagram. [WBUT 2009, 2014) OR, Explain the need to’ demultiplex the bus (ADT-ADO. How is demultiplexing done? [WBUT 2010} oR, Explain the need to de-multiplex the bus ADO-AD7. Show how it can be demultiplexed in 8085 microprocessor. [WBUT 2016] M&M-51IPULAR PUI TIO Answer: . One of the first things that an architect ofan 8085 based system needs to do is to Separaty out the data and the address busses on the ADO-AD7 pins. Since the address bys it: unidirectional, we can do this by using a (unidirectional) “Jateh” array. A “latch” is basically a flip-flop. It has an input, an output and a control pin. When the control is 1, the input is ‘passed on to’ the output. When ‘the control is 0, the Previously ‘passed on’ value remains on the output, A common logic IC, 74373 (or, preferably, itg faster version 741.8373) that consists of an array of eight latches with a common contro} pin, is convenient for the purpose. The ALE signal on Pin-30 is fed to the control pin of 74L8373. A typical design looks like: Aus Ais a Aux Highs Ais Onder 8085 Au Address Microprocessor Ave Bus a As bs nue Fate AD; ‘ADs Ay AD. oa Ay AP, As Lowe 2. As Onder Address is Data Bus Fig: Schematic of Latching Low-Order Address Bus Note: There are some Intel manufactured memory/peripheral IC-s (for example, 8155) that were specifically designed for 8085 and themselves have a multiplexed address/dala bus. For such devices, it is alright to connect the ADO through AD7 pins of 8085 directly to the corresponding pins on the IC. . «The ALE signal on Pin-30 is fed to the control pin of 74L8373. 42. Compare the I/O mapped I/ 0 and Memory mapped I/O. [WBUT 2009, 2011] OR, Differentiate between peripheral mapped V/O and memory mapped /O. - [WBUT 2012, 2048, 2017] M&M-52SOPROCI Mi INTROLL OR, jate between Memory mapped I/O and lO mapped V/O. [WBuT 2018] VO-Mapped 10 fie TN and OUT instructions, Both are two | 1) Ma Momory-Mapped we —| < . ia im ic a instruction. In IN instruction, it reads data transferred hea instructions are used (0 by van input port and places the data into the : faulaiot and the OUT instruction, it sends the accumulator to the address port, Sj tri-state buffer is commonly used to | ii) To interta = = ii - * ce W/O devices, the entire bus eerface input sevice at atch is commonly | must be decoded to generate the device sed to interface eutpt cS. address pulse, which must be combined with the control signal MEMR/ MEMW to generate the VO select pulse which is used for data transfer In WO device. 43. Can an input port have the same address? Justify, [WBUT 2009] can an input port and an output port have the same address? Justify. [WBUT 2010] ‘Answer? eer ‘ ‘There is no restriction, imposed by a microprocessor for an i/p port having the same address a8 an o/p port. However, if the external circuit corresponding to port is not properly designed there may be danger of circuit burn out. (output to an input port). Or undefined data input (input from an output port). 44, What is the purpose of DMA controller? [WBUT 2009, 2015] OR, With respect to 8237 explain the DMA operation. [WBUT 2015) Answer: The 8237 DMA Controller The 8237 is a programmable Direct Memory Access controller (DMA) housed in a 40- pin package. It has four independent channels with each channel capable of transferring 64K bytes. [t must interface with two types of devices: the MPU and peripherals such as floppy disks. As mentioned earlier, the DMA plays two roles in a given system: It is an 1/0 to the microprocessor (slave mode) and it is a data transfer processor to peripherals such as floppy disks (master mode}, Many of its signals that are input in the VO mode become outputs in the processor mode, It also needs additional signal lines to communicate with the addresses of 64K data bytes, and these signals must be generated externally by using latches and buffers. The $237 is a complex device. To maintain clarity, the following discussion is divided into five segments: DMA channels and interfacing, DMA signals, system interface, programming, and DMA execution. “The Specification details of the 8237 are included in Appendix D M&M-53ULAR PUBLICATIONS: Functions of DMA Controller r : A wpical DMA environment is shown above, The following steps are performed when 1/0 device is to transfer data to memory. 1. VO device place a DMA request (BRO) to DMA controller. 2, DMA controller in turn places a hold request (HRQ) with the microprocessor. 3. microprocessor completes the current machine eycle and then tristates the buses ang send HLDA (Hold acknowledge signal) to DMA controller. 4. DMA controller takes control over the buses and send DMA acknowledge (BACK) to device. ADDRESS BUS Memory cru i DMA Controller HLDA’ DACK Fig: DMA operation 5. DMA controller now generates the address and required control signals (Read/Write). Data transfer now takes place between I/O device and memory. For proper functioning of the system, the DMA controller must be initially initialized. ‘That is the initial address and number of bytes are to be transferred should be entered in Byte count register and Address registers respectively 15. Explain the functions of pin as follows: [WBUT 2010, 2014] READY, ALE, RESET Answer: READY (pin 35) Used to insert wait states (controlled by memory and 10. for reads/\vrites) into the microprocessor. The ALE signal on Pin-30 is fed to the control pin of 74LS373. ‘The 8085 microprocessor can be reset by holding the RESET IN (Pin-36) input pin to 0 for a short duration, When reset, the 8085 lets its external environment know about it through the RESET QUT (Pin-3) output pin, 18. How is sub-routine handled by microprocessor? [WBUT 2010] M&M-54