Scribd
Upload
67 views3 pages

Sayan Chatterjee CV VLSI

Sayan Chatterjee is a Senior System Engineer at Cognizant Technology Solutions with 15 months of experience, specializing in Linux scripting and server monitoring. He holds an M.Tech in VLSI and has skills in Verilog, SystemVerilog, and various EDA tools, while currently pursuing further training in design and verification. Sayan has published research in academic journals and is proficient in multiple programming languages and operating systems.

Uploaded by

himani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
67 views3 pages

Sayan Chatterjee CV VLSI

Sayan Chatterjee is a Senior System Engineer at Cognizant Technology Solutions with 15 months of experience, specializing in Linux scripting and server monitoring. He holds an M.Tech in VLSI and has skills in Verilog, SystemVerilog, and various EDA tools, while currently pursuing further training in design and verification. Sayan has published research in academic journals and is proficient in multiple programming languages and operating systems.

Uploaded by

himani
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Sayan Chatterjee

Email id:[Link]@[Link]

Contact number-9748346073

Objective: To work in a professional atmosphere with a view to enhance my knowledge and


skills in my field of work and be able to develop my standards while meeting the
organizations’ goals as well as the individual goals.

Work Experience:- Currently working in Cognizant Technology Solutions. 15TH Months of


working experience.

Project name- Cengage Learning (US)

Current Role- Senior System Engineer

Tool used- Avaya CM,Verint,AD,Paralance,eCAS,CMS.

Job Description:- Working on linux scripting.

Monitoring different servers in client side and resolve the issues.

Create and validate user AD account.

Dealing with different server related issue and resolve those.

Solving different IP related networking issues.

Area of interest:

 VLSI frontend work. HDL Programming (Verilog) and ASIC Verification using
SystemVerilog.

 Extensive experience in writing RTL models in Verilog HDL and Test benches in
SystemVerilog and UVM(ongoing) .
 Experience in using industry standard EDA tools for the front-end design and verification.
 Currently pursuing a Design and Verification Training from the institute QSOCS
Technology, Bangalore.

VLSI Domain Skills

HDL: Verilog

HVL: SystemVerilog
TB UVM
Methodology:
Protocols: AXI, UART

EDA Tool: Aldec Rivera-Pro


Domain: ASIC front-end Design and Verification

Knowledge: RTL Coding, FSM based design,


Simulation

Other Skills:

 Language Known:- Verilog, SystemVerilog, C, JAVA.


 Operation System :- Linux/Unix, Windows 7,Windows 10
 Tool Known:- ,Aldec Riverapro (RTL designing and Verification),Cadence
(45nm,90nm,180nm)circuit simulation with Layout, Xilinx, Tanner EDA.

Education Qualification:-

College Degree/Exam Marks Year of pass


name/School name obtained(%/CGPA/YGPA) out
Heritage Institute [Link] (E.C.E- 8.25 2015
of Technology VLSI)
Pailan collage of [Link](E.C.E) 7.26 2013
Management and
Technology
Salkia A.S High W.B.C.H.S.E(XII) 65.2% 2009
School
Salkia Hindu High W.B.B.S.E(X) 73% 2007
School(Unit-2)

Projects/ Training:

 Design and Verification Training from QSOCS Technology, Bangalore which


includes

[1]RTL design of Synchronous and Asynchronous circuits.

[2] UART design in Verilog.

[3] UART Verification in UVM.

[4] AXI Verification.


 [Link] final year project “Study of 4*4 Wrap Around Barrel Shifter” undertaken
by college (duration-6months).

Achievements/ Certification:
1. IJECT journal publication on the topic of “Study of Power Consumption Using
the Schematic and Layout Designing of a 4*4 Wraparound Barrel Shifter” (IJECT Vol. 6,
Issue 2, April - June 2015).

2. IJIRCCE journal publication on the topic of “Study and Analysis of Full Adder in
Different Sub-Micron Technologies with an Area Efficient Layout of 4-Bit Ripple
Carry Adder” ( Vol. 3, Issue 6, June 2015).

Personal Details:-

 Date of Birth : 02/10/1991


 Gender : Male
 Languages Known : English, Bengali, Hindi
 Location : Bangalore, Karnataka

Sayan Chatterjee

You might also like