DIRECT MEMORY ADDRESSING DMA Pdf 18

What is DMA?

• DMA is a method that lets I/O devices transfer data directly to/from memory without the
continuous involvement of the CPU.
• This frees the CPU to perform other tasks and speeds up data transfer, as the transfer rate
depends only on memory and DMA controller speed.
• Common uses include DRAM refresh, video display refresh, disk reads/writes, and
high-speed memory-to-memory transfers.

How DMA Works (Basic Operation):

• When a device wants to use DMA, it sends a HOLD request to the CPU.
• The CPU samples this HOLD signal during its clock cycle.
• On recognizing HOLD, the CPU pauses its current execution and releases control of the
system buses (address, data, control).
• The CPU asserts HLDA (Hold Acknowledge) to signal it has relinquished bus control.
• The DMA controller takes over the buses and performs the data transfer directly.
• Once done, the DMA controller releases HOLD, and the CPU resumes normal operation.

HOLD vs Interrupts and Reset:

• HOLD signal has higher priority than interrupts (INTR or NMI).

o Interrupts wait for the current instruction to complete before servicing.
o HOLD can take effect in the middle of an instruction cycle, forcing the CPU to
pause immediately.
• The RESET pin has the highest priority, overriding even HOLD.

Visualizing the Process:

• Imagine the CPU working on instructions normally.

• A device sends HOLD.
• CPU stops and “steps aside” by making the buses high-impedance.
• DMA controller takes control, transfers data directly.
• After the transfer, CPU resumes.

Overview: Intel 8237 DMA Controller

 • Package: 40-pin DIP
• It manages 4 DMA channels (CH0 to CH3), allowing direct memory access transfers.
• Interfaces between the microprocessor and peripheral devices to offload data transfers.

Important Pins
Number of
Pin Group Functionality Description
Pins
A3–A0 (4 pins) 4 Low 4 bits of DMA register/port addresses
A7–A4 (4 pins) 4 High 4 bits of DMA register/port addresses
DB7–DB0 (8 pins) 8 8-bit bidirectional data bus for DMA data transfer
DREQ3–DREQ0 (4
4 DMA channel request inputs from peripherals
pins)
DACK3–DACK0 (4
4 DMA channel acknowledge outputs to peripherals
pins)
HRQ, HLDA (2 pins) 2 Hold request and hold acknowledge signals to CPU
MEMR, MEMW (2
2 Memory read and write control signals
pins)
IOR, IOW (2 pins) 2 I/O read and write control signals
READY, RESET (2
2 Ready input (wait control) and reset signal
pins)
ADSTB, AEN (2 pins) 2 Address strobe and address enable signals
CS, CLK (2 pins) 2 Chip select and clock input
End of process signal (indicates transfer
EOP (1 pin) 1
completion)
NC (1 pin) 1 No connection
Vcc, GND (2 pins) 2 Power supply and ground

Microprocessor Interface vs DMA Interface

• The 8237 interfaces with the microprocessor using address, data, and control lines.
• It manages DMA interface signals like DREQ/DACK, HRQ/HLDA to control bus
arbitration and data transfer.

Internal Registers and Address Offsets

 Channel Channel Channel
Register Name Write/Read Channel 0
1 2 3
Base Address Register (BAR) Write (W) 0 2 4 6
Base Word Count Register
Write (W) 1 3 5 7
(BWCR)
Current Address Register
Read (R) 0 2 4 6
(CAR)
Current Word Count Register
Read (R) 1 3 5 7
(CWCR)
8 (all
Command Register Write (W)
channels)
8 (all
Status Register Read (R)
channels)
9 (all
Request Register Write (W)
channels)
A (all
Mask Register (1-channel) Write (W)
channels)
B (all
Mode Register Write (W)
channels)
B (all
Temporary Register Read (R)
channels)
C (all
Clear Internal Flip Flop Write (W)
channels)
D (all
Master Clear Write (W)
channels)
E (all
Clear Mask Register Write (W)
channels)
F (all
Mask Register (4-channel) Write (W)
channels)

Notes on Registers:

• Base Address Register stores starting memory address for DMA.

• Base Word Count Register stores number of bytes to transfer minus one.
• Current Address Register and Current Word Count Register are updated during
transfer.
• Command Register controls the mode and enables of DMA.
• Status Register reflects the current status of DMA operations.
• Request Register manages individual channel requests.
• Mask Register enables/disables individual channels.
• Mode Register selects transfer type (e.g., read, write, verify) and addressing modes.
• Temporary Register is internal for temporary data storage.
 • Flip-flop and master clear registers manage internal state resets.

Programming 8237 DMA Controller Channel 1: Example

Explained
Given:

• Base I/O address of 8237: 80h

• Memory block assigned to channel 1: starting at 43C0h
• Number of bytes to transfer: 4050h (hex) bytes

1. Loading Base Address Register (BAR) for Channel 1

• BAR is at offset 2 from base address for channel 1.

• It needs two writes: LSB and MSB of the 16-bit address.

MOV AL, 0C0h ; LSB of base address = C0h (from 43C0h)

OUT 82h, AL ; 80h + 2 = 82h, load LSB into BAR channel 1, FF
toggles

MOV AL, 43h ; MSB of base address = 43h (from 43C0h)

OUT 82h, AL ; Load MSB into BAR channel 1, FF toggles back

2. Loading Base Word Count Register (BWCR) for Channel 1

• BWCR is at offset 3 from base address for channel 1.

• Number of bytes is 4050h, but DMA word count register holds (count – 1).
• So, count = 4050h, count - 1 = 404Fh.
• LSB = 4Fh, MSB = 40h.

MOV AL, 4Fh ; LSB of word count (4050h - 1)

OUT 83h, AL ; 80h + 3 = 83h, load LSB into BWCR channel 1

MOV AL, 40h ; MSB of word count

OUT 83h, AL ; Load MSB into BWCR channel 1

Important Notes:

• Internal flip-flop (FF) toggles after each byte write/read to select LSB/MSB.
• BAR and BWCR set initial starting address and number of bytes to transfer.
• During transfer, Current Address Register (CAR) and Current Word Count Register
(CWCR) are automatically updated by the DMA controller.
3. Reading Current Address and Current Word Count (for example, Channel 2)

• Channel 2 BAR offset = 4, BWCR offset = 5.

• To read CAR and CWCR, do:

; Read CAR for channel 2 (offset 4)

MOV AL, 0 ; Reset FF before reading (usually done by reset or
clear)
IN AL, 84h ; 80h + 4 = 84h, read LSB of CAR (FF toggles)
MOV DL, AL ; Store LSB

IN AL, 84h ; Read MSB of CAR (FF toggles)

MOV DH, AL ; Store MSB (DX = CAR)

; Read CWCR for channel 2 (offset 5)

MOV AL, 0 ; Reset FF before reading (optional)
IN AL, 85h ; 80h + 5 = 85h, read LSB of CWCR (FF toggles)
MOV CL, AL ; Store LSB

IN AL, 85h ; Read MSB of CWCR (FF toggles)

MOV CH, AL ; Store MSB (CX = CWCR)

Summary of Register Offsets (from base 80h):

Channel Channel Channel

Register Channel 0
1 2 3
Base Address Register (BAR) (W) 80h + 0 80h + 2 80h + 4 80h + 6
Base Word Count Register (BWCR)
80h + 1 80h + 3 80h + 5 80h + 7
(W)
Current Address Register (CAR) (R) 80h + 0 80h + 2 80h + 4 80h + 6
Current Word Count Register (CWCR)
80h + 1 80h + 3 80h + 5 80h + 7
(R)
80h + 8 (all
Command Register (W)
channels)
80h + 8 (all
Status Register (R)
channels)
80h + 9 (all
Request Register (W)
channels)
80h + A (all
Mask Register (1-channel) (W)
channels)
80h + B (all
Mode Register (W)
channels)
1. COMMAND REGISTER Programming

• Purpose: Configure controller-wide settings (enable/disable, transfer type, priority, etc.)

Bit(s) Description Example Values (Your examples)

7 Controller Enable (1 = enabled) 1
6 Memory-to-Memory Transfer (1 = enabled) 0 (disabled) or 1 (enabled)
5 Reserved 0
4 DREQ Polarity (1 = active high) 1
3 DACK Polarity (1 = active high) 0 or 1 (based on example)
2 Priority Mode (1 = rotating) 0 or 1
1 Timing Mode (0 = normal, 1 = cascade) 0
0 Reserved 0 or 1

Example 1: Controller enabled, memory-to-memory disabled, DREQ & DACK

active high, rotating priority, normal timing
MOV AL, 10010000b ; binary: 1 0 0 1 0 0 0 0 = 90h
OUT 88h, AL ; 80h + 8 = 88h (Command register)

Example 2: Memory to memory enabled

MOV AL, 00000001b ; binary: 00000001
OUT 88h, AL
2. MODE REGISTER Programming

• Purpose: Configure each DMA channel’s transfer mode.

Bit(s) Description
7-6 Transfer Type: 00=Verify, 01=Write, 10=Read, 11=Cascade
5 Auto Initialization (1=enable)
4 Address Increment/Decrement (1=increment)
3-2 Transfer Mode: 00=Demand, 01=Single, 10=Block
Bit(s) Description
1-0 Channel Number (0 to 3)

Example 1: Channel 3, input device, auto init enabled, address increment,

demand mode
MOV AL, 00010111b ; 0 0 0 1 0 1 1 1
OUT 8Bh, AL

Example 2: Channel 0, output device, auto init disabled, address decrement,

single mode
MOV AL, 01101000b ; 0 1 1 0 1 0 0 0
OUT 8Bh, AL

Example 3: Channel 2, input device, auto init disabled, address increment, block
mode
MOV AL, 10000110b ; 1 0 0 0 0 1 1 0
OUT 8Bh, AL

Example 4: Channel 1, cascade mode (DMA controller connected)

MOV AL, 11000001b ; 1 1 0 0 0 0 0 1 (bits 7-6 = 11 = cascade)
OUT 8Bh, AL

3. REQUEST REGISTER & MASK REGISTER

 • Request Register bits correspond to requesting DMA channel service.
• Mask Register bits correspond to enabling/disabling channels (1 = masked/disabled).

Initiate memory-to-memory transfer:

MOV AL, 00000100b ; Request for channel 2 (bit 2)
OUT 89h, AL ; Request register (80h + 9)
IN AL, 8Bh ; Read temporary register (80h + B)

Disable Channel #1 (mask register 1-channel):

MOV AL, 00000101b ; Mask channel 1 (bit 1), plus command bits
OUT 8Ah, AL ; Mask register 1-channel (80h + A)

Disable Channels #1 and #3 (mask register 4-channel):

MOV AL, 00001010b ; Mask channel 1 and 3
OUT 8Fh, AL ; Mask register 4-channel (80h + F)

4. STATUS REGISTER
 • Reading the status register gives current interrupt and terminal count status for all
channels.

IN AL, 88h ; Read status register (same port as command register)

Example status value: 01101000b

Means channels 1 & 2 have active interrupt requests, and channel 3 reached terminal count.

5. CLEAR COMMANDS

• Clear internal flip-flop: (used to reset internal address/data latch)

\
OUT 8Ch, AL ; Port 80h + C
 • Master clear: (resets controller to initial state)

]
OUT 8Dh, AL ; Port 80h + D

• Clear mask register: (unmasks all channels)

\
OUT 8Eh, AL ; Port 80h + E

EXTRA INFO:
What Are “Channels” in 8237 DMA?
The 8237 DMA (Direct Memory Access) controller can handle four independent data
transfer paths, called channels:

Channel Number Typical Use

Channel 0 Input/Output Device 1
Channel 1 Input/Output Device 2
Channel 2 Input/Output Device 3
Channel 3 Input/Output Device 4

Each channel transfers data between memory and a device (like a disk, sound card, or serial
port) without CPU involvement.

What Are Internal Registers?

Each channel has its own pair of internal registers:

Register Function
BAR (Base Address Register) Starting memory address for transfer
BWCR (Base Word Count Register) Number of bytes/words to transfer
CAR (Current Address Register) Keeps track of current address during transfer
CWCR (Current Word Count Register) Keeps track of bytes left during transfer

There are also some common (shared) registers for the whole controller:

• Command Register (to enable/disable controller)

• Status Register (shows which channel finished)
 • Request Register (software request for channel)
• Mode Register (defines how each channel works)
• Mask Register (enable/disable channel)
• Flip-Flop Clear, Master Clear (controller resets)

What Do the Numbers (0–Fh) Mean?

These are offset addresses added to the base address of the DMA controller. Suppose the base
address is 80h, then:

Offset Register Full I/O Address

0 CH0: BAR / CAR 80h
1 CH0: BWCR / CWCR 81h
2 CH1: BAR / CAR 82h
3 CH1: BWCR / CWCR 83h
4 CH2: BAR / CAR 84h
5 CH2: BWCR / CWCR 85h
6 CH3: BAR / CAR 86h
7 CH3: BWCR / CWCR 87h
8 Command Register / Status 88h
9 Request Register 89h
A Mask Register (1 channel) 8Ah
B Mode / Temporary Register 8Bh
C Clear Flip-Flop 8Ch
D Master Clear 8Dh
E Clear Mask Register 8Eh
F Mask Register (4 ch) 8Fh

So, for example:

• OUT 82h, AL = Write to Channel 1 Base Address Register

• OUT 88h, AL = Write to Command Register
• IN AL, 85h = Read Channel 2’s Current Word Count Register

How to Understand the Table You Posted

 Register Name W/R CH0 CH1 CH2 CH3
Base Address Register W 0 2 4 6
Base Word Count Register W 1 3 5 7
Current Address Register R 0 2 4 6
Current Word Count Reg R 1 3 5 7
Command Register W 8 (shared)
Status Register R 8 (shared)
Request Register W 9 (shared)
Mask Register (1-ch) W A (shared)
Mode Register W B (shared)
Temporary Register R B (shared)
Clear Flip-Flop W C (shared)
Master Clear W D (shared)
Clear Mask Register W E (shared)
Mask Register (4-ch) W F (shared)

Example
Suppose the base address is 80h. To program channel 2:

• Set Base Address:

MOV AL, <LSB of address>

OUT 84h, AL ; BAR LSB for CH2
MOV AL, <MSB of address>
OUT 84h, AL ; BAR MSB for CH2

• Set Word Count:

MOV AL, <LSB of count>

OUT 85h, AL ; BWCR LSB for CH2
MOV AL, <MSB of count>
OUT 85h, AL ; BWCR MSB for CH2

• Start the DMA transfer by writing to the mode register and unmasking channel 2.

Background:

The 8237 DMA Controller uses some internal flip-flops and registers to manage data
transfers between memory and I/O devices. These clear commands are control operations that
help reset or prepare the controller.
1. Clear Internal Flip-Flop
]
OUT 8Ch, AL ; (Base + C)

What it does:

This resets the internal flip-flop, which is used for loading 16-bit values (like addresses and
word counts) into the controller 8 bits at a time.

Why it's needed:

The 8237 handles 16-bit values using two 8-bit writes:

• First you write the LSB

• Then the MSB

It keeps track of whether it's expecting LSB or MSB using a flip-flop.

But if something goes wrong or you need to restart loading a value, use this command to reset
the flip-flop to its initial state (LSB mode).

Think of it like:

“Reset the controller’s memory so it expects the first part of a number again.”

2. Master Clear
\
OUT 8Dh, AL ; (Base + D)

What it does:

This command resets the entire DMA controller to its default (power-on) state.

Why it's needed:

If you want to fully reset the DMA controller, clear all registers and settings, and start over, use
this command.

It will:

• Reset command register

 • Clear all mode and mask settings
• Reset the internal flip-flop
• Disable all channels

Think of it like:

“Reboot the DMA controller completely.”

3. Clear Mask Register

OUT 8Eh, AL ; (Base + E)

What it does:

This unmasks (enables) all channels of the DMA controller.

Why it's needed:

Each DMA channel can be enabled or disabled (masked). This command will unmask
(enable) all 4 DMA channels at once.

Note: This only affects the masking, not the configuration or memory settings of the channels.

Think of it like:

“Allow all DMA channels to transfer data.”

Summary Table
I/O
Command What It Does When to Use
Port
Clear Internal Flip-
8Ch Reset LSB/MSB toggle Before reloading BAR/BWCR
Flop
Reset everything in DMA
Master Clear 8Dh On restart or error
controller
After setup, before starting
Clear Mask Register 8Eh Enable (unmask) all 4 channels
DMA