CST Studio Suite 2025

PCB and Package Simulation

Workflow &
Solver Overview

Version 2025.0 - 8/21/2024

 Copyright
© 1998 2024 Dassault Systemes Deutschland GmbH
CST Studio Suite is a Dassault Systèmes product.
All rights reserved.

Information in this document is subject to change without notice. The

software described in this document is furnished under a license
agreement or non-disclosure agreement. The software may be used
only in accordance with the terms of those agreements.

No part of this documentation may be reproduced, stored in a retrieval

system, or transmitted in any form or any means electronic or
mechanical, including photocopying and recording, for any purpose

of Dassault Systèmes.

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STUDIO, CST EMC STUDIO, CST MICROWAVE STUDIO, CST
PARTICLE STUDIO, CST Studio Suite, EM Studio, EMC Studio,
Microstripes, Microwave Studio, MPHYSICS, MWS, Particle Studio,
PCB Studio, PERFECT BOUNDARY APPROXIMATION (PBA),
Studio Suite, IdEM, Spark3D, Fest3D, Antenna Magus, Opera,
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3DS.com/SIMULIA

2
 Chapter 1 Introduction ......................................................................................................... 5
Welcome ............................................................................................................................. 5
How to Get Started Quickly ............................................................................................. 5
What is CST PCB Studio? ............................................................................................... 5
Applications ..................................................................................................................... 6
CST PCB Studio Key Features ........................................................................................... 6
General ............................................................................................................................ 6
PCB Structure Modeling .................................................................................................. 6
PCB Electric Modeling ..................................................................................................... 6
Circuit Simulator .............................................................................................................. 7
About This Manual .............................................................................................................. 7
Document Conventions ................................................................................................... 7
Your Feedback ................................................................................................................ 7
Chapter 2 Overview ............................................................................................................. 8
User Interface...................................................................................................................... 8
Importing a PCB .................................................................................................................. 9
Exploring the PCB ............................................................................................................. 12
View Attributes Window and Color Modes ........................................................................ 24
Stackup Manager........................................................................................................... 28
Net Editor....................................................................................................................... 31
Select Filter.................................................................................................................... 34
Editing and Checking the PCB .......................................................................................... 38
Drawing a new Trace and Area ..................................................................................... 38
Layout Checker.............................................................................................................. 41
Repair Function ............................................................................................................. 42
Chapter 3 Examples .......................................................................................................... 44
Design and Simulation of a Differential Strip Line using 2D (TL) Modeling....................... 44
Task Definition ............................................................................................................... 44
The PCB Design ............................................................................................................ 44
2D TL Modeling ............................................................................................................. 48
Signal Integrity on a Multilayer using the SI TD solver ...................................................... 51
Task Definition ............................................................................................................... 51
The PCB Design ............................................................................................................ 51
SI TD Solver .................................................................................................................. 57
Impedance Calculator ....................................................................................................... 67
PI Analysis using the PI Solver ......................................................................................... 71
Task Definition ............................................................................................................... 71
The PCB Structure......................................................................................................... 72

3
 PI Solver ........................................................................................................................ 75
Crosstalk on Split Power Planes using 3D (PEEC) Modeling ........................................... 79
Task Definition ............................................................................................................... 79
The PCB Design ............................................................................................................ 79
3D (PEEC) Meshing and Modeling................................................................................ 85
Low Frequency Extraction ............................................................................................. 95
Chapter 4 General Terminology....................................................................................... 100
3D (PEEC) Modeling ....................................................................................................... 100
2D (TL) Modeling............................................................................................................. 100
3D (FE/FD) Modeling ...................................................................................................... 101
Method Approximations................................................................................................... 101
Chapter 5 Finding Further Information ............................................................................. 103
Online Documentation..................................................................................................... 103
Tutorials and Examples................................................................................................... 103
Technical Support ........................................................................................................... 103
Macro Language Documentation .................................................................................... 103
History of Changes.......................................................................................................... 103

4
 Welcome to CST PCB Studio , the powerful and easy-to-use program for the analysis
of electromagnetic characteristics of complex PCBs.

CST PCB Studio is part of the CST Studio Suite, which is described in the CST Studio
Suite Getting Started manual. The following instructions assume that you have already
installed the software and familiarized yourself with the basic concepts of the user
interface.

We recommend that you proceed as follows:

Read the CST Studio Suite Getting Started manual.
Work through this document carefully. It should provide you with the information
necessary to understand the advanced documentation found in the online help.
Take look at the Component Library in the startup window. There are all kinds of
already prepared examples that will give you a good idea of the types of workflows
that can be addressed. These short examples are designed to give you a basic
insight into a particular application domain. You can filter by e.g., PCB & Packages
to reduce the number of listed examples.
After working through this booklet, you can start with your own examples. Choose
a reasonably simple example that will allow you to quickly become familiar with the
software.

CST PCB Studio is an electromagnetic simulation tool specially designed for the fast
and accurate simulation of real-world PCBs and can be used for pre-layout and post
layout analysis. It allows the simulation of effects like resonances, reflections or crosstalk
on any kind of PCBs from single-layer up to multilayered high-speed PCBs.

CST PCB Studio can be easily integrated into any existing design flow by importing PCB
designs directly from many popular EDA layout tools and provides a powerful tool for
the automated layout checking and correction of geometric errors.

CST PCB Studio has an intuitive user interface that makes it easy to define a design
from scratch for pre-layout analyses. There are advanced functions to navigate through
a design and to select, hide or visualize any objects like traces or areas.

CST PCB Studio incorporates three different solver techniques to account for all kinds
of PCBs. Single- or two layer PCBs are usually designed without any special ground
reference layers and are therefore dedicated to the lower- or medium frequency range.
The method best suited to this kind of application is the quasi-static Partial Element
Equivalent Circuit method (3D PEEC). The program generates equivalent circuits out of
any selected combination of conductors. Skin effect and dielectric loss are modeled in
both the frequency and the time domain.

CST PCB Studio uses CST Design Studio to define passive and active devices on the
modeled PCB layout with the help of an easy-to-use schematic editor. The powerful
built-in network simulator in CST Design Studio enables the simulation of the whole
system consisting of the equivalent circuit of the PCB and its termination in both
frequency and time domain. Broadband equivalent circuits can be exported in several
SPICE formats for a further usage in other commercial network simulators.

5
 CST PCB Studio offers a modeling technique dedicated to the analysis of power
distribution networks (PDN) in multi-layer PCBs. Given a set of PDN nets to be
characterized, the full-wave three-dimensional Finite Element Frequency Domain
solver, hereafter referred to as 3D (FE FD), is able to compute PDN impedances directly.
The results can be used to check whether the design margins imposed by the IC
component are met. Using the CST PCB Studio component library, this modeling option
enables the assessment of different decoupling capacitor strategies, taking into account
the full-wave electromagnetic effects in the PDN.

SI analysis on single/multilayer PCBs and packages

PI analysis on single/ multilayer PCBs and packages
IR Drop analysis on single/ multilayer PCBs and packages
DDR4 analysis on PCBs that use DDR4 technology
Line impedance analysis for single ended and differential nets
Layer impedance calculator for pre-layout analysis

An overview of the main features of CST PCB Studio can be seen in the following list.
Please note that not all options may be available to you due to license restrictions.
Please contact your local sales office for details.

For the circuit simulator only some selected key features are listed below. A full list can
be found in the CST Design Studio Workflow manual.

Graphical user interface based on Windows and Linux operating systems.

Tight interface to CST Design Studio.
PEEC method specializing in the simulation of single- and two-layer boards.
Transmission line modeling method for SI analysis of high-speed multi-layer
PCBs and packages.
Specialized FEM method for PI analysis of high-speed multi-layer PCBs and
packages.
IR Drop analysis to simulate DC power/ground behavior of a PCB and package.
SI TD and SI FD analysis to simulate signal behavior in time and frequency
domain.
DDR4 wizard to quickly set up memory analysis.
PCB line impedance plot of individual nets.

Import of PCB designs from Cadence Allegro/APD/SiP.

Import of PCB designs from Zuken CR-5000/8000 ASCII.
Import of PCB designs from Mentor Graphics Hyperlynx.
Import of PCB designs from ODB++.
Import of PCB designs from IPC-2581.
PCB layout checker with automatic correction.
Interactive PCB editing tools.
Advanced navigation through the PCB.
Hiding/visualizing selections.

Automatic meshing and extraction of 3D PEEC models.

Automatic meshing and extraction of 2D transmission line models.
Automatic meshing and extraction of 3D (FE FD) models and PDN impedances.
Consideration of skin effect and dielectric loss in time and frequency domain.

6
 Export of equivalent SPICE circuits.
Export of current distribution and near fields for radiation analysis.
Advanced export of PCB sub structures to CST MICROWAVE STUDIO.

Schematic editor enables the easy definition of passive and active devices.
Fast circuit simulation in time and frequency domain.
Support of IBIS models and eye-diagram analysis.
Import and Export of S-Parameter data via TOUCHSTONE file format.
Parameterization of termination circuitry and parameter sweep.

This manual is primarily designed to enable a quick start to the modeling capabilities of
CST PCB Studio. It is not intended as a reference guide of all available features, but
rather as an overview of the key concepts. Understanding these concepts will allow you
to learn working with the software efficiently with additional help from the online
documentation.

To learn more about the circuit simulator please refer to the CST Design Studio Workflow
manual.

The next chapter Overview is dedicated to explaining the underlying concepts of CST
PCB Studio and to showing the most important objects and related dialog boxes. The
chapter Examples will guide you through the three important analysis types. We strongly
recommend studying both chapters carefully.

Buttons that should be pressed within dialog boxes are always written in italics,
e.g., OK.

Key combinations are always indicated by a plus (+) sign. Ctrl+S means that you
should hold down the Ctrl key while pressing the S key.

top of the main window. The commands are organized in a series of tabs within
the Ribbon. In this document a command is printed as follows: Tab name: Group
name Button name Command name. This means that you should activate
the proper tab first and then press the button Command name, which belongs to
the group Group name. If a keyboard shortcut exists, it is shown in brackets after
the command.

Example: View: Change View Reset View (Space)

The project data is accessible through the navigation tree on the left side of the

following way: NT: Tree folder Sub folder Tree item.

Example: NT: Components IC100 IC100-A1

We are constantly striving to improve the quality of our software documentation. If you
have any comments regarding the documentation, please send them to your support
center: 3DS.com/Support.

7
 CST PCB Studio is designed to be easy to use. However, to get started quickly you will
need to know your way around the interface and have knowledge of the basic features
and concepts. The main purpose of this chapter is to provide an overview of the general
interface.

Launch CST Studio Suite from the Start menu or by clicking on the desktop icon. In the
Modules and Tools list, click on PCBs & Packages.
A new CST PCB Studio project opens with an empty Main View.

Ribbon

Main
View

View
Navigation Attributes
Tree

Message Progress
Window Window

The user interface consists of several areas:

1. The Main View shows the 2D/3D visualization of the PCB design.
2. The Ribbon offers quick access to the most important dialog boxes and options.
3. The View Attributes window allows the setting of specific visualization and selection
properties for many objects.
4. The Navigation Tree allows access to all objects of the project. It is organized into folders
and subfolders with specific contents. When selecting an item it will be highlighted in the
Main View. It also includes a powerful tool for a more convenient selection of different
objects. It makes it possible to track logical net list relations in a physical geometry due to
its hierarchical tree structure and due to the connection with the Main View.
5. The Message window shows general information, solver progress, warnings and errors
during project set-up or simulation.
6. The Progress Window lists all open projects and any solver progress. The user has the
ability to abort running calculations here.

8
 In order to import an existing PCB layout from the Component Library in the main window
of CST Studio Suite,
corresponding item.

Press the button with the three dots and select View to explore more details.

A new dialog box will appear where the the Attachments frame can
be selected.

9
 In a last step, we press the Download button in the upper right corner:

This will download the file into a temporary folder and makes it available in the
Attachments frame:

To import the file, we click on the folder next to the workflow.dar icon.
A file browser will open where we can either drag & drop the file directly into the CST
PCB Studio main window or we store the file in a separate folder, go back the CST PCB
Studio and import the file by choosing Home Exchange Import/Export EDA Import.

The following dialog box will appear:

Before pressing the Import button, we can switch off the Show simulation wizard in the
left bottom part of the dialog box for this example.
We recommend though to always perform the steps in the Simulation Wizard for regular
boards to fix issues with the imported data.

10
 The import will only take a few seconds and the PCB design like the one below will
appear in the Main View. The layer visibility may be different due to individual settings
or use of a remote desktop.

We have now imported our first PCB design. Save the project as e.g., .

11
 This section will explain the most important tools for exploring a PCB. The Main View
window includes a powerful 2D layout viewer that allows a fast investigation even for
complex PCBs. The three main modes to manipulate the view on the layout are
Selection, Zoom and Pan. They control the behavior of the mouse for the viewer and
can be switched using View: Mouse Control as shown in the image below:

An important characteristic of the board is its overall size.

When importing an existing board, the corresponding units will be set automatically and
can be found in Home: Units View Units:

The view unit can be changed by selecting any unit available in the drop-down menu.
Changing the view unit will not change the physical size of any structure on the PCB.
Note: switching the unit in this way is possible with many other dialog boxes in CST PCB
Studio. Just the PCB length values are displayed in the new unit.

We will change the view unit to mil as shown in the image below and continue our
exploration.

The best way to get an overview of the available objects and functions is using the
Navigation Tree. After expanding the folders Technology, we see the following items:

12
 We start by inspecting the objects in the Technology section.
When selecting the object Board, the PCB representation in the Main View will change.
Board defines the outline of the PCB and this outline can be edited using Edit Outline
with the right mouse button or double clicking with the left mouse.
The following dialog box will appear where we see the polygon defining the outline of
the PCB:

We can change its shape either by changing the coordinates in the table or by dragging
the point interactively using the mouse in the Main View. New points can be added or
imported as well. We will close the dialog box without changing anything.

Three predefined material types are available by default when we expand the Materials
tree item:

After double clicking Materials, picking Edit Layout > Materials in the ribbon or choosing
Edit by using the right mouse button the following dialog box will appear:

We are able to edit the existing materials or to create new materials by pressing the
indicated buttons. Importing a layout can also create new materials.
We close the dialog box without applying any changes.

13
 After expanding the Layers tree item, a list appears defining the layer stack-up:

We see four metallic layers (LR1, LR2, LR3 and LR4) and the corresponding dielectric
layers between them. We will see the editing of such a layer stack-up later in the sub-
chapter Stackup Manager.

Expanding the Pad Stacks tree item shows a list of objects, which represent the different
pad stacks available in this layout. If you select e.g., VIA_01 and expand the object, you
will see a list of four items defining a stack of connected pads in all four metallic layers:

Choosing Edit by using the right mouse button or a double click on this pad stack will
open up the following dialog box:

The list of pads corresponds with the items in the expanded Navigation Tree. Each pad
can be edited by selecting the corresponding item and pressing Edit.
A conductive tube that represents the drill connects the pads in the different layers.

14
 A Drill shape and its sleeve thickness define the outer diameter of that tube. The Pad
Stacks are not designed for a direct manipulation. They serve as auxiliary objects and
are referenced by the objects Vias as well as by Footprint Pins.

Expanding the Footprints tree item, a list of available footprints will appear as shown in
the image below:

These footprint items can be edited as well as created from scratch. They are usually
generated automatically during the EDA-import of an existing PCB design as part of the
component definition. The user can also manually create footprints.
They define the geometrical layout of a component including its pins and are placed
either on the top or the bottom layer of a PCB through the placement of the component
that uses the footprint.

In a next step we open the Nets navigation tree node.

A Net is a group of conductive shapes that are electrically connected. If you scroll down
the Navigation Tree and select the MAGNFIN item, the corresponding net is highlighted
in the Main View:

15
 We select the Net Classes object and expand it. A list with the four different net classes
can be seen:

Net class differential and net class single-ended are both nets meant to transport
signals. Net class differential is a special class type necessary to identify a pair of
differential nets that are usually symmetrically aligned along their path through the PCB
and in that way establish a complete transmission line.
A net of type single-ended needs another net serving as path for the return current. In
most cases a net from the ground net class is used to complete the transmission line.
The power net class is used to identify all nets that do not transport signals but supply
power for connected active devices.
Nets of the ground net class typically serve as return current path for all other nets.

The import process tries to assign the different nets to their corresponding net classes
e.g., the net GND becomes part of the net class ground).
In case the import format does not provide this functionality, please use the Auto-
Tagging functionality available in Home: Layout -> Net Editor -> Edit Nets -> Auto-
Tagging or perform the steps in the Import Wizard during import.
We strongly recommend performing this step to prepare the layout for later simulations.

The column Signal Specifications provides additional information on signal nets, which
can be also used in workflows like CST BOARDCHECK or the PI analysis.
CST PCB Studio contains many predefined signal specifications, but it is also possible
to define own specifications when needed. Signal type nets can be auto-tagged to
contain this additional information.

The column DDR4 Signal Type is quite similar to Signal Specifications. The DDR4 signal
type is used in the DDR4 Analysis simulation workflow to set up specific analyses for
nets that have this DDR4 signal type assigned.

16
 As for Signal Specifications, the DDR4 Signal Type cannot be assigned to power or
ground nets.

Next, we expand the Components object. While selecting different items in the list we
see the corresponding components highlighted in the Main View.
Scrolling down the Navigation Tree and selecting MN1 will highlight the rectangle with a
colored frame as shown in the image below:

Closely related to the component items are Virtual Components. They allow the creation
of components that consist of arbitrary component pins, vias or terminals on the board.

Another tree item is called Terminals. A terminal is a geometric test point that the user
can place on conductors. In the modeling phase, terminals are used as dedicated spots
to measure voltages or drawing currents at this specific location. The creation and use
of terminals will be explained in more detail in the chapter Examples.

The next three folders called Traces, Areas and Vias all contain geometric objects
related to a net.

We expand the Select frame at the bottom of the Navigation Tree and select Traces
instead of Entire nets. This allows the selection of one single trace instead of all traces
that belong to a certain net:

You will recognize the change of the Main View. The outlines of the traces are now
visible.

17
 In order to remove all previous selections, we press Home: Select Unselect All:

Next, we expand the Traces folder, scroll down the Navigation Tree and select trace_41.
The corresponding trace gets highlighted in the Main View.
Choosing Edit by clicking the right mouse button or double clicking the following dialog
box will appear showing the definition of the trace:

The trace is part of the MAGNFIN net and its width is 10 mil. The path of the trace is
defined by the list of x/y-points on layer LR1. The x/y coordinates can be edited.
In addition, the buttons on the right-hand side allow the user to edit the list of points and
even to import/export points from/to a text file.

Next, we remove the selection by pressing Unselect All again, change to the Select
frame and check Areas as shown in the image below:

18
 Next, we set layer LR2 visible in the View Attributes Window. Then we expand the
folder Areas and select the first item Area. The corresponding area is highlighted in the
Main View as can be seen in the image below:

We right mouse click and choose Edit (or double click). The following dialog box will
appear showing the definition of this area:

The area is part of the GND net and is located on Layer LR2. An area consists of exactly
one outline shape and it optionally also contains an additional number of cutout shapes.

All sub-shapes are listed in the frame Available shapes on the left of the dialog box. If
you select an item in this list, the highlighted lines of all shapes change in the Main View
and the definition of the selected shape will appear in the table on the right side of the
dialog box. A selected point can also be moved in the main view using the mouse.

19
 Apart from the general Arc Polygon (which supports a special description for round
corners), Polygon, Rectangle and Circle shape type are also available after import or
can be used for a quick manual creation of an area.

In order to investigate the area object more deeply, we look into Cutouts to see the list
of all cutouts:

After selecting the item Cutout 145, we see a crosshair in the Main View showing the
location of the cutout:

We activate the axis by selecting Home: Visibility Axis.

For closer inspection, we zoom into the location of the cutout.

20
 To perform zooming select View: Mouse Control Zoom. The mouse cursor changes
to a magnifying glass and allows zooming into the location of the selected cutout.
Alternatively, a mouse wheel can be used to zoom in and out of the point at the current
cursor location.

The magnified location looks like in the image below:

Now we switch back into the selection mode in order to return to the default behavior of
the mouse cursor (by selecting View: Mouse Control Selection).

After that we change back to the dialog box, we select the first point in the arc polygon
definition, and start clicking through all other points by using either the left mouse button
or the up and down arrows on your keyboard. We will see the synchronized movement
of the crosshair in the Main View.

Every shape can be edited by changing the values in the table or dragging the selected
x-y node in the main view once its editor dialog box is open.

We will now close the dialog box without changing any values and reset the Main View
by selecting View: Change View Reset View.
There will be a more-in-depth explanation on the editing possibilities in chapter Editing
and Checking the PCB.

21
 As the last object of the Navigation Tree, we select and expand the object Vias:

We unselect all selected objects by using Home: Select Unselect All and check Vias
in the Select frame as shown in the image below:

Now we move down the list of vias, select via_7 and see it highlighted by a cross hair in
the Main View:

22
 We choose Edit by clicking the right mouse button (or double click) and see the following
dialog box:

This via is part of the VCC net and refers to (and thereby uses) the pad stack VIA_02.
The position on the board is defined in two fields x and y.

On layouts that support the feature, an additional Die Stacks tree item is visible. In case
die elements were imported, this navigation tree item provides information about the
inner layers, traces, areas and nets in such a Die.
Those elements behave in the same way as their counterparts in the main PCB layout
and can be edited in the same way.

We now have completed the overview of all major objects of CST PCB Studio and in the
next step we are going to explain the most important supporting tools.

23
 A central tool for manipulating the view on the PCB is the View Attributes window as
shown in the image below:

The panel consists of four different tabs where important view characteristics of the
objects Layers, Nets, Net Classes, and Components can be edited. The default tab is
Layers.
All tabs are organized in the same way: The columns define the view characteristics
Color, Visible and Selectable. The rows contain the corresponding items of the objects
Layers, Nets, Net Classes, and Components.

Let us first observe the behavior by selecting the Top Components item in the first
column on the left side. After doing this, only the top side of the board with its
components is displayed. When you select the item below with the mouse, you will notice
that only the currently selected layer with its corresponding structures will be displayed.
In the image below, you see the layer LR1:

24
 We restore the visibility of all layers by selecting All Layers:

In a next step, we investigate the different view characteristics. For this, we double-click
on the red cell in column Color of layer Top Components. A dialog box appears in which
we can choose another color for elements of this layer.

We select for example a light blue-grey color, press Ok and see the new color for all
components in the Main View.

25
 If we uncheck the cell in column Visible, we will notice that all components are hidden in
the Main View as shown in the image below:

In order to demonstrate the purpose of the column Selectable, we first check Visible
again and then select layer LR1 as shown in the image below:

26
 In a next step, we select Entire nets in the Select frame as shown below:

In the Main View, we now double-click at net UNLOAD_SWITCH as shown in the image
below:

We uncheck the cells in column Selectable as shown in the image below and try to select
another net.

With the selectable box inactive, it will not be possible to select this net by mouse click
on the main view. This function is very useful, e.g., when selecting an object in a layer
which is obscured by objects in other layers. In this case, the other layers can be set to
not selectable which allows us to select the object in a convenient way. You should try
the behavior of the settings for tab Nets, tab Net Classes, and tab Components by
yourself.

The function Color Mode corresponds to the functions provided in the View Attributes
window. With Color Mode, we can assign different colors to objects in order to distinguish
between different layers, between different nets or between different net classes.

27
 The default color mode is Layers and this means all objects on a layer have a certain
color.
In order to switch into the color mode Nets (or Net Classes), we select View: Color
Color Mode Nets as shown in the image below:

You are also encouraged to try out the behavior of the settings for color mode Nets and
color mode Net Classes.

The definition of the layer stack-up is very important to the overall electromagnetic
behavior of the PCB. Importing a layout design via an EDA-import does not always
automatically ensure that the layer stack-up is defined correctly.
Many designs do not contain correct values (or no values at all) for this important
parameterization and the user has to make sure the layer stack-up is defined correctly.

The layer stack-up is accessible in the Stackup Manager dialog. We can open the
dialog box by selecting Home: Layout Stackup. The following dialog box will appear:

We see the number of layers and the thickness of the board. There are four metallic
layers LR1, LR2, LR3 and LR4 in the table. Dielectric layers separate these metallic
layers and there are usually two additional dielectric layers on the bottom and the top of
the board.

The columns in the table provide access to all the relevant settings. Most values can be
edited. Material properties reflect the global values and cannot be changed here.

There is also an option to define a default material that is used for all via connections.

28
 To create a new layer, we press the Create New Layer button. The following dialog box
will appear:

To choose, whether the layer is metallic or dielectric, we select the Type drop-down box
in the dialog box marked above. A list show us the choices like in the image below:

Signal and Reference Plane are both metallic types. In addition to the Dielectric type,
there are two additional types, namely Enclosure and Mirror Plane. Both are metallic
layer types but are not part of the board itself but instead they provide the possibility to
define the environment surrounding the board.
We do not want to create a new layer right now so we press Cancel and look further into
the Layers Stackup dialog box.

The buttons in the Material column allow the selection of a material type from the
material library. The selection depends on the layer type: for metallic layers, only metallic
materials can be selected and for dielectric layers only dielectric materials can be
selected.

In the Fill box, we are able to define the position of the conductive structures in the
metallic layer relative to the boundary line of the dielectric underneath. The meaning of
the two parameters Above and Below is best explained by looking at the conductive
layer (between two dielectrics) as shown in the figure below:

29
 Etch type and etch factor determine the way production technology affects the shape of
the structure.

Etch Factor: Y divided by X. The default value is 2.0 but it can be adapted to the current
technology.

Etch Type: This field determines how the conductive traces shapes are interpreted.
Possible values are:
None: Traces are regarded as rectangular.
Consistent with Fill: uses a trapezoid shape where the broad base is set on the
edge between two dielectrics (for all typical layouts).
Contrary to Fill: uses a trapezoid shape where the small top is set on the edge
between two dielectrics below the substrate (only for some rare layouts).

The Stackup Manager allows saving or loading of a previously saved layer definition.
This can be done by pressing the Create LDF File button or the Read LDF File button
as shown in the image below:

LDF is an abbreviation for Layer Definition File. This storage function is useful when
different designs based on the same layer stack-up technology are imported regularly.
It can also be useful when optimizing the electromagnetic behavior of a certain design
by trying different layer stack-up technologies.

30
 Pressing the View
The effect of changes for e.g., Thickness, Fill and Etch parameters are visualized
interactively.

Related to the layer stackup is the Impedance Calculator which can be found in Home:
Simulation Impedance Calculator.
We close the dialog box and examine the Net Editor.

In order to assign the different nets to the corresponding net classes we open the Net
Editor with Home: Layout Net Editor:

The dialog box consists of several columns, but only the first and second are of interest
now. The first column lists the nets by name and the second the corresponding net class
for each net. We scroll down and see that net GND is set to net class ground and the
net VCC has the net class power.

Some layouts do not contain the required net class information and all nets can be of
type single-ended. This can be fixed by using the auto-tagging for the layout. To see
and apply the default expressions we press the Auto-Tagging button on the top menu
bar of the dialog box.

31
 A new dialog box appears containing the tabs Net Classes and Signal Specifications.

In the Net Classes tab, the values in the column Net Name can be edited and adapted
to individual naming schemes, if necessary.
The Signal Specifications are used in e.g., CST BOARDCHECK to determine specific
signal properties by name of a net. *USB1* e.g., tags a net with the specification for USB
1.1.

We close the Auto-Tagging dialog box again and try to assign a net class manually.

To give e.g., net Supply the net class power, we double-click on the corresponding value
in the Net Class column and select power as shown in the image below.

To see the effect of the net class assignments we now select View: Color Color Mode
Net Classes. Then we move to the View Attributes window and select the Net Classes
tab.

In case the View Attributes window is not visible, please activate it using View: Window
Windows View Attributes.

32
 Now we select the row single-ended. All single-ended nets are now highlighted as shown
in the image below:

In order to switch off the black background color, we toggle the button View: Color
Invert View

Now the Main View should look like in the image below:

33
 The Select filter supports many actions related to the selection of objects on the PCB
and we have already seen in the last chapter how to control the selection mechanism
by checking different buttons in the Select frame (see also image below):

We can either select the entire nets, even if we just select one single trace of the net (if
it is checked as in the image above), or you can select a single trace e.g., by checking
Traces instead of Entire nets.

If we check the button & Nets connected not only an entire net will be selected but also
other nets that are separated from the original selected net by components like resistors
or resistor arrays. We will see this powerful function in the example Signal Integrity on a
Multilayer using the SI TD solver in chapter 3.

In general, there are two possibilities to select an object. It can either be done by
selecting the object in the Navigation Tree or by simply clicking on it in the Main View.
Navigating and selecting on the PCB can be a difficult task because of the large number
of layers, conductors and components.

To show some more select functions we first switch the Color Mode back to layer (View:
Color Color Mode Layers) and activate the black background color again (View:
Color Black Background).

Then we go into the View Attributes window, change to the Layers tab, select layer LR1
and make sure that Visible and Selectable are selected for All Net Classes as shown in
the image below:

34
 The Main View should look like in the image below:

We zoom into the marked region of the image above and see something similar to the
image below:

35
 Before we select a net, we first make sure that Entire nets is marked in the Select
frame. We check the button Only selected items at the top of the Navigation Tree:

All items in the Navigation Tree are now hidden and we will see the top folder structure
only. We now select a net in the Main View as shown in the image below:

The net is now the only one listed in the Navigation Tree as shown in the image below:

36
 We can now expand the item and can navigate to the available connected objects:

This feature is useful when navigating and searching for specific elements on the PCB.

In order to fit the PCB view to the original size again, we can either use View: Change
View Reset View, or click with the right mouse button in the Main View and select
Reset view to structure from the drop-down menu, or simply press the spacebar on the
keyboard with the main view active.

37
 This section describes how to create and edit traces and areas and how to check and
repair overlaps.
First, we close the existing project and create a new, empty project. We will create a
simple PCB from scratch in the just a few steps.

We first select View: Visibility Axes to get a better overview in the Main View:

We press Edit: New Object Rectangular Area. A message will show in the main view
asking the user either to define the area directly by double-clicks with the mouse or by
using the corresponding dialog box.

We press ESC in order to open the dialog box. In the dialog box, we assign the default
net GND to new area, choose Rectangle as Shape Type and enter the coordinates and
size as shown in the image below:

38
 After pressing the Ok button, the new area should look like in the image below:

Now we create a new trace by pressing Edit: New Object Trace. Again, we press ESC
to open the corresponding dialog box where we enter the values as shown in the image
below. It is important to leave the trace at the default net Signal.

39
 After pressing Ok, we have two clearly overlapping nets as shown in the image below:

Before we go to the next section, we will take notice of the Object Spy in the right bottom
corner. The Object Spy can be turned off and on via View: Visibility Object Spy or
using the right mouse button context menu.

When we move the mouse cursor over items in the Main View, the Object Spy shows
the corresponding available structure details under the current mouse position.

40
 The two overlapping nets we just created represent a very simple layout. Nevertheless,
this simple layout is an example of an issue that often occurs when importing a complex
PCB layout. The input data of a complex layout may be slightly incorrect or inaccurate.
In order to generate a valid mesh for the modeling phase later on it is necessary to find
and repair these overlapping locations first.

To find potential geometrical problems we press Edit: Check Layout Layout Check. A
dialog box will open in which we press the Start button. This starts the analysis of the
geometry of the whole PCB in order to find overlapping or open-ended nets. When using
this feature for a complex PCB you will see progress information in the Messages
Window. In this simple case, the report dialog box appears quickly and looks like in the
image below:

All overlapping nets are listed on the left of the dialog box.
In our case both nets GND and Signal were found, because GND overlaps Signal and
Signal overlaps GND. Upon expanding of the nets, we can find all other nets that overlap
with the root element. On the right side of the dialog box all positions with an overlap as
well as the affected objects will be listed. In our case, there is only one location,
indicating the expected overlap between trace and area along with a position.

We select Signal on the left side of the dialog box and the line TOP with the left mouse
button and see the crosshair appear in the Main View which has also zoomed in on the
location of the overlap (in the image below it is already zoomed out again):

41
 It is important to find critical regions with overlapping nets and to repair such
configurations. In order to repair this kind of overlap in a complex layout there is a built-
in repair function available. Let us zoom into the existing layout to have a closer look at
the overlap:

To fix it, we select the area in the Navigation Tree and choose Edit by using the right
mouse button or double click on it. In the area dialog box, we press the Repair button:

A dialog box will prompt us to enter a Spacing value. The spacing distance defines the
minimal distance (free space) inserted between two conductive but not connected
objects by the repair procedure.
The value is in the global unit that is selected in View: Units View Units.

We leave the default value and press OK. The repair algorithm now tries to cut free the
overlapping conductors using the given spacing. A message will appear reporting the
successful separation.

42
 Now we have a layout without overlapping conductors:

Other overlaps of the type touching objects, e.g., traces, pads or areas.
In these cases, the offending objects can be shifted apart, size be slightly decreased or
the outline modified to fix the overlap.

We close the project (saving is not necessary) and try out some examples.

43
 Chapter 1 and 2 are an introduction to the handling and interface of CST PCB Studio.
This chapter will present five simple examples offering an insight into the numerical
techniques (solvers) available in CST PCB Studio.
The first example uses the 2D (TL) solver directly.
The second example demonstrates the use of the SI TD solver, which is based on the
2D (TL) solver technology but provides additional features for setting up a complete
simulation in a very convenient way.
The third example explains how to use the impedance calculator.
The fourth example shows the usage of the PI solver.
The last example demonstrates the handling of the 3D (PEEC) solver.

Sometimes it can be necessary to build up a small example from scratch in order to

analyze the behavior of a certain structure on a PCB in a so-called pre-layout-analysis .
In this example, we generate a pair of embedded strip lines and analyze the differential
transmission characteristic of the pair.

We create a new and empty PCBS-

is also available in the Component Library.

In a first step, we go to the Navigation Tree and change the default values for the
material fr4 as shown in the image below:

Next, we open the stackup editor by pressing Home: Layout Stackup. In a first step,
we add an additional insulator (Dielectric) and signal layer (Signal). Then we set the
materials accordingly (see the image below) and change the layer type of the TOP and
BOT layer to Reference Plane .

We check Filled Up for both reference planes, since this will automatically fill the whole
layer with metal. All three metallic layers should have a thickness of 0.02mm, the two
dielectric layers should get a thickness of 0.25mm. Make sure to arrange the layers in
the order below. It may be necessary to update the main view by pressing F5.

44
 After these steps, the stackup should look like in the image below:

In a next step, we go into the Technology Board node of the Navigation Tree and
make sure the width of the board outline is as shown in the image below:

Now we open the net editor by pressing Edit: New Object Net and generate two signal
nets as shown in the images below:

The next step in the set-up is to press Home: Layout Net Editor

45
 Here we define the two nets sig-p and sig-n as corresponding differential signal lines
by changing the net class of one to differential and pick the other as differential partner
net:

We can now start to place two parallel traces. We begin with the upper trace using Edit:
New Object Trace, which will be part of net sig-p as shown in the image below:

The definition of the second trace should look like this:

Now we have to place a terminal at each end of both traces.

To do this, we open the Edit Terminal dialog box by pressing Edit: New Object
Terminal. We add four terminals with the values shown below:

T1: Layer Signal, Net sig-p, x=0mm, y=100.45mm

T2: Layer Signal, Net sig-p, x=600mm, y=100.45mm
T3: Layer Signal, Net sig-n, x=0mm, y=100mm
T4: Layer Signal, Net sig-n, x=600mm, y=100mm

46
 Once we zoom into the layout, it should look like in the image below:

47
 With this done we can generate the equivalent circuit of the differential stripline pair. To
do that, we select the two nets sig-p and sig-n the Navigation Tree.
We open the 2D (TL)-dialog box by pressing Home: Parasitic Extraction 2D (TL).

In the Selection tab we can add the two nets to the list of selected nets as shown in the
image below by either pressing Add or dragging the selected items from the navigation
tree end up with this setup:

We switch to the Modeling tab and set the parameter Model valid up to frequency to
10GHz as shown in the image below. All other values should be left unchanged.

We press the Update Schematic button and switch to the Schematic tab where we see
the generated schematic block of our stripline pair.
If the pins are not located like shown in the image below, correct their position by
selecting the block, clicking the right mouse button and selecting Change Pin Layout.
The pins can be dragged left and right to fit. Close the pin layout editor by pressing Esc.

48
 Next, we load the schematic block according to the schematic in the image below:

We use 100 and 1000 The probes P1 and P2 are

differential ports and measure the voltage between T1-T3 and T2-T4.

We now create a Transient task:

In the corresponding Task Parameter List, we select the Excitations tab and choose
Define Excitation for Port 1 as shown in the image below:

49
 In the new dialog box, we insert the settings of our excitation:

Next, we change to the Transient tab and change the maximum simulation time Tmax
to 20 ns:

In a last step we press Update to start the simulation. The image below shows the TD
results of the simulation. You can select the relevant results out of the list of results.

The delay time of about 4 ns through the differential pair is clearly visible and a slight
increase of the voltage at one port due to some reflection of the signal can be observed.

50
 The purpose of this example is to acquaint you with the
Usage of the SI TD solver.
Time domain analysis with focus on signal integrity.

In many high-speed PCB designs it is important to check the integrity of the signal paths.
This means the whole system consisting of selected high-speed transmission lines,
signal sources and loads has to be analyzed with respect to delay, over- and undershoot
and crosstalk. For this kind of analysis, the power delivery systems are typically
considered as ideal and the simulation is performed in the time domain. In this example
we perform such an analysis on the basis of a single transmission line on a PCB.

First, we start a new project by importing an existing PCB design. The matching example
can be found in
high
and . We download both.

We start by high spee by clicking on the folder icon next to high

speed.dar. A file browser will open from where we drag & drop the file directly into the
empty CST PCB Studio main window. We keep
Import.
After the import, the PCB will look similar to the image below:

We save the project as e.g.,

51
 Now we start to examine the design.
We see an integrated circuit on the left side that connects to two other integrated circuits
on the right side via some address lines.

We press Home: Layout Stackup and see the different layers of the PCB. The board
consists of seven metallic layers and has an overall thickness of about 1.12 mm.
The material of the dielectric layers is fr4 with a relative permittivity of 4.2.

Note the particular sequence of Above and Below values in the Fill column and refer to
the CST PCB Studio online help for more details on the meaning of these parameters.

By pressing the View button, the effect of changing those Fill values can be viewed in a
separate dialog box. We unselect Fixed size to get a real impression of the technology.

52
 Next, we take a closer look at the components of the board.

We go to the View Attributes window and select the first two layers Top Components
and L1 by selecting the first column of the layer table (Top Components) and then with
mouse button still pressed go down to the next line (L1). Mouse click with shift/control
key pressed is another option.

We see the three integrated circuits.

Next, we select the last two layers L7 and Bottom Components. We see another two
ICs on the bottom side. To improve the visibility of the nets, we can switch the black
background color to white by pressing View: Color Invert View:

The address bus connects each signal from a pin of the IC on the left side to the
corresponding pins of the four ICs on the right side.

We are interested in what kind of and how many pins are connected to the net ADDR1.
In order to select the net, we expand the Select frame below the Navigation Tree and

) as shown in the image below:

Checking the box ensures that all nets connected to a selected net
(e.g., by a resistor) will be automatically selected as well.

53
 Checking the box means that all components connected to
any selected net (including the automatically selected nets) will be selected as well. This
is a powerful functionality, as we will see in the next steps.

We go into the Navigation Tree, expand the Nets folder and see ADDR1 as shown in
the image below:

We select ADDR1 and in addition, we turn on View: Visibility Hide Unselected Nets
to hide all other unselected nets. This allows to quickly locate a net in a large design.

Next, we switch the black background color on again, unselect View: Visibility Hide
Unselected Nets again, and go into the View Attributes window. Here, we select All
Layers in order to make all layers visible as shown in the image below:

Now we go into the Main View and if necessary, adjust the view. We should now have
a view similar to the one shown in the image below:

54
 We see the selected net highlighted with an additional net on the left side, both
separated by a resistor array. We go back into the Navigation Tree and check Only
selected items.

The two selected nets and the six components will be listed:

Next, we go back to the View Attributes window and select the two top layers Top
Components and L1 only. We zoom into the region of the resistor array and should have
a view like this:

We take a closer look at the signal path of the selected nets. In order to do this, it is
convenient to expand the selected nets in the Navigation Tree as shown in the image
below:

Now we can easily follow the signal path starting from pin IC1-A1 of the left IC to pin
Rarr-1 of the resistor array.
The resistor array consists of 10 Ohm resistors and connects the signal to pin Rarr-8.
From this pin, the net ADDR1 starts and connects the pins to the four other ICs.

55
 To show the location of these pins we first zoom out again (by pressing View: Change
View Reset View). Then we zoom in on the ICs on the right side and switch on the
pin names (by pressing button View: Visibility Pin Names also available in the context
menu of the Layout View). The image below shows the pins of IC3t.

We change back to the View Attributes window and select the two bottom layers L7 and
Bottom Components. We zoom into the corresponding regions and recognize pin IC5b-
1 and IC4b-1:

Now we uncheck View: Visibility Pin Names and uncheck the check box Only
selected items (at the top of the Navigation Tree) to proceed with the SI TD simulation.

56
 In order to start a signal integrity analysis on net ADDR1 we have to prepare the
participating components first. To do this, we review the components models by
selecting Home: Components Components. The following dialog box will appear
presenting the Component Library:

In the left column we see a list with all components placed on the PCB. The first five
components are the ICs and the last is the resistor array.

We select IC1 and see that it refers to a part with name ic1x. This part is stored in the
Part Library. You can examine the part by either pressing Edit straight away in the
dialog box above or by going in the Navigation Tree and double-clicking on the
corresponding part item :

After doing so, a dialog box appears showing that the part is still undefined without an
electrical model:

The next four ICs in the list (IC2T, IC3T, IC4b and IC5b) reference the part ic2y, which
also has no electrical model. The resistor array Rarr references to an already defined
part pn-rx4array_10R.

57
 It is of model type R-HF, with some default parameters already defined:

parts.ppt_ ,
which we have downloaded from the Component Library at the beginning of this chapter.
To do this, we right-mouse-click Part Library in the Navigation Tree and select Import as
shown in the image below:

A file browser appears and allow us to select the file from the folder where
we have stored the file at the beginning of this chapter.

58
 After pressing Open, a new dialog box appears showing the parts that can be imported
from the file:

We see ic1x and ic2y defined as I/O Device. All available pins are of pin type signal. The
part pn-rx4array_10R consists of 10 Ohm resistors with parasitic capacitances of 30 pF
and parasitic inductances of 5 nH.
Since the parts are already available and only their parameters have to be updated, we
check Assign values to available parts on the bottom left of the dialog box and press
Ok. A message window tells us that the three parts have been updated successfully.

To start the SI TD analysis, we select Home: Simulation SI TD Analysis in the drop-

down list.
In the following dialog we choose the pin IC1-A1 from the Available pins panel and shift
it to the right side by pressing the add button or by dragging it with the mouse.

The workflow automatically adds IC1-A1, and in addition it also adds all other pins
connected to IC1-A1 via Used nets and Used components. In this case the two
connecting nets are ADDR1 and net1 and the connecting component is the resistor array
Rarr in between.

Both the nets and the component connected to the user selection are listed in two
separate fields in the Used nets/Used components frame. If necessary expand that field
using the small + below the Excitations/ports:

59
 The icon on the left of the resistor array indicates that this component is based on a
part library electrical model.
The green marker on the right side of the resistor indicates that the setup has found a
valid electrical model for this kind of simulation and so the whole simulation setup can
be performed successfully.
If that box is yellow indicates that the corresponding component has either no electrical
model assigned to it or that the model assigned is not suitable. The results of the
simulation may be inaccurate and not as expected in this case.

Selecting the components in the left list and choosing in the right
mouse button menu allows inspection and changes to those component models. Note
the warning message at the bottom - we will define the stimuli in a few moments.

We now close the component editor again; select the two nets ADDR1 and net1 in the
Used nets/Used components frame and see how the nets and the resistor array get
selected in the Main view:

In a next step, we assign suitable I/O models to the listed pins.

For this we select the corresponding Model field for the pin IC1-A1 and select Edit from
the drop -down menu using a double click like shown in the image below:

In the following dialog box we keep Digital Pulse as the Signal model type. The
parameter V-amplitude means the digital pulse will swing from 0V to 5V. The
paramter t-rise/fall defines the rise- and fall time in seconds.

60
 The parameter R-inner defines the dynamic inner resistance during the voltage swing
happens. We change this value to 15 Ohm and press Ok.

In a next step, we multi-select the rest of the pins and double click on the Model field in
the top control row (responsible for multiple model editing) as shown in the image
below:

We again keep Digital Pulse for the Signal model type and set the same parameters as
before for all selected pins:

For every digital pulse definition CST PCB Studio creates an equivalent simple IBIS
model during the simulation setup which will later be used in the following circuit
simulation.

61
 Next, we assign a stimulus sequence as an excitation to the pin IC1-A1 by double-
clicking into the Stimulus field of the pin and picking Select as shown in the image
below:

The Stimulus dialog box lists some default stimulus sequences.

We select the DDR_Write stimulus and close the dialog box by pressing the Ok button.
Next, we multi-select the remaining four pins and set the stimulus Quiet by pressing
Stimulus -> Select at the top row of the table with a double click to pick a value for all
selected pins.

In a last step, we define an additional parallel termination resistance at pin IC2t-1.

To do this, we double-click into the corresponding cell in the table and choose Edit as
shown in the image below:

We choose the Termination type parallel R , assign 100 Ohm to the parameter R1 as
shown in the image below and press Ok.

62
 We set the overall simulation time to 80ns. The setup of the SI TD analysis is now finished.
The setup will perform a quick local simulation run instead of generating a simulation
project.

Before we start the simulation we have a quick look at some control options. We press
the Specials button at the right side of the dialog box. A dialog box opens offering four
tabs with several control settings. More details can be found in the online help section.

63
 We see that both ohmic and dielectric losses are considered and that the generated
equivalent circuit is to be valid up to a maximum frequency of 1000 MHz. Feel free to
experiment with the effects of other control parameters.

We proceed with the signal integrity analysis by pressing the Start button at the bottom
of the SI TD dialog box. As a first step of the following automatized process, the
equivalent 2D (TL) circuit model of the selected nets is calculated. In a second step, a
complete schematic setup is generated and in a last step, the circuit simulation will be
started. This will take a few seconds and the individual steps can be observed in the
Message and Progress windows.

After the simulation is finished, we change to the schematic tab and see the generated
schematic.

64
 We see the schematic block in the center which holds the equivalent circuit of the nets
net1 and ADDR1 and in also the included equivalent circuit of the connecting resistor
array Rarr .
We can also see the corresponing IBIS blocks for the driver pin IC1-CA1 on the left
side and the other four input buffer pins on the right.

The results, i.e. the pins voltages, can be seen by selecting the values in the result
folder for the SI TD task in the Navigation tree similar to the image below:

65
 We finish the example by switching back to the SI TD dialog box and pressing the
Show Mesh button as it is shown in the image below:

An additional 2D(TL) Mesh View Manager dialog box will appear providing the list of all
the calculated 2D cross-sections. In the Main view the corresponding segments for the
cross-sections are marked in white colored frames.

We scroll through the list of cross-sections and can see the corresponding segments
getting highlighted in the Main View.

In order to see the cross-sections itself, we double-click on an element.

A separate Cross Section View window will appear showing the cross-section of the
element, which will look similar to this:

While we scroll through the list of cross-section elements keeping the cross section view
open, we see that the corresponding cross-section will change as well.

We now have finished the signal integrity analysis of a simple net. If you now added a
second net, e.g., net ADDR2, you could also check the crosstalk effects from one net to
the other. You are encouraged to trying this additional step by yourself.

Note: For further documentation on how to use CST PCB Studio for more complex signal
integrity (SI) tasks, please refer to the online documentation of CST PCB Studio.

66
 A very important task of signal integrity analysis is to determine a good layer technology.
The technology should provide the desired single-ended and differential impedances on
all the layers.
This chapter demonstrates how the impedance calculator can be used to optimize the
layer technology.

We start by creating an empty PCB Studio project. First, we open the stackup dialog box
and define a 10-layer technology as shown in the image below:

The conductor layers are equidistant from each other and all have the same thickness.
Fill is set alternatingly
layers all have the same thickness.

Next, we open the dialog box of the impedance calculator by pressing Home: Layout
Impedance Calculator. We can see a table of layers similar to the stackup manager.
There are a few more columns. Some of the additional columns are necessary to define
the distances between traces and the width of the traces. In addition, on the right-hand
side there are columns that show the impedance results after an impedance calculation.

At the bottom of the dialog box, the following message can be seen:

The reason for this is that the impedance calculator needs the information on which
layers are to be filled completely or partially with ground or power planes. These planes
have a high impact on the impedance values.
We define four reference plane layers like shown in the image below. The Type
CST PCB Studio.

In addition, we set a trace width of 0.2 mm for all the layers. We see a configuration as
shown in the image below:

67
 The tool calculates impedances even for layers that are set as reference plane layers.
In order to do this, the tool assumes that the signal tracks are guided by the ground or
power planes and define a coplanar geometry.

Now we calculate the impedances for the first time by pressing the button Calculate. The
four columns on the right-hand side of the table are now showing some impedance
values (they may vary slightly).
You can find a more detailed description on the specifics of these impedances in the
online documentation.

We press the button Specials to check the settings used by the impedance calculator.
We change the value Maximum relative error from 0.01 to 0.001. This increases the
solver accuracy regarding the optimization by reducing the relative error threshold that
is used as the iteration stop criteria.

The first impedance value we want to achieve is 50 for ZSingle on the layer TOP.
We unfold the frame Optimization at the top of the dialog box, there we select the button
Optimization, and set the options like shown in the image below:

We now want to optimize the target impedance Zsingle depending on the variation of the
thickness of the dielectric layer Insulator1.

68
 After pressing Calculate, we get as the result a value for the thickness that yields the
intended impedance of 50 .
For some reason (e.g., limit of the available technology) this value can be below a certain
threshold that we do not want to go below. We enter this imaginary threshold value, e.g.,
0.15 mm into the field Thickness for layer TOP.
In a next step, we want to achieve trace width on layer TOP
instead.
After pressing Calculate again, we get the following result:

We press To Stackup to apply the calculated value of 0.286549 mm for the trace width
to the layer TOP of the main PCB.

We then optimize the trace width of layer Layer3 to get ZSingle

(resulting in a trace width of 0.173062 mm). We do the same for layer Layer5 (result is
0.233833 mm). We aim for a symmetrical layer stackup. For this, we copy the values of
the trace width from layer TOP to layer Bottom, from layer Layer3 to layer Layer8, and
from layer Layer5 to layer Layer6.

Next, we want to achieve differential impedances

optimize the trace gap on these layers. For this, we need again to choose the respective
target and variate variables. If everything was done correctly, the optimization gives the
trace gap values of 0.220683 mm on TOP, 0.188951 mm on Layer3, and 0.257296 mm
on Layer5.
Again, we make the stackup symmetrical by copying the values for the trace gap to the
layers in the lower half of the stackup.

Finally, we uncheck the button Optimization and start a verification calculation by

pressing Calculate. The results now should look like shown in the image below:

In a last step, we check the cross-section that is the basis to calculate one of the
impedance values. To do that we double-click in the table on the impedance value
ZDifferential on layer Layer5.

69
 We see the cross-section corresponding with this value. It looks like the image below:

To apply all the changes of the layer settings of the Impedance Calculator back to the
CST PCB Studio layer stackup, press the button Apply at the bottom of the dialog box.
The Reset button next to it replaces the current setting in the Impedance Calculator with
the defaults from the PCB.

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 The purpose of this example is to introduce the
Selection, and Modeling dialog for the 3DFEFD solver
Impedance analysis with focus on power integrity

In this chapter, we want to investigate the impedance of a power delivery network (PDN).
The stackup of our example consists of four metallic layers (two GND, two VCC). The
GND layers are connected through vias, and similarly, the VCC layers are connected
through other vias:

The bottom VCC- and GND-layers are loaded with two decoupling capacitors C1 and
C2, which are located at the bottom side of the board. In addition, the top side of the left
via pair is loaded at X1, drawing power from both the VCC and GND layers. We are
interested in the impedance that is seen from X1.

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 We create a new project by importing the existing PCB design Power Integrity Analysis
from the Component Library. In a first step, we locate the attachment using and
click on the folder icon next to the attached power delivery system.dar file. We
download the file by pressing the Download button in the upper right corner and import
it into PCB Studio:

and then start to examine the design.

On the lower left of the PCB, we see the red image of component X1. It provides the
port where we want to analyze the impedance. We go to the View Attributes window and
select layer TOP.

We now see the two drills connecting X1 to VCC (on this layer) and to GND (on the layer
below):

We zoom into the region around the drills to see there is a connection between the
conductor on the layer and the left drill, and no connection between the layer and the
right drill because of a cutout in the area shape:

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 Now we zoom out again and change to layer BOT to see the drills and the connections
for the two decoupling capacitors (see image below) and finally select layer Bottom
Components to see the capacitor components.

In order to have a closer

Navigation Tree and expand folder Components as shown this image:

We select C1 and choose Edit by using the right mouse button or a double click. The
following dialog box will appear:

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 We see C1 refers to a part model definition in the part named Cap. In order to edit this
part, we press the highlighted Edit button (see image above). A dialog box allows to
assign a Touchstone file to this part.

In order to replace the model with a simple capacitor model, pick Standard Model from
the Model type drop-down menu.

The dialog box changes and we can set the corresponding capacitor model for the part
Cap:

We change the capacitance value to 1.0 nF, leave the values for the parasitic resistance
and parasitic inductance and finally press Ok. For the second capacitor C2, we do not
have to make any further settings, since C2 also refers to the same part Cap.

Before starting with the simulation setup, we briefly explore the component X1:

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 We see that the part reference X1 is a generic Vendor Device or Undefined Device type,
which has no internal electrical model defined in the Part Library. We do not need a
further examination of this component since X1 will only be used to define a port in the
following impedance analysis.

We start the simulation task by selecting Home: Simulation PI Analysis in the drop-
down list. The following dialog box will appear:

We see that by default there are only power pins listed in the Available pins frame. This
is because PI-analysis is a power analysis tool so only power pins and their related
ground reference pins are of interest.

We want to calculate the impedance between the VCC- and GND-pin of X1. We select
the pin X1- and click on the highlighted button in the center of the dialog to add
the port. On the right, we now see a new port consisting of the selected power pin and
its corresponding ground reference pin.

We set the Simulation settings as follows:

With the button Consider components, we can control whether the linear two-pin
components (resistors, inductors, capacitors), which will be listed in the Used nets/Used
components frame should be considered during the simulation or not.
For the first simulation, we uncheck the button and press Start.

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 After a few seconds, a result like the one below will appear in CST Design Studio:

If we expand the Used nets/Used components frame, we can now see that the two
capacitors C1 and C2, which both are connected to net VCC and net GND. This
indicates that they were involved in the simulation.

In order to store the curve for a comparison afterwards, we generate a folder with name
comparison below the Results folder and copy the result curve from the Impedances
folder into the comparison folder under the name without decaps as shown in the image
below:

Now we change back to the Solver Settings tab and set the value of Consider
components to true:

prompt and press the Start button once

again. After another few seconds the new curve will appear.
The curve now includes the effect of the decoupling capacitors.

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 We copy this curve under the name with decaps in the comparison folder and compare
two plots as shown in the image below:

In order to get a logarithmic scaling of the curves, we change the setting in the 1D Plot
ribbon accordingly:

We press OK and the resulting curves should look like in the figure below:

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 We go back to the PI solver dialog and press the Specials-button. In the dialog box, we
select the Spatial Impedance Plots-tab as shown in the image below:

We activate the Generate plots flag and choose the bottom layer BOT as Reference
layer. This causes the electric potential on this layer to be considered as zero.

Once we repeat the impedance calculation, the 2D results will appear in the PCB Main
View similar like to the image below:

Please note the Plot Type option in the ribbon. It is switched to Maximum.

On the left, there is a list of calculated frequencies, where a local impedance maximum
occurred. You can select any of them and watch the corresponding impedance
distribution.

You can find more information about PI Analysis in the online documentation.
Especially the EDA Decap Tool is an interesting add-on to analyze and improve PDN
behavior.

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 The purpose of this example is to acquaint you with the
Most important tools to edit and navigate through a PCB.
Selection, Meshing and Modeling dialog box for PEEC.
Usage of the PEEC model in the circuit simulator.
Frequency domain analysis.

For many PCBs, it is common practice to provide different power delivery systems for
different applications. It is for example common for the analog and digital systems on
the board to have a separate power delivery.
A standard measure to prevent noise coupling from one power system to the other is to
separate the power planes by introducing slots. In order to check the effectiveness of
the slot in the higher frequency range, 3D (PEEC) modeling can be used and this is
demonstrated in the example below.

We create a new project by importing the existing PCB design

Reference Ground Conductor either load the project from the component library or
download the corresponding split plane.dar file and import it into CST PCB Studio:

Power Crosstalk with Reference Ground Conductor

start with an inspection of the stack-up technology.
To do this, we expand the folder Navigation Tree: Technology Layers.
We can find four metallic layers L_Power, L_Signal1, L_Signal2, L_Gound and the
corresponding dielectric layers in between.

In order to investigate the layers, we go to the View Attributes window, select the Layers
tab and then select the first layer Top Components. All other layers are hidden now.

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 Next, we switch on the object spy (View: Visibility Object Spy) and move the mouse
pointer over one of the red marked frames at the bottom.

We select layer L_Power and see two different planes separated by a thin slot:

In addition to the slot, we see the characteristic via pattern of the SMA sockets.

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 We switch off Object Spy and zoom into the region of the bottom left socket:

It can be seen, that the via pad in the center is connected to the power plane whereas
the pads of the four outer vias are connected to ground and are separated by a cutout
(in black).

We again zoom out (by using right mouse click or selecting Reset view to structure from
the drop-down menu / Space key) and select the next layer L_Signal1. The layer is
empty but for the small conductive pattern of the vias and their corresponding pads and
the same applies to L_Signal2.

We select L_Ground. We see a single plane with a cutout on the left.

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 If we zoom back into the region of one of the sockets, we now see the pads of the outer
vias are connected to the surrounding plane and the pad of the center via is
disconnected:

The layer Bottom Components is an empty layer.

In order to investigate the layer stack-up technology we press Home: Layout Stackup.
We look at the Prepreg parameter and see its value is Nominal, which indicates the
metallic layer is pressed into the surrounding layers and their thickness does not count
for the total board thickness.
We also see the two upper metallic layers are of type Fill = Above, whereas the two
lower metallic layers are of Fill = Below. For further details on the Prepreq- and Fill
parameter you can refer to the CST PCB Studio online help.

The top and bottom dielectric layers have a thickness of 0.12 mm whereas the one in
the center has a thickness of 0.14 mm.
The material for all dielectric layers is fr4 and the overall thickness of the board is about
0.4 mm. This will later determine the mesh size in the Meshing and Modeling section.

We continue our investigation by having a look at the available nets.

We first select layer L_Power in the Layers tab of the View Attributes window. Then we
select View: Color Color Mode Nets and once again change to the View Attributes
window to select the Nets tab.

We select VCC1 and VCC2 by using Shift + left mouse button. In order to see the pin
names of the nets on these layers, we press View: Visibility Pin Names and make
sure that the zoom level is big enough to visualize the pin names.

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 We should now see something similar to the following image:

To see the GND net on the L_Ground layer first select net GND in the Nets tab (in the
View Attributes window) and then change to tab Layers and select layer L_Ground.

If you zoom into the lower region, you will see each socket connects to GND through the
four pins.

If the text size of the pin names does not fit, we can change it in a dialog box that you
can open with View: Options View Options

We zoom out again and switch on the axes via View: Visibility Axes. Displaying the
axes scaling helps to estimate the real dimensions of the PCB and this can give a good
orientation on the mesh size to choose in the next section.

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 After selecting the two layers Top Components and L_Ground the Main View now should
look similar to the image below:

Before we open the meshing dialog box, we will finish the inspection by having a look at
Home: Layout Net Editor.

We see that net GND is of net class ground and the two nets VCC1 and VCC2 are of
net class power. This is an important fact because any net of net class ground or power
can be treated as an ideal reference conductor during the 3D (PEEC) modeling
process. No separate inductive or capacitive elements will be generated for reference
conductors. Their contribution is considered in the capacitive and inductive value of the
remaining signal elements.

Assigning the net class ground to a net and choosing net class ground as reference can
speed up the modeling and simulation phase, but it is only effective if the assumption of
an ideal reference conductor is sufficiently fulfilled. A conductor can be interpreted as
an ideal reference conductor if it allows a sufficient current return path along the path
near the corresponding signal conductor.
This is, for instance, not true, if the conductor has considerable slots or constrictions.
As a first step, we will model the GND net as an ideal reference conductor and then
change this to see the effect of the slot in the conductor.

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 Here we select the three nets in the Navigation Tree as shown in the image below:

We select Home: Parasitic Extraction 3D (PEEC) Model. In the dialog box, we choose
the Selection tab. We add the three selected nets by either pressing the Add button or
by dragging the nets in from the navigation tree:

These three nets will now be considered during the meshing and modeling phase. We
expand net GND in the list of Selected Nets:

We see the list of all available pins on net GND. Every checked pin will appear as a
terminal in the equivalent circuit, which will be generated later, provided that GND is not
considered as a reference conductor. Although GND will be interpreted as a reference
conductor in the first simulation, we already prepare the pin selection for the later
simulation setup.

The two pins of interest are SMA11_1-2 and SMA11_2-2. All other pins should be
unselected by clicking on the corresponding check box. Expand net VCC1 and VCC2
and see the available pins are selected by default.

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 We keep these settings and move to the Meshing tab:

We now want to investigate the different available settings. The first frame, Extraction
settings for net class power and ground , determines whether net class power and
ground should be modeled as a reference conductor (simplified null potential) or not.

In addition, a Channel width can be assigned individually to both net class power and
ground. The channel width can significantly reduce the size of the overall structure to be
calculated. This is a powerful feature when modeling transmission lines along or
between reference conductors, because the whole reference conductor will not be
considered but only parts within the specified channel width around the transmission
line.
In our example, there is no transmission line, but instead there are power planes which
are of similar size as the ground reference planes. Therefore, specifying a channel width
does not make sense. We can turn off the option for both net class ground and net class
power (see image above).

The Meshing settings allows the specification of the mesh cell size for the PEEC mesh
cell. We set the value to 1.2 mm and keep the other parameters with their default values.

The next frame is Dielectric settings. If we drop down the menu Board Dielectric, we see
four choices of how to treat the dielectric layers during the modeling phase:

The first entry, layer stack (original), means each dielectric layer will be considered
during the capacitance calculation. This is the costliest, but also most precise
consideration of the dielectric layers.

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 The second item average (between signal layers) performs an averaging of all dielectric
layers between two adjacent metallic layers.

The third item, average (total board), causes an averaging between all dielectric layers
of the board. This approximation speeds up the capacitance calculation procedure but
the user has to be aware of this simplification. In our case, there are three dielectric
layers consisting of the same material and so we will choose this option for our
calculation without any loss of accuracy.

The last item, none (uniform), ignores the presence of any dielectric and the user is able
to define a background dielectric material. Choosing this function makes the capacitance
calculation as fast as possible. It can be useful for a rough and quick estimation of the
electromagnetic effects or in cases where the capacitive effects of the board are not
dominant.

Checking the box Shrink board outline helps to shrink the overall board when only
conductors in a small bounded region are selected. In this case, the mesher avoids
meshing the entire dielectric layer of the board but adapts the board outline to an
adequate size around the selected conductors. In our case, the selected conductors fill
the whole board outline and so
Shrink board outline parameter activate.

The settings frame Regions allows the setting of a finer mesh for user defined regions
on the board. We do not need this function right now and this also is true for the last
settings frame, Geometry simplification. It allows the setting of parameters controlling
the abstraction of the board during the layout import. These parameters should only be
changed by expert users, for details please refer to the online help.

In order to start the meshing, press Start Meshing in the lower left corner of the tab. The
meshing process will start showing some information in the Message Window. There
will be a warning No DC path from following terminals .
This means, there is no further terminal for the corresponding nets VCC1 and VCC2
found and so there will be no DC connection. Since we are interested in a crosstalk
analysis between VCC1 and VCC2, we can ignore this message.

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 The meshing process will run for a few seconds and the result can be checked by
pressing the Show Mesh button. The mesh view will open in the PCB tab:

In the View Attributes frame on the right, we deselect the first two layers
(Top_Components and L_Power). We change to the 3D View using View: Change View
3D View and rotate the meshed structure as shown in the image below:

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 We finally reset the view by pressing the space bar. We now switch to the Modeling
settings.

In the Modeling settings frame, we uncheck Dielectric losses in order to get a simpler
model and leave all other parameters at their default values.

We take a look at the Parameter calculation frame:

The settings apply for both inductance and capacitance calculations. In general, there
are two calculation methods: complete or step by step
means that all mesh elements (careas and isegs) will be coupled with each other. This
is the classical PEEC approach but it can cause two problems:

First, the coupled capacitive areas, for example, are modeled by using a static
capacitance and the longest distance between these areas limits the maximum allowed
frequency range of the model. In case of complete, the maximum valid frequency is
directly limited by the size of the board, ignoring all screening effects that can lead to a
considerable decoupling between different regions of the board.

in general leads to longer calculation times.

The method is started by the solver only if the Maximum number of elements for
complete calculation is not exceeded. The method often leads to larger equivalent
circuits that can only be avoided by using the Tolerance limit for minor couplings.

The calculation method complete should only be used when a PCB has only a few
metallic structures and so fewer screening effects for decoupling certain regions can be
expected. This is sometimes true for single-layer or double-layer PCBs.

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 In all other cases, the calculation method step by step is recommended. With this
method, the complete capacitance (or inductance) matrix is constructed using several
calculations on different sub-regions. The size of these sub-regions is best chosen by
setting the radius value in the Search by field.

In general, the Search radius should be about ten times the distance between the
metallic layers or at least three times the mesh size to make sure the available
conductors can lead to the expected screening effects. Screening only takes place within
an environment with considerable conductive materials.

In our case, there is a high presence of conductive materials on both layers allowing
good screening. The mesh element size was set to 1.2 mm and the distance between
the layers is about 0.4 mm, so we pick 4.0 mm as Search by radius.

Choosing value factor in the field Search by makes the program define an adequate
radius based on the existing distances between the conductors.

As a last step, we change the Tolerance limit for minor couplings to 0.2 % as shown in
the image below. The solver will delete all off-diagonal entries of the inductance- and
capacitance matrix, which are lower than 0.2 % of their corresponding main-diagonal
values. This leads to a sparser PEEC model and to a faster simulation, especially if the
Calculation method is set to complete.

Now we press the button Update Schematic. The generation of the corresponding
schematic block will take only a few seconds and we change to the Schematic tab:

We can see the two pins of net VCC1 and VCC2. Because of the assumed ideal
reference behavior of net GND, there is no need for more pins and we can connect the
loads between the pins and the ground reference symbol.

90
 We load the schematic block at both sides with a 50-Ohm resistor and put an excitation
port on at the left side. In addition, we put a probe at the right side of the block.

Note: the direction of the probe in your project can differ from the direction in the image

connector where the probe is placed on. T by how the

connector was drawn, either from the left pin to the right pin or vice versa. Since we are
will not influence our
results.

Next, we define an AC-task by pressing Home: Simulation New Task. A dialog box
will appear where we select AC, Combine results as shown in the image below:

In the Task Parameter List, we select the AC tab and choose Fmin=0.005 GHz,
Fmax=0.5GHz and the number of Samples=80 as shown in the image below:

Next, we change to the Excitations tab of the Task Parameter List, select Load and
choose Define Excitation from the drop-down menu as shown in the image below:

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 In this dialog box, we keep the default parameters and close the box again by pressing
the Ok button.

Now we select Home: Simulation Update and start the simulation. In a first step, the
inductances and capacitances of the 3D (PEEC) model will be calculated. In a second
step, the actual circuit simulation starts. The Messages window informs about the
progress and when the whole simulation task is finished.

To show the results in an appropriate way, we go into the Navigation Tree, select folder
Results, choose Add Result Plot (by using the right mouse button) and name the new
result folder GND as reference:

We open the result folder, select AC1 FD Voltages P1 and copy it.

We paste it into the newly created result folder and rename it.

Now we generate another 3D (PEEC)model using the calculation method complete

instead of step-by-step to compare the two methods.
To do this, we change back to the PCB tab and press Home: Parasitic Extraction 3D
(PEEC):

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 Once we switch to complete as Calculation Method, we will be prompted to accept the
value change and deletion of the old model. We agree with Yes.
Then we switch back to the Schematic tab and restart the simulation by pressing Home:
Simulation Update.

The simulation may take a few seconds longer than the previous one. In order to
compare the new result with the existing one, we put the result of the first simulation into
the folder GND as reference and rename it to step by step. Then put the newly created
result into the same folder and call it complete.

We now see a second curve that is almost identical to the first:

In order to see the effect of the cutout in the net GND, we must consider the net GND
as a regular net and not as a reference conductor. To do this, we change back to the
PCB tab and again chose Home: Parasitic Extraction 3D (PEEC).

In this dialog box, we select the Meshing tab and uncheck the Model netclass ground
as reference button. We will be prompted to accept the value change and we press Yes.
The settings in the Extraction settings for netclass power and ground frame should
look like in the image below:

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 Next, we select to the Modeling tab and change the Calculation Method back to step-
by-step as shown in the image below:

Again, we press Update Schematic and see the information in the Messages window.

In order to prepare the setup of this PEEC model, we recommend removing the
ground symbols, the electric connection lines and the probes from the schematic block
by simply selecting them and pressing delete.

We start with the following schematic, making sure the four terminals are selected:

First, we transform the port 1 to a differential port. To do this, we select the Port P1
appearing in the Navigation Tree. Then we select the property Show port reference in
the Block Parameter List.

Once we do so, we will see an additional terminal below the yellow port and we can
complete the schematic setup like in the image below:

Finally, we place a differential probe between both terminals on the right-hand side as
shown above. To do this, we select the two corresponding connector lines and perform
Home: Components Probe.

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 Now we can run the simulation again by pressing Home: Simulation Update. The
simulation will take noticeably longer than for the previous ones since the GND system
is calculated as well.

The differential voltage of interest is now called P1 Diff. Comparing the new result with
the two curves from the previous pages we see that the peak is a somewhat smaller.
Overall, the result shows no significant influence from the cutout in the net GND:

We will now slightly change the layout by introducing two terminals on either side of the
slot as can be seen in the image below:

The two terminals are defined as follows:

T1: Layer L_Power, Net VCC1, Position x=39.5, y=315.0
T2: Layer L_Power, Net VCC2, Position x=40.5, y=315.0

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 Next, we change the global frequency unit in Schematic to MHz:

In the Meshing tab, we model the netclass ground as reference and choose a suitable
channel width.

We keep the existing settings in the Modeling tab and start the 3D (PEEC)modeling by
pressing the Update Schematic button.

Now we change to the schematic tab and see the schematic block with two new pins for
both terminals T1 and T2. Between T1 and T2 we connect a resistor with 0.1 Ohm, the
rest will be loaded like in the setups before.

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 Next we set-up an AC-task in the frequency range from to .

As excitation we again choose an ideal voltage source of . This means that the
excitation need to be changed.

After pressing the Update button the simulation will take a few seconds. The calculated
voltage on probe P1 is shown in the figure below:

It can be seen that the transmitted voltage decreases for frequencies higher than 3 MHz
and this is due to the inductance and capacitance properties of the layout structure.

It is sometimes useful and necessary to consider such parasitic layout effects in a more
complex system simulation. One way would be to export the complete equivalent circuit
of the PEEC model but this often would overwhelm the whole setup. And often the user
is only interested in the first order effects which can be accurately modeled by a reduced
low frequency approximation of the PEEC model.

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 We now generate such a low-frequency approximation model by going back into the
Modeling tab.
First, we check the button LF reduction at and set the corresponding frequency, where
the approximation should take place, to 1.0 kHz:

In the Export model frame, we choose Spice3 as simulator output type and specify the
name and folder the SPICE subcircuit file should be written to.
The final step is to press the Export Model button and wait for the modeling and export
process to finish.

In order to see the similar behaviour of this SPICE circuit we open a new Circuits &
Systems Schematic project and import the SPICE sub-circuit by going into the Block
Selection Tree, selecting the folder Data Import and draging the SPICE block onto the
empty schematic sheet:

A file browser appears where specify the Spice circuit file which we have exported
previously.

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 Next, we rearrange the pins of the Spice block and load them as it was done for the 3D
(PEEC) block before:

As a last step we set-up an identical AC-task as in the simulation before. After pressing
the Update button the simulation provides a very similar result, but within a significantly
shorter calculation time:

Such equivalent circuits can be used to expand existing SPICE setups e.g., to consider
parasitic layout effects during the simulation of a switched power supply.

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 CST PCB Studio is designed to be easy to use. However, to work with it in the most
efficient way the user should know the principal methods behind it. The main purpose of
this chapter is to explain the theoretical concepts.

The Partial Element Equivalent Circuit (PEEC) method divides a selected 3D structure
(including conductors and dielectrics) into a mesh of short conductive segments and
small conductive and dielectric areas. Constant currents within the segments and
constant charges on the areas are assumed.

There are different types of PEEC methods that differ in the way they treat retardation
effects and in the way they handle dielectrics. The common feature of all types of PEEC
methods is the transformation of the electromagnetic field problem into an electric
network that can be simulated with a network simulator in time and frequency domain.
Because of the electric connection of the conductive segments in the network simulator,
the models work for low frequency and DC.

CST PCB Studio uses a quasi-static 3D (PEEC) approach. The magnetic coupling
between the conductive segments is done by inductive coupling devices and the electric
coupling between the conductive areas is done by capacitors, which takes into account
the impact of the dielectric areas.
The size of the circuit can be reduced by the amount of the dielectric areas and this is a
big advantage of this approach but also the reason for limitations on the maximum
allowed frequency.
The longest distance between two coupled elements (segments or areas) limits the
maximum frequency range of the whole circuit. The program evaluates the maximum
valid frequency automatically.

There are many applications of the 3D PEEC method and CST PCB Studio features
additional approximation tools in order to enable the usage for complex PCBs. However,
the most appropriate applications for this method are boards with a small number of
layers and no reference plane with clearly defined characteristic impedances present.
This means the 3D (PEEC) method is most suitable in the case that the conductors
cannot be modeled as microstrips or striplines due to the absence of a ground, from
which the characteristic impedance could be determined.

The Transmission Line Modeling method parses a single trace or a group of traces and
divides them into a finite number of straight segments. For each segment, the program
checks for any conductive areas surrounding the traces which may serve as reference
conductors. All traces in a segment, in combination with additional reference areas,
define its cross-section. A static 2D field solver will calculate the primary transmission
line parameter per unit length (R , L , C .

In a following step, all segments will be transformed into an equivalent circuit. The
procedure even considers vias and creates related equivalent circuits as well.
Finally, all circuits are connected together into one single electrical model representing
the whole trace or group of traces.

The procedure implies that only TEM propagation modes can be considered and this
causes two limitations. First, the model is only valid in a frequency range from DC to a
maximum frequency. This is due to the fact, that the primary transmission line
parameters are static parameters and only valid when the geometric dimensions behind

100
 the calculation are significantly smaller than the shortest wavelength of the propagating
wave. A second limitation is that additional effects on typical discontinuities like bends,
deviations or open ends are not considered.

The method is best used in the classical SI analysis where wave propagation effects on
signal lines into high-speed multi-layer boards have to be analyzed. The method
assumes ideal power delivery systems and does not take into account any effects like
ground bouncing.

The 3D (FE FD) solver is based on the frequency-domain Finite-Element method,

combined with a domain-decomposition approach. Problem-adapted basis functions are
used to improve simulation performance by exploiting the structural characteristics of
the PCB.

In order to explain the underlying idea, we first note that multi-layer PCBs, despite their
first-sight high complexity, exhibit strong internal structuring, such as the layer-based
geometry, solid power/ground planes, highly repetitive local via domains, and signal
traces which follow strong design constraints, like bounding to reference planes and 45-
degree routing, just to name a few.
It is clear that exploiting these characteristics within a numerical method leads to
tremendous performance improvements when compared to a general but monolithic
approach (like standard Finite Elements).

Thus, as an essential first step, the present solver algorithm identifies the partial volumes
(called specific domains) of the whole PCB volume that allows a specialized and efficient
numerical description, due to the above-mentioned structural elements.
In the current version, these are: (i) domains sandwiched between copper areas/planes,
possibly containing intermediate signal layers, (ii) vias and their local surroundings, (iii)
domains containing microstrip lines.
Ideally, the specific domains cover all relevant aspects of the PDN.

CST PCB Studio specializes in the fast and accurate simulation of electromagnetic
transmission effects of PCBs. This specialization brings some limitations which are
summarized below:

The 3D (PEEC) modeling method is based on a quasi-static 3D approach where all

selected conductors are divided into a number of elements and transferred into an
equivalent circuit consisting of resistors, inductors and capacitors. The capacitor and
inductor representing the longest distance between two mesh elements limit the
maximum frequency range of the whole circuit. The program evaluates the maximum
valid frequency automatically.
The 2D (TL) modeling method is based on classical transmission line theory where
all selected transmission lines are divided in a finite number of straight segments
with constant cross-sections and is used for signal-integrity applications (SI TD
and SI FD Analysis). For each segment the primary transmission line parameters
( ) will be calculated via a 2D static field calculation.
This means the maximum frequency range is limited by the largest dimension of the
cross-section within a segment. The solver determines the maximum valid frequency
automatically.
The 3D (FE FD) method has been developed with the focus on power-integrity
applications (PI Analysis). As described above, the current implementation
accurately models the full-wave electromagnetic effects for the typical building
blocks of power-distribution networks (PDN) of multi-layer PCBs. These are, (i)

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 domains sandwiched between PDN copper areas/planes, (ii) vias and their local
surroundings, (iii) domains containing microstrip lines. The solver should therefore
be used for analyzing PDNs with distributed capacitance (power/ground plane pairs).
In turn, if this precondition is not met, other modeling techniques are recommended,
e.g., 3D (PEEC).

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 The online help system is your primary source of information. You can access the help
File: Help Help Contents . The
online help system includes a powerful full text search engine.

In each of the dialog boxes, there is a specific Help button, which opens the
corresponding manual page. Additionally, the F1 key gives some context sensitive help
when a particular mode is active. For instance, by pressing the F1 key while a block is

When no specific information is available, pressing the F1 key will open an overview
page from which you may navigate through the help system.

Please refer to the CST Studio Suite - Getting Started manual to find some more detailed
explanations about the usage of the CST Studio Suite Online Documentation.

The component library provides tutorials and examples, which are generally your first
source of information when trying to solve a particular problem. See also the explanation
given when following the Tutorials and Examples Overview link on the online help
that you browse through the list of all available
tutorials and examples and choose the one closest to your application.

Before contacting Technical Support, you should check the online help system. If this
does not help to solve your problem, you find additional information in the Knowledge
Base and obtain general product support at 3DS.com/Support.

More information concerning the built-in macro language for a particular module can be
VBA book: Visual Basic (VBA) Language.

An overview and a general description of the macro language.

A description of all specific macro language extensions.
A syntax reference of the Visual Basic for Applications (VBA) compatible macro
language.
Some documented macro examples.

An overview of important changes in the latest version of the software can be obtained
by following the link
from the File: Help backstage page. Since there are many new features in each new
version, you should browse through these lists even if you are already familiar with one
of the previous releases.

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