EXAMPLE 4–7

The Boolean expression for an exclusive-OR gate is AB + AB. With this as a starting
point, use DeMorgan’s theorems and any other rules or laws that are applicable to
develop an expression for the exclusive-NOR gate.

Solution
Start by complementing the exclusive-OR expression and then applying DeMorgan’s
theorems as follows:

AB + AB = (AB)(AB) = (A + B)(A + B) = (A + B)(A + B)

Next, apply the distributive law and rule 8 (A # A = 0).

(A + B)(A + B) = AA + A B + AB + BB = A B + AB

The final expression for the XNOR is A B + AB. Note that this expression equals 1 any
time both variables are 0s or both variables are 1s.

Related Problem
Starting with the expression for a 4-input NAND gate, use DeMorgan’s theorems to
develop an expression for a 4-input negative-OR gate.
EXAMPLE 4–10

Simplify the following Boolean expression:

[AB(C + BD) + A B]C
Note that brackets and parentheses mean the same thing: the term inside is multiplied
(ANDed) with the term outside.
Solution
Step 1: Apply the distributive law to the terms within the brackets.
(ABC + ABBD + A B)C
Step 2: Apply rule 8 (BB = 0) to the second term within the parentheses.
(ABC + A # 0 # D + A B)C
Step 3: Apply rule 3 (A # 0 #D = 0) to the second term within the parentheses.
(ABC + 0 + A B)C
Step 4: Apply rule 1 (drop the 0) within the parentheses.
(ABC + A B)C
Step 5: Apply the distributive law.
ABCC + A BC
Step 6: Apply rule 7 (CC = C) to the first term.
ABC + A BC
Step 7: Factor out BC.
BC(A + A)
Step 8: Apply rule 6 (A + A = 1).
BC # 1
Step 9: Apply rule 4 (drop the 1).
BC

Related Problem
Simplify the Boolean expression [AB(C + BD) + AB]CD.
EXAMPLE 4–26

Map the following SOP expression on a Karnaugh map:

B C + AB + ABC + ABCD + A B CD + ABCD

Solution
The SOP expression is obviously not in standard form because each product term does
not have four variables. The first and second terms are both missing two variables, the
third term is missing one variable, and the rest of the terms are standard. First expand the
terms by including all combinations of the missing variables numerically as follows:
B C + AB + ABC + ABCD + A B CD + ABCD
0000 1 0 0 0 1100 1010 0001 1011
0001 1001 1101
1000 1010
1001 1011
Map each of the resulting binary values by placing a 1 in the appropriate cell of the
4-variable Karnaugh map in Figure 4–32. Notice that some of the values in the expanded
expression are redundant.
CD
00 01 11 10
AB
00 1 1

01

11 1 1

10 1 1 1 1

FIGURE 4–32

Related Problem
Map the expression A + CD + ACD + ABCD on a Karnaugh map.
 Related Problem
Use a Karnaugh map to simplify the following SOP expression:
W X Y Z + WXYZ + WX YZ + WYZ + WX Y Z

SOLVE by Yourself :-) .. This Related Example is IMportant. you may ignore other ones..
EXAMPLE 5–1

In a certain chemical-processing plant, a liquid chemical is used in a manufacturing

process. The chemical is stored in three different tanks. A level sensor in each tank
produces a HIGH voltage when the level of chemical in the tank drops below a speci-
fied point.
Design a circuit that monitors the chemical level in each tank and indicates when the
level in any two of the tanks drops below the specified point.

Solution
The AND-OR circuit in Figure 5–2 has inputs from the sensors on tanks A, B, and C as
shown. The AND gate G1 checks the levels in tanks A and B, gate G2 checks tanks A
and C, and gate G3 checks tanks B and C. When the chemical level in any two of the
tanks gets too low, one of the AND gates will have HIGHs on both of its inputs, causing
its output to be HIGH; and so the final output X from the OR gate is HIGH. This HIGH
input is then used to activate an indicator such as a lamp or audible alarm, as shown in
the figure.

A B C

G3

X Low-level
G2
indicator

G1

FIGURE 5–2

Related Problem*
Write the Boolean SOP expression for the AND-OR logic in Figure 5–2.

*Answers are at the end of the chapter.

EXAMPLE 5–6

Develop a logic circuit with four input variables that will only produce a 1 output when
exactly three input variables are 1s.
Solution
Out of sixteen possible combinations of four variables, the combinations in which there are
exactly three 1s are listed in Table 5–5, along with the corresponding product term for each.
TABLE 5–5
A B C D Product Term
0 1 1 1 ABCD
1 0 1 1 ABCD
1 1 0 1 ABCD
1 1 1 0 ABCD

The product terms are ORed to get the following expression:

X = ABCD + ABCD + ABCD + ABCD
This expression is implemented in Figure 5–13 with AND-OR logic.

D C B A FIGURE 5–13 Open file

F05-13 to verify the operation.

ABCD

ABCD

ABCD

ABCD
The logic gates required are three inverters, three 3-input AND gates and one 3-input
OR gate. The logic circuit is shown in Figure 5–12.
C B A FIGURE 5–12 Open file F05-12 to
verify the operation.

C B A
ABC

ABC
X

ABC

Related Problem
Determine if the logic circuit of Figure 5–12 can be simplified.
EXAMPLE 5–8

Minimize the combinational logic circuit in Figure 5–16. Inverters for the comple-
mented variables are not shown.
A
B
C
A
B
C
D
X
A
B
C
D
A
B
C
D
FIGURE 5–16
Solution
The output expression is
X = AB C + ABC D + A B CD + A B C D
Expanding the first term to include the missing variables D and D,
X = AB C(D + D) + ABC D + A B CD + A B C D
= AB CD + AB C D + ABC D + A B CD + A B C D
This expanded SOP expression is mapped and simplified on the Karnaugh map in Fig-
ure 5–17(a). The simplified implementation is shown in part (b). Inverters are not shown.
CD
AB 00 01 11 10

00 1 1 BC
A
C
01 D
X
11 1 ACD
B

10 1 1 C

(a) (b)

FIGURE 5–17

Related Problem
Develop the POS equivalent of the circuit in Figure 5–17(b). See Section 4–10.
EXAMPLE 6–2

Determine the sum generated by the 3-bit parallel adder in Figure 6–8 and show the
intermediate carries when the binary numbers 101 and 011 are being added.

1 0 0 1 1 1

A B Cin A B Cin A B Cin

FA3 FA2 FA1
Cout Σ Cout Σ Cout Σ
1 1
Σ4 Σ3 Σ2 Σ1
1 0 0 0
FIGURE 6–8
Solution
The LSBs of the two numbers are added in the right-most full-adder. The sum bits and
the intermediate carries are indicated in blue in Figure 6–8.

Related Problem
What are the sum outputs when 111 and 101 are added by the 3-bit parallel adder?
EXAMPLE 6–14

The data-input and data-select waveforms in Figure 6–45(a) are applied to the multi-
plexer in Figure 6–44. Determine the output waveform in relation to the inputs.

D0

D1

D2

D3

S0 0 1 0 1 0 1 0 1

(a) S1 0 0 1 1 0 0 1 1

(b) Y

D0 D1 D2 D3 D0 D1 D2 D3

FIGURE 6–45

Solution
The binary state of the data-select inputs during each interval determines which data
input is selected. Notice that the data-select inputs go through a repetitive binary
sequence 00, 01, 10, 11, 00, 01, 10, 11, and so on. The resulting output waveform is
shown in Figure 6–45(b).

Related Problem
Construct a timing diagram showing all inputs and the output if the S0 and S1 wave-
forms in Figure 6–45 are interchanged.
EXAMPLE 6–18

The serial data-input waveform (Data in) and data-select inputs (S0 and S1) are shown in
Figure 6–53. Determine the data-output waveforms on D0 through D3 for the demulti-
plexer in Figure 6–52.

Data
in
S0
S1

D0 1 0
D1 1 0
D2 0 1
D3 1 1

FIGURE 6–53

Solution
Notice that the select lines go through a binary sequence so that each successive input
bit is routed to D0, D1, D2, and D3 in sequence, as shown by the output waveforms in
Figure 6–53.

Related Problem
Develop the timing diagram for the demultiplexer if the S0 and S1 waveforms are both
inverted.