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All About Architecture

The document compares Von Neumann and Harvard architectures, highlighting that Von Neumann uses a single memory for both data and instructions, while Harvard has separate memories and buses for each. It includes diagrams illustrating the system buses and the fetch-decode-execute cycle, as well as how pipelining can enhance computer throughput. Additionally, it outlines the stages of a RISC processor's instruction cycle.

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nigelnyats
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13 views4 pages

All About Architecture

The document compares Von Neumann and Harvard architectures, highlighting that Von Neumann uses a single memory for both data and instructions, while Harvard has separate memories and buses for each. It includes diagrams illustrating the system buses and the fetch-decode-execute cycle, as well as how pipelining can enhance computer throughput. Additionally, it outlines the stages of a RISC processor's instruction cycle.

Uploaded by

nigelnyats
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

All about architecture

Different between von nuemann and Harvard architecture

Von neumenn Harvard


Data and instructions or program processed data Contains two separate areas and for program and
are stored in some memory instructions
Only one bus to transfer both data and Uses two separate buses for data and instructions
instructions

The diagram which illustrate system buses in von neuman architecture

CPU Memory Input and output

Control bus

Address bus

Data bus

With the aid of a diagram show who pipelining can increase the through put of a computer

fetch decode execute


Instruction 1
Instruction 2 Instruction 1
Instruction 1 Instruction 2 Instruction 1
Instruction 3 Instruction 3
Instruction 3

Draw a well abled diagram to show the main memory CPU and the following registers: memory address
register, memory data register, current instruction register, and program counter, which show the fetch
decode execute cycle
ALU
CU Accumulator
PC
Main memory CPU
CIR

MAR
MDR

The fetch decode execute cycle

start

Fetch the next instruction

Decode instruction

yes

Execute instruction

Any more
instructions in the

no
stop
Buses connecting the processor to memory

PC MBR

CIR
MAIM

SR MEMORY

MAR

Von Nuemann and Harvard Architecture diagram

Von Nuemann Architecture

Address bus

memory CPU

Data bus

I/O Ports

Harvard
Instruction bus

Instruction CPU
memory
Instruction bus

Address bus
Data memory

Data bus

RISC processor 5 stages of fatch, decord and execute cycle

TIME INTERVAL
Stage
1 2 3 4 5 6 7 8 9
Fetch instruction
Decode instruction

Execute instruction
Access operand in memory
Write results to register

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