TEAM TENT DISCUSSION GROUP
ELE3103: APPLIED DIGITAL ELECTRONICS
DACS AND ADCS
Question 1
a) Consider a 6-bit DAC that produces an analog voltage output of 1.2 V
when the input is 100100. Answer these questions:
i) Find the percentage resolution of the DAC.
𝑉𝑂𝑈𝑇 1.2
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 𝐾 = = = 33.33 𝑚𝑉
𝑑𝑖𝑔𝑖𝑡𝑎𝑙 𝑖𝑛𝑝𝑢𝑡 36
𝑠𝑡𝑒𝑝 𝑠𝑖𝑧𝑒
%𝑎𝑔𝑒 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = × 100
𝑓. 𝑠 𝑣𝑎𝑙𝑢𝑒
𝑉𝑂𝑈𝑇 (𝑚𝑎𝑥) = (33.33𝑚)(26 − 1) = 2.1 𝑉
33.33𝑚
%𝑎𝑔𝑒 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = × 100 = 𝟏. 𝟓𝟗 %
2.1
Alternatively;
1
%𝑎𝑔𝑒 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = × 100
𝑡𝑜𝑡𝑎𝑙 𝑛𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑡𝑒𝑝𝑠
1
%𝑎𝑔𝑒 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = × 100 = 𝟏. 𝟓𝟗%
26 −1
ii) What is the maximum output of the DAC?
𝑉𝑂𝑈𝑇 (𝑚𝑎𝑥) = (33.33𝑚)(26 − 1) = 𝟐. 𝟏 𝑽
b) Consider a 6-bit DAC whose output is 10 mA when the digital input is
110010
i) Write the expression that relates the percentage resolution of a DAC to
its full-scale output.
𝑠𝑡𝑒𝑝 𝑠𝑖𝑧𝑒
%𝑎𝑔𝑒 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = × 100
𝑓. 𝑠 𝑣𝑎𝑙𝑢𝑒
ii) What is the maximum or full-scale output of this DAC?
𝐼𝑂𝑈𝑇 10𝑚
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 𝐾 = = = 0.2 𝑚𝐴
𝑑𝑖𝑔𝑖𝑡𝑎𝑙 𝑖𝑛𝑝𝑢𝑡 50
𝐼𝑂𝑈𝑇 (𝑚𝑎𝑥) = (0.2𝑚)(26 − 1) = 𝟏𝟐. 𝟔 𝒎𝑨
Question 2
a) Consider a 4-bit R/2R ladder network DAC whose reference voltage is set
at 4 V.
i) Why is the R/2R ladder preferred over DACs that employ binary-
weighted resistors in their hardware circuitry?
ii) Find the resolution and full-scale voltage output of this R/2R ladder
DAC.
𝑉𝑅𝐸𝐹
𝐹𝑟𝑜𝑚; 𝑉𝑂𝑈𝑇 = − ×𝐵
2𝑁
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 𝑤𝑒𝑖𝑔ℎ𝑡 𝑜𝑓 𝑡ℎ𝑒 𝐿𝑆𝐵 𝑎𝑛𝑑 𝑖𝑠 𝑑𝑒𝑡𝑒𝑟𝑚𝑖𝑛𝑒𝑑 𝑏𝑦 𝑠𝑒𝑡𝑡𝑖𝑛𝑔 𝐵 = 00012 = 110
𝑉𝑅𝐸𝐹 4
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = − × (1) = − ( ) (1) = −0.25 𝑉
2𝑁 16
𝑉𝑂𝑈𝑇 (𝑚𝑎𝑥) = (−0.25)(24 − 1) = −𝟑. 𝟕𝟓 𝑽
Alternatively;
This can also be determined by setting 𝐵 = 11112 = 1510
𝑉𝑅𝐸𝐹 4
𝑉𝑂𝑈𝑇 (𝑚𝑎𝑥) = − 𝑁
× (15) = − (15) = −𝟑. 𝟕𝟓 𝑽
2 16
b) Consider a 5-bit DAC that works by generating an analog current output
that is proportional to the binary input. If the reference voltage is 10 V and
the resistance associated with the second LSB is 20 𝑘Ω, answer the
following:
i) Find the resolution of the DAC.
20
𝑅= = 2.5 𝑘Ω
8
𝑉𝑅𝐸𝐹 10
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = 𝑤𝑒𝑖𝑔ℎ𝑡 𝑜𝑓 𝑡ℎ𝑒 𝐿𝑆𝐵 = = = 𝟎. 𝟐𝟓 𝒎𝑨
16𝑅 40𝑘
ii) Find the F.S output of the DAC
𝐼𝑂𝑈𝑇 (𝑚𝑎𝑥) = (0.25 𝑚𝐴)(25 − 1) = 𝟕. 𝟕𝟓 𝒎𝑨
iii) If the resistance associated with the MSB is used to design an R/2R
ladder DAC, what is its resolution and F.S voltage output of this R/2R
ladder?
10
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = − ( ) (1) = −𝟎. 𝟑𝟏𝟐𝟓 𝑽
32
10
𝑉𝑂𝑈𝑇 (𝑚𝑎𝑥) = − (31) = −𝟗. 𝟕 𝑽
32
Question 3
a) Consider a computer that is controlling a heater/ cooler actuation system
to maintain the temperature inside a reaction chamber between
−10℃ 𝑎𝑛𝑑 50℃
i) What is the minimum number of bits that the DAC should have if the
computer is to produce a temperature that is within 0.5℃ of the desired
temperature.
Within a temperature of ≤ 0.5℃ means that the maximum possible step size
(resolution) will be 0.5℃
The full-scale value 𝐴𝑓𝑠 = (50 − −10) = 60℃
60
𝑇𝑜 𝑟𝑒𝑎𝑐ℎ 𝑓. 𝑠 𝑣𝑎𝑙𝑢𝑒, = 120 𝑠𝑡𝑒𝑝𝑠 𝑎𝑟𝑒 𝑛𝑒𝑒𝑑𝑒𝑑.
0.5
2𝑛 − 1 ≥ 120
2𝑛 ≥ 121
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 log10 . 𝑜𝑛 𝑏𝑜𝑡ℎ 𝑠𝑖𝑑𝑒𝑠; 𝑛 ≥ 6.92
𝒏 = 𝟕 𝒃𝒊𝒕𝒔
ii) How close to 45.3℃ can the temperature be adjusted?
60
𝑊𝑖𝑡ℎ 7 𝑏𝑖𝑡𝑠, 𝑡ℎ𝑒 𝑎𝑐𝑡𝑢𝑎𝑡𝑖𝑜𝑛 𝑠𝑦𝑠𝑡𝑒𝑚 𝑤𝑖𝑙𝑙 ℎ𝑎𝑣𝑒 𝑎 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛, = = 0.472 ℃/𝑠𝑡𝑒𝑝
27 − 1
45.3 + 10
𝑇ℎ𝑒 𝑎𝑐𝑡𝑢𝑎𝑡𝑖𝑜𝑛 𝑠𝑦𝑠𝑡𝑒𝑚 𝑤𝑖𝑙𝑙 𝑔𝑜 𝑡ℎ𝑟𝑜𝑢𝑔ℎ = = 117.161
0.472
𝑰𝒏𝒗𝒆𝒔𝒕𝒊𝒈𝒂𝒕𝒊𝒏𝒈 𝒇𝒐𝒓 𝒄𝒍𝒐𝒔𝒆𝒏𝒆𝒔𝒔; 117(0.472) = 55.224 𝑎𝑛𝑑 118(0.472) = 55.696
𝑇ℎ𝑒 𝑎𝑐𝑡𝑢𝑎𝑡𝑖𝑜𝑛 𝑠𝑦𝑠𝑡𝑒𝑚 𝑤𝑖𝑙𝑙 𝑔𝑜 𝑡ℎ𝑟𝑜𝑢𝑔ℎ 𝟏𝟏𝟕 𝒔𝒕𝒆𝒑𝒔 𝒕𝒐 𝒊𝒏𝒄𝒓𝒆𝒂𝒔𝒆 𝒕𝒉𝒆 𝒕𝒆𝒎𝒑𝒆𝒓𝒂𝒕𝒖𝒓𝒆
𝒇𝒓𝒐𝒎 − 𝟏𝟎 ℃ 𝒕𝒐 𝟒𝟓. 𝟑 ℃
b) A computer is controlling the pressure in a gas chamber. The current
output of the DAC is converted into pressure that ranges from 0 (zero) to
a maximum value of 1800 Pa.
i) What is the minimum size of the DAC should be used so that the
produced pressure is within 3 Pa of the desired (targeted) pressure
value?
Within a pressure of ≤ 3 𝑝𝑎 means that the maximum possible step size (resolution)
will be 3 𝑝𝑎
The full-scale value 𝐴𝑓𝑠 = (1800— 0) = 1800 𝑃𝑎
1800
𝑇𝑜 𝑟𝑒𝑎𝑐ℎ 𝑓. 𝑠 𝑣𝑎𝑙𝑢𝑒, = 600 𝑠𝑡𝑒𝑝𝑠 𝑎𝑟𝑒 𝑛𝑒𝑒𝑑𝑒𝑑.
3
2𝑛 − 1 ≥ 600
2𝑛 ≥ 601
𝐴𝑝𝑝𝑙𝑦𝑖𝑛𝑔 log10 . 𝑜𝑛 𝑏𝑜𝑡ℎ 𝑠𝑖𝑑𝑒𝑠; 𝑛 ≥ 9.231
𝒏 = 𝟏𝟎 𝒃𝒊𝒕𝒔
ii) Using this DAC, how close can the pressure be adjusted to 924 Pa
1800
𝑊𝑖𝑡ℎ 10 𝑏𝑖𝑡𝑠, 𝑡ℎ𝑒 𝑔𝑎𝑠 𝑐ℎ𝑎𝑚𝑏𝑒𝑟 ℎ𝑎𝑣𝑒 𝑎 𝑟𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛, = = 1.7595 ℃/𝑠𝑡𝑒𝑝
210 − 1
924
𝑇ℎ𝑒 𝑔𝑎𝑠 𝑐ℎ𝑎𝑚𝑏𝑒𝑟 𝑤𝑖𝑙𝑙 𝑔𝑜 𝑡ℎ𝑟𝑜𝑢𝑔ℎ = = 525.149
1.7595
𝑰𝒏𝒗𝒆𝒔𝒕𝒊𝒈𝒂𝒕𝒊𝒏𝒈 𝒇𝒐𝒓 𝒄𝒍𝒐𝒔𝒆𝒏𝒆𝒔𝒔; 525(1.7595) = 923.74 𝑎𝑛𝑑 526(1.7595) = 925.50
𝐻𝑒𝑛𝑐𝑒 𝑡ℎ𝑒 𝑐ℎ𝑎𝑚𝑏𝑒𝑟 𝑤𝑖𝑙𝑙 𝑔𝑜 𝑡ℎ𝑟𝑜𝑢𝑔ℎ 𝟓𝟐𝟓 𝒔𝒕𝒆𝒑𝒔
Question 4
The figure below shows a 4-bit DAC with inputs A, B, C and D and the op amp
is a summing amplifier.
i) Find the appropriate values of resistors 𝑅𝑑 , 𝑅𝑐 𝑎𝑛𝑑 𝑅𝑏 given that 𝑅𝑎 = 8𝑘Ω
𝑅𝑏 = 0.5𝑅𝑎 = 4 𝑘Ω
𝑅𝑐 = 0.25𝑅𝑎 = 2 𝑘Ω
𝑅𝑑 = 0.125𝑅𝑎 = 1 𝑘Ω
ii) Construct a truth table showing only the DCBA entries for 0000, 0001,
0100, 1000 and 1111 and their corresponding 𝑉𝑂𝑈𝑇 given that the input
voltage is 0 or 5 V.
𝑉𝐷 𝑉𝐶 𝑉𝐵 𝑉𝐴
𝐹𝑟𝑜𝑚, 𝑉𝑂𝑈𝑇 = −𝑅𝑓 [ + + + ]
𝑅𝑑 𝑅𝑐 𝑅𝑏 𝑅𝑎
D C B A VOUT (V)
0 0 0 0 0.000
0 0 0 1 -0.625
0 1 0 0 -2.500
1 0 0 0 -5.000
1 1 1 1 -9.375
iii) Determine a new value of 𝑅𝑓 that gives a step size of 0.5 𝑉. How is the
percentage resolution of the DAC affected?
𝑉𝐴
𝑇ℎ𝑒 𝑠𝑡𝑒𝑝 𝑠𝑖𝑧𝑒 𝑐𝑜𝑟𝑟𝑒𝑠𝑝𝑜𝑛𝑑𝑠 𝑡𝑜 𝑡ℎ𝑒 𝐿𝑆𝐵 ℎ𝑒𝑛𝑐𝑒; 𝑅𝑓 = 0.5
𝑅𝑎
(0.5)(8𝑘)
𝑅𝑓 = = 𝟖𝟎𝟎 𝛀
5
𝑻𝒉𝒆 𝒑𝒆𝒓𝒄𝒆𝒏𝒕𝒂𝒈𝒆 𝒓𝒆𝒔𝒐𝒍𝒖𝒕𝒊𝒐𝒏 𝒐𝒇 𝒕𝒉𝒆 𝑫𝑨𝑪 𝒓𝒆𝒎𝒂𝒊𝒏𝒔 𝒄𝒐𝒏𝒔𝒕𝒂𝒏𝒕 𝒔𝒊𝒏𝒄𝒆 𝒕𝒉𝒆 𝒏𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝒃𝒊𝒕𝒔
𝒂𝒓𝒆 𝒖𝒏𝒂𝒇𝒇𝒆𝒄𝒕𝒆𝒅.
Question 5
a) If input A into the DAC below is open, construct a truth table and draw
the DAC output staircase wave form. Using a distinguishable color, draw
the stair case wave form on the same graph if A were connected properly.
Truth table
C B A 𝑉𝑂𝑈𝑇 (𝑉)
0 0 1 1
0 0 1 1
0 1 1 3
0 1 1 3
1 0 1 5
1 0 1 5
1 1 1 7
1 1 1 7
b) Consider a 4-bit DAC driven by a counter as shown below. Assume that
DAC inputs are TTL-compatible.
Scenario 1: The DAC acts normally.
Scenario 2: The DAC inputs B and C are floating.
Task: Draw the staircase waveform for both scenarios on the same
diagram. Make sure that they are clearly distinguishable.
Scenario 2 truth table
D C B A 𝑉𝑂𝑈𝑇 (𝑉)
0 1 1 0 6
0 1 1 1 7
0 1 1 0 6
0 1 1 1 7
0 1 1 0 6
0 1 1 1 7
0 1 1 0 6
0 1 1 1 7
1 1 1 0 14
1 1 1 1 15
1 1 1 0 14
1 1 1 1 15
1 1 1 0 14
1 1 1 1 15
1 1 1 0 14
1 1 1 1 15
Stair case for scenario 2
N.B I forgot to draw the one for scenario 1 but you have to draw it also
using a different color such that they are distinguishable
Question 6
A technician connects a 4-bit counter to the DAC and gets the performance in
the figure below;
i) What is the resolution of the DAC.
𝑹𝒆𝒔𝒐𝒍𝒖𝒕𝒊𝒐𝒏 = 𝟏 𝑽
ii) Comment on the performance of the DAC. Explain and give any reason
for the performance.
D C B A 𝐸𝑥𝑝𝑒𝑐𝑡𝑒𝑑 𝑉𝑂𝑈𝑇 (𝑉) 𝐴𝑐𝑡𝑢𝑎𝑙 𝑉𝑂𝑈𝑇 (𝑉)
0 0 0 0 0 0
0 0 0 1 1 2
0 0 1 0 2 1
0 0 1 1 3 3
0 1 0 0 4 4
0 1 0 1 5 6
0 1 1 0 6 5
0 1 1 1 7 7
1 0 0 0 8 8
1 0 0 1 9 10
1 0 1 0 10 9
1 0 1 1 11 11
1 1 0 0 12 12
1 1 0 1 13 14
1 1 1 0 14 13
1 1 1 1 15 15
From the above truth table, whenever the last two least significant bits of the DAC
take on different states, the output voltage goes through two steps, then back to
prior state and then normalizes when they have similar states.
The cause of the malfunction is mainly because the inputs of the two LSBs have
been interchanged with A taking on the input of B and B taking on the input of A.
Question 7
a) Consider a 5-bit DAC whose full-scale is rated 2.48 V. it has an accuracy
specified as ±0.5% F.S and its offset error is ±2 𝑚𝑉. If the offset error has
not been zeroed out, determine which of the measurement values obtained
in the table below is outside the expected range of this DAC. Show your
working so that I can understand how you reach your conclusions.
Input code (EDCBA) Output (V)
00001 0.09
00110 0.4669
01010 0.785
10110 1.7762
11000 1.932
𝑇𝑜𝑡𝑎𝑙 𝑒𝑟𝑟𝑜𝑟 = ±((2.48)(0.5%) + 2𝑚) = ±14.4 𝑚𝑉
2.48
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = = 0.08 𝑉
31
𝑭𝒐𝒓 𝟎𝟎𝟎𝟎𝟏; 0.08 ± 11.4 𝑚𝑉 = [0.0656, 0.0944], ℎ𝑒𝑛𝑐𝑒 0.09 𝑙𝑖𝑒𝑠 𝑤𝑖𝑡ℎ𝑖𝑛 𝑡ℎ𝑒
𝑠𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑠
𝑭𝒐𝒓 𝟎𝟎𝟏𝟏𝟎; 6 × 0.08 ± 11.4 𝑚𝑉 = [0.4656, 0.4944], ℎ𝑒𝑛𝑐𝑒 0.4669 𝑙𝑖𝑒𝑠 𝑤𝑖𝑡ℎ𝑖𝑛 𝑡ℎ𝑒
𝑠𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑠.
𝑭𝒐𝒓 𝟎𝟏𝟎𝟏𝟎; 10 × 0.08 ± 11.4 𝑚𝑉 = [0.7856, 0.8144], ℎ𝑒𝑛𝑐𝑒 0.875 𝑑𝑜𝑒𝑠 𝑛𝑜𝑡 𝑙𝑖𝑒 𝑤𝑖𝑡ℎ𝑖𝑛 𝑡ℎ𝑒
𝑠𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑠
𝑭𝒐𝒓 𝟏𝟎𝟏𝟏𝟎; 22 × 0.08 ± 11.4 𝑚𝑉 = [1.7456, 1.7744], ℎ𝑒𝑛𝑐𝑒 1.7762 𝑑𝑜𝑒𝑠 𝑛𝑜𝑡 𝑙𝑖𝑒 𝑤𝑖𝑡ℎ𝑖𝑛
𝑡ℎ𝑒 𝑠𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑠
𝑭𝒐𝒓 𝟎𝟎𝟎𝟎𝟏; 24 × 0.08 ± 11.4 𝑚𝑉 = [1.9056, 1.9344], ℎ𝑒𝑛𝑐𝑒 1.932 𝑙𝑖𝑒𝑠 𝑤𝑖𝑡ℎ𝑖𝑛 𝑡ℎ𝑒
𝑠𝑝𝑒𝑐𝑖𝑓𝑖𝑐𝑎𝑡𝑖𝑜𝑛𝑠.
b) A 4-bit DAC has the following specifications: F.S of 0.3 V and accuracy of
±1% 𝐹. 𝑆 a static measurement on the DAC returns measurements in table
below what has caused the malfunction? Show all your working so that I
can understand how you reached your conclusions.
Input code (DCBA) Output (V)
0000 0.078
0001 0.101
0010 0.121
0100 0.0825
1000 0.238
𝑇𝑜𝑡𝑎𝑙 𝑒𝑟𝑟𝑜𝑟 = ±((0.3)(1%) + 2𝑚) = ±3 𝑚𝑉
0.3
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = = 0.02 𝑉
15
𝐹𝑜𝑟 0000, 𝑒𝑥𝑝𝑒𝑐𝑡𝑒𝑑 𝑜𝑢𝑡𝑝𝑢𝑡 = 0.02(0) ± 3𝑚 = ±3𝑚𝑉
𝐹𝑜𝑟 0001, 𝑒𝑥𝑝𝑒𝑐𝑡𝑒𝑑 𝑜𝑢𝑡𝑝𝑢𝑡 = 0.02(1) ± 3𝑚 = [0.017,0.023] 𝑉
𝐴𝑐𝑡𝑢𝑎𝑙 𝑜𝑢𝑡𝑝𝑢𝑡 = 0.023 + 0.078 = 0.101 𝑎𝑛𝑑 𝑑𝑜𝑒𝑠 𝑛𝑜𝑡 𝑙𝑖𝑒 𝑤𝑖𝑡ℎ𝑖𝑛 𝑡ℎ𝑒 𝑟𝑎𝑛𝑔𝑒
𝐹𝑜𝑟 0010, 𝑒𝑥𝑝𝑒𝑐𝑡𝑒𝑑 𝑜𝑢𝑡𝑝𝑢𝑡 = 0.02(2) ± 3𝑚 = [0.037,0.043] 𝑉
𝑎𝑐𝑡𝑢𝑎𝑙 𝑜𝑢𝑡𝑝𝑢𝑡 = 0.043 + 0.078 = 0.121 𝑎𝑛𝑑 𝑑𝑜𝑒𝑠 𝑛𝑜𝑡 𝑙𝑖𝑒 𝑤𝑖𝑡ℎ𝑖𝑛 𝑡ℎ𝑒 𝑟𝑎𝑛𝑔𝑒
𝐹𝑜𝑟 0100, 𝑒𝑥𝑝𝑒𝑐𝑡𝑒𝑑 𝑜𝑢𝑡𝑝𝑢𝑡 = 0.02(4) ± 3𝑚 = [0.077,0.083] 𝑉
𝑎𝑛𝑑 𝑖𝑡 𝑙𝑖𝑒𝑠 𝑤𝑖𝑡ℎ𝑖𝑛 𝑡ℎ𝑒 𝑟𝑎𝑛𝑔𝑒
From the above working, it can be concluded that input C is held HIGH
always the reason its weight keeps adding its self but looking the case
when 𝑫𝑪𝑩𝑨 = 𝟎𝟏𝟎𝟎, there is no additional value meaning that it takes on
its actual weight.
Question 8
a) The wave shown below represents ADC conversion using successive
approximation method (SAC). Given it is a 4-bit ADC.
i) What is the resultant digital output?
Truth table:
time D C B A
𝑡1 1 0 0 0
𝑡2 1 1 0 0
𝑡3 1 0 0 0
𝑡4 1 0 1 0
𝑡5 1 0 1 1
𝑡6 1 0 1 0
The digital output is 1010
ii) what is the resolution and F.S output of the ADC?
𝟖
𝑹𝒆𝒔𝒐𝒍𝒖𝒕𝒊𝒐𝒏 = =𝟏𝑽
𝟖
𝑉𝑂𝑈𝑇 (𝑚𝑎𝑥) = (15)(1) = 15 𝑉.
iii) If the ADC utilizes a 50 kHz clock, what is the conversion time for an
input of 6.5 V.
1
𝐹𝑜𝑟 𝑎𝑛 𝐴𝐷𝐶 𝑆𝐴𝐶; 𝑡𝑐𝑜𝑛𝑣 = 𝑁 × 𝑐𝑙𝑜𝑐𝑘 𝑐𝑦𝑐𝑙𝑒 = 4 ( ) = 𝟖𝟎 𝝁𝒔
50𝑘
b) The wave shown below represents ADC conversion using successive
approximation method (SAC). Given it is a 6-bit ADC.
i) What is the resultant digital output?
time F E D C B A
𝑡0 1 0 0 0 0 0
𝑡1 1 1 0 0 0 0
𝑡2 1 0 1 0 0 0
𝑡3 1 0 0 1 0 0
𝑡4 1 0 0 1 1 0
𝑡5 1 0 0 1 0 1
The digital output is 100101
ii) What is the resolution and F.S output of the ADC?
1.28
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = = 0.04 𝑉
32
𝑉𝑂𝑈𝑇 (𝑚𝑎𝑥) = (63)(0.04) = 2.52 𝑉
Question 9
1
a) A 9-bit ADC has a full-scale voltage of 5.12 V. Its specified error is ± 4 𝐿𝑆𝐵.
What is the maximum possible error in any measurement?
5.12
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = = 10.02 𝑚𝑉
511
𝑄𝑢𝑎𝑛𝑡𝑖𝑧𝑎𝑡𝑖𝑜𝑛 𝑒𝑟𝑟𝑜𝑟 = 10.02 𝑚𝑉 𝑇𝐻𝑂𝑈𝐺𝐻 𝑇𝐻𝐼𝑆 𝑀𝐴𝑌 𝑁𝑂𝑇 𝐵𝐸 𝐴𝐵𝑆𝑂𝐿𝑈𝑇𝐸𝐿𝑌 𝐶𝑂𝑅𝑅𝐸𝐶𝑇
𝑆𝑝𝑒𝑐𝑖𝑓𝑖𝑒𝑑 𝑒𝑟𝑟𝑜𝑟 = 0.25(10.02 𝑚) = 2.505 𝑚𝑉
𝑇𝑜𝑡𝑎𝑙 𝑒𝑟𝑟𝑜𝑟 = 10.02 + 2.505 = 𝟏𝟐. 𝟓𝟐𝟓 𝒎𝑽
b) Consider an 8-bit counter-type ADC with clock frequency of 2MHz, 𝑉T =
0.2 mV, and a FS output of 2.56 V.
i) Find the digital output for an input of 1.86 V.
2.56
𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛 = = 10.04 𝑚𝑉
255
(1.8602)
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑡𝑒𝑝𝑠 = = 185.28 = 186 𝑠𝑡𝑒𝑝𝑠
10.04 𝑚
𝐷𝑖𝑔𝑖𝑡𝑎𝑙 𝑒𝑞𝑢𝑖𝑣𝑎𝑙𝑒𝑛𝑡 = 𝟏𝟎𝟏𝟏𝟏𝟎𝟏𝟎
N.B: approximating the resolution to 10 mV will result into 187 steps
instead, yet the more accurate is supposed to be 186
ii) Find the conversion time of the ADC
𝟏
𝒕𝒄𝒐𝒏𝒗 = 𝟏𝟖𝟔 × = 𝟗𝟑 𝝁𝐬
𝟐𝑴𝑯𝒛
c) Consider an 8-bit digital-ramp ADC with 40 𝑚𝑉 resolution which uses a
clock of frequency 2.5 𝑀𝐻𝑧 and a comparator with 𝑉𝑇 = 1 𝑚𝑉. Determine
the following:
i) The digital output when input voltage is 𝑉𝐴 = 6 𝑉.
(6.001)
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑠𝑡𝑒𝑝𝑠 == = 150.025 = 151 𝑠𝑡𝑒𝑝𝑠
40 𝑚
𝐷𝑖𝑔𝑖𝑡𝑎𝑙 𝑒𝑞𝑢𝑖𝑣𝑎𝑙𝑒𝑛𝑡 = 𝟏𝟎𝟎𝟏𝟎𝟏𝟏𝟏
ii) The maximum and average conversion times of the ADC.
𝑡𝑐𝑜𝑛𝑣 (𝑚𝑎𝑥) = (2𝑁 − 1). 𝑝𝑒𝑟𝑖𝑜𝑑 = (28 − 1)(0.4𝜇) = 𝟏𝟎𝟐 𝝁𝒔
𝑡𝑐𝑜𝑛𝑣 (𝑚𝑎𝑥) 102 𝜇𝑠
𝑡𝑐𝑜𝑛𝑣 (𝑎𝑣𝑔) = = = 𝟓𝟏𝝁𝒔
2 2
𝑵. 𝑩: 𝒊𝒇 𝒕𝒉𝒆 𝒒𝒖𝒆𝒔𝒕𝒊𝒐𝒏 𝒔𝒊𝒎𝒑𝒍𝒚 𝒘𝒂𝒏𝒕𝒔 𝒚𝒐𝒖 𝒕𝒐 𝒅𝒆𝒕𝒆𝒓𝒎𝒊𝒏𝒆 𝒕𝒉𝒆 𝒄𝒐𝒏𝒗𝒆𝒓𝒔𝒊𝒐𝒏 𝒕𝒊𝒎𝒆 𝒐𝒇 𝒕𝒉𝒆 𝑫𝑨𝑪, 𝒚𝒐𝒖 𝒖𝒔𝒆
𝒕𝒉𝒆 𝒅𝒊𝒈𝒊𝒕𝒂𝒍 𝒆𝒒𝒖𝒊𝒗𝒂𝒍𝒆𝒏𝒕 𝒊𝒏 𝒕𝒉𝒆 𝒑𝒓𝒆𝒗𝒊𝒐𝒖𝒔 𝒑𝒂𝒓𝒕 ( 𝒏𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝒔𝒕𝒆𝒑𝒔) 𝒊𝒏 𝒕𝒉𝒆 𝒑𝒍𝒂𝒄𝒆 𝒐𝒇
𝟐𝑵 − 𝟏
COMPILED BY DAVID
