PART A: DIGITAL CIRCUITS SIMULATION LAB

LIST OF EXPERIMENTS:
1. Design a simple combinational circuit with four variables and obtain minimal expression
and verify the truth table using Digital Trainer Kit.
2. Verification of functional table of 3 to 8-line Decoder /De-multiplexer.
3. 4 Variable logic function verification using 8 to1 multiplexer.
4. Design full adder circuit and verify its functional table.
5. Design a four-bit ring counter using D Flip–Flops/JK Flip Flop and verify output
6. Design a four bit Johnson’s counter using D Flip-Flops/JK Flip Flops and verify output
7. Verify the operation of 4-bit Universal Shift Register for different Modes of operation.
8. Draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-Flip-
Flops and Test It with a low frequency clock and sketch the output waveforms.
9. Design MOD–8 synchronous counter using T Flip-Flop and verify the result and sketch
the output waveforms.
10. (a) Draw the circuit diagram of a single bit comparator and test the output
(b) Construct 7 Segment Display Circuit Using Decoder and7 Segment LED and test it.

11. Design Binary to Gray and Gray to Binary conversion using gates
 Getting Started With SYNAPTICAD Tool for
VERILOG Programming
 Choose Start > SynaptiCAD > TestBencher Pro menu to launch the simulator with the graphical debugger.

 create a file called Filename by choosing the Editor > New HDL File menu option to

 open an editor window.

 Type in your source code and save the file.

 Then add the file to the project by right clicking on the User Source Files Folder and choosing

Add HDL Files to Source File Folder from the context menu.

 First, build the project by pressing the yellow Build button on the simulation button bar or

selecting the Simulate > Build menu.

 Building the project compiles the source files.

 After the build you are also able to set the top-level component for the project and/or select

additional signals to watch using the project tree context menus.

 Watch signals are those listed in the Waveform Diagram Window.

 Check the Report window to find any syntax errors found by the build.

 Next, start the simulator by pressing one of the green buttons on the Build and Simulate button bar.

 The simulated signals should appear in the Waveform window

 The Testbench Results should appear Report Window > Verilog.log

DCD LABORATORY II B.Tech I Sem

EXP NO : 1 DATE:

AIM:- Design a simple combinational circuit with four variables and obtain minimal expression
and verify the truth table

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

Example:

Function = Sum of Product (SOP) Y = ∑m (2,3,6,7,8,10,13,15)

SELECTI
ON OUTPUTS
LINES

A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

SOP realization Diagram

Solution:-

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DCD LABORATORY II B.Tech I Sem

Explanation
The simplification of the function is done as per the following steps −
There are no isolated 1s in the K-Map.
The minterm m2 can form a 4-square with m3, m6, and m7. Make it and read it as −
A’C
The minterm m8 can form a 2-square with m10. Make it and read it as −
ABD’
The minterm m13 can form a 2-square with m15. Make it and read it as −
(AB’D)
Write all the product in SOP form.
So the simplified SOP expression is,
f(A,B,C,D)=A’C+AB’D+ABD’

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 DCD LABORATORY II B.Tech I Sem

Verilog Program:

module sop4(out,A,B,C,D);
output out;
input A,B,C,D;
wire abar,bbar,cbar,dbar,p1,p2,p3,p4;
not(abar,A);
not(bbar,B);
not(cbar,C);
not(dbar,D);
and(p1,abar,cbar,dbar);
and(p2,abar,bbar,D);
and(p3,A,bbar,cbar);
and(p4,A,B,C,D);
or(out,p1,p2,p3,p4);
endmodule

RESULT:

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DCD LABORATORY II B.Tech I Sem

EXP. NO: 2 DATE:

3 TO 8-LINE DECODER /DE-MULTIPLEXER

AIM:-Verification of functional table of 3 to 8-line Decoder /De-multiplexer.

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

DECODER:

A decoder is a device which does the reverse operation of an encoder, undoing the
encoding so that the original information can be retrieved. The same methodused to encode
is usually just reversed in order to decode. It is a combinational circuit thatconverts binary
information from n input lines to a maximum of 2n unique output lines. Indigital
electronics, a decoder can take the form of a multiple-input, multiple-output logiccircuit
that converts coded inputs into coded outputs, where the input and output codes are
different. e.g. n-to- 2n, binary-coded decimal decoders. Enable inputs must be on for the
decoder to function, otherwise its outputs assume a single "disabled" output code word. In
case of decoding all combinations of three bits eight (2 3=8) decoding gates are required.
This type of decoder is called 3-8 decoder because 3 inputs and 8 outputs. For any input
combination decoder outputs are 1.

LOGIC DIAGRAM:

FIG: 3:8 DECODER

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 DCD LABORATORY II B.Tech I Sem

TRUTH TABLE FOR DECODER:

Verilog Program:

module decoder3to8( in,en,y);

input [2:0] in;
input en;
output [7:0] y;
reg [7:0] y;
always @( in or en)
begin
if (en)
begin
y=8'd0;
case (in)
3'b000: y= 8'b0000_0001;
3'b001: y= 8'b0000_0010;
3'b010: y= 8'b0000_0100;
3'b011: y= 8'b0000_1000;
3'b100: y= 8'b0001_0000;
3'b101: y= 8'b0010_0000;
3'b110: y= 8'b0100_0000;
3'b111: y= 8'b1000_0000;
default: y=8'd0;
endcase
end
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DCD LABORATORY II B.Tech I Sem
else
y=8'd0;
end
endmodule

RESULT:

VIVA QUESTIONS:

1. What do you understand by decoder?

2. What is demultiplexer?

3. What do you understand by encoder?

4. What is the main difference between decoder and demultiplexer?

5. Why Binary is different from Gray code?

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DCD LABORATORY II B.Tech I Sem

EXP NO: 3 DATE:

Design 8:1 MULTIPLEXER using 4 variable Function
AIM: Design a 8 to 1 multiplexer by using the 4 variable function given by F(A, B, C, D) =
∑ (0,1,3,4,8,9,15).

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

Design of 8 to 1 Multiplexer: It is a four-variable function and thus we require a multiplexer along with three
selection lines and 8 inputs. We select to apply variables B, C, and D for the selection lines. It is shown in
Table no.1. The first half of given minterms are associated with A' and the second half with A. Through
circling the minterms of the function and applying the rules for determine values for the multiplexer inputs,
the implementation represented in Table no.2.

The specified function can be implemented along with a 8-to-1 multiplexer as represented in fig.(a). 3 of the
variables as B, C and D are applied to the selection lines in order that is B is connected to s2, C to s1 and D to
s0. Hence the inputs of the multiplexer are 0, 1, A and A'. As BCD = 000,001 and 111 output F = 1 because
I0 and I8 = 1 for BCD(000), I1 = 1and I9 =1 correspondingly. Thus, minterms m0 = A' B' C' m1 = A' B' C,
m8 = A', B', C' and m9 = A' B' C generate a 1 output. While BCD = 010, 101 and 110, output F = 0, as I2, I5
and I6 respectively are equivalent to 0.

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DCD LABORATORY II B.Tech I Sem

Minterm A B C D F

0 0 0 0 0 1

1 0 0 0 1 1

2 0 0 1 0 0

3 0 0 1 1 1

4 0 1 0 0 1

5 0 1 0 1 0

6 0 1 1 0 0

7 0 1 1 1 0

8 1 0 0 0 1

9 1 0 0 1 1

10 1 0 1 0 0

11 1 0 1 1 0

12 1 1 0 0 0

13 1 1 0 1 0

14 1 1 1 0 0

15 1 1 1 1 1

Table no.1 Truth Table for 8-1 Multiplexer

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 DCD LABORATORY II B.Tech I Sem

Table no.2 Implementation Table for 8 to 1 MUX

Fig.(a) Logic circuit for 8-to-1 Multiplexer

Verilog Program:
module m81(out,A,B,C,D);
output out;
input A,B,C,D;
wire D0,D1,D2,D3,D4,D5,D6,D7,S2bar,S1bar,S0bar,Abar;
assign S2bar=~B;
assign S1bar=~C;
assign S0bar=~D;
assign Abar=~A;
assign D0=1;
assign D1=1;
assign D2=0;
assign D3=Abar;
assign D4=Abar;
assign D5= 0;
assign D6=0;
assign D7=A;
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 DCD LABORATORY II B.Tech I Sem

assign out = (D0 & S2bar & S1bar & S0bar) | (D1 & S2bar & S1bar & D) | (D2 & S2bar & C & S0bar) | (D3 & S2bar
& C & D) | (D4 & B & S1bar & S0bar) | (D5 & B & S1bar & D) | (D6 & B & C & S0bar) | (D7 & B & C & D);

RESULT :

VIVA QUESTIONS:

1. What is a multiplexer?

2. What are the applications of multiplexer and de-multiplexer?

3. What is a de-multiplexer?

4. In 2n to 1 multiplexer how many selection lines are there?

5. Implement an 8:1 mux using 4:1 muxes?

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DCD LABORATORY II B.Tech I Sem

Exp No: 4 Date:

FULL ADDER

AIM: To verify the truth tables of Full Adder.

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

Full adder
A Full adder is a combinational circuit that performs addition of three input bits. Half adder
has inputs X, Y, Z and outputs sum (S) and carry(C). The truth table is

a b cin Sum Carry

(S) (C)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 DCD LABORATORY II B.Tech I Sem

The logic circuit to implement is as shown below

Verilog Program

module full_adder_d (a,b,cin,sum,carry);

input a,b,cin;
output sum,carry;
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (b & cin) | (cin & a) ;
endmodule

module tb_top;
reg a, b, cin;
wire sum, carry;
full_adder_d fa(a, b, cin, sum, carry);
initial
begin
$monitor("At time %0t: a=%b b=%b, cin=%b, sum=%b, carry=%b",$time,a,b,cin,sum,carry);
a = 0; b = 0; cin = 0; #1;
a = 0; b = 0; cin = 1; #1;
a = 0; b = 1; cin = 0; #1;
a = 0; b = 1; cin = 1; #1;
a = 1; b = 0; cin = 0; #1;
a = 1; b = 0; cin = 1; #1;
a = 1; b = 1; cin = 0; #1;
a = 1; b = 1; cin = 1;
end
endmodule

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DCD LABORATORY II B.Tech I Sem

RESULT:

VIVA QUESTIONS:

1. What is use of Full adder?

2. What is difference between the half and full adder?

3. How many half adders required to make a full adder?

4. In full adder how many types of gates are required?

5. Draw full adder circuit?

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DCD LABORATORY II B.Tech I Sem

Exp No: 5 Date:

RING COUNTER

AIM: Design a four-bit ring counter using D Flip–Flops/JK Flip Flop.

APPARATUS REQUIRED:

Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

Ring counter and Johnson counters are basically shift registers Ring

Ring counter:

It is made by connecting Q&Q‟ output of one JK FF to J&K input of next FF respectively.

The output of final FF is connected to the input of first FF. To start the counterthe first
FF is set by using preset facility and the remaining FF are reset input. When the clock arrives
the set condition continues to shift around the ring ,

As it can be seen from the truth table there are four unique output stages for this counter. The
modulus value of a ring counter is n, where n is the number of flip flops. Ring
counter iscalled divided by N counter where N is the number of FF

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 DCD LABORATORY II B.Tech I Sem

Verilog Program:

module ring_count(q,clk,clr);
input clk,clr;
output [3:0]q;
reg [3:0]q;
always @(posedge clk) if(clr==1)
q<=4'b1000;
else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule

`timescale 1ns/1ps
module ring_count_test();
reg clk_tb,clr_tb;
wire [3:0]q_tb;
ring_count dut1(q_tb,clk_tb,clr_tb);
initial
begin clr_tb=1'b0;
#50 clr_tb=1'b1;
#100 clr_tb=1'b0;
#10000 $finish;
end
always
begin
#50 clk_tb=1'b1;
#50 clk_tb=1'b0;
end
initial
begin
$display("time,\t clk_tb,\t clr_tb,\t q_tb");
$monitor("%g,\t %h,\t %h,\t %h",$time,clk_tb,clr_tb,q_tb);
end
endmodule

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DCD LABORATORY II B.Tech I Sem

RESULT:

VIVA QUESTIONS:

1. What do you mean by Counter?

2. What is the ring counter?

3. What are the types of Counters? Explain each

4. Why asynchronous counters are called as ripple counters?

5. What are the applications of asynchronous counters?

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DCD LABORATORY II B.Tech I Sem

Exp No: 6 Date:

JOHNSON’S COUNTER

AIM: Design a four bit Johnson’s counter using D Flip-Flops/JK Flip Flops.

APPARATUS REQUIRED:

Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

Ring counter and Johnson counters are basically shift registers

Johnson counter (Twisted ring counter)

The modulus value of a ring counter can be doubled by making a small change in the ring counter circuit.
The Q‟ and Q of the last FFS are connected to the J and K input of the first FFrespectively. This is the
Johnson counter.

Initially the FFs are reset. After first clock pulse FF0 is set and the remaining FFs are reset.
After the eight clock pulse all the FFS are reset. There are eight different conditions creating a
mode 8 Johnson counter. Johnson counter is called a twisted ring counter or divide by 2N
counter.

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DCD LABORATORY II B.Tech I Sem

LOGIC DIAGRAM:

FIG: JOHNSON COUNTER

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 DCD LABORATORY II B.Tech I Sem

Verilog Program:

module Johnson_Counter( out,reset,clk);

input clk,reset;
output [3:0] out;
reg [3:0] q;
always @(posedge clk)
begin
if(reset)
q<=4'd0;
else
begin
q[3]<=q[2];
q[2]<=q[1];
q[1]<=q[0];
q[0]<=(~q[3]);
end
end
assign out=q;
endmodule

`timescale 1ns/1ps
module Johnson_count_test();
reg clk_tb,reset_tb;
wire [3:0]q_tb;
Johnson_Counter dut1(q_tb,reset_tb,clk_tb);
initial
begin
$display("time,\t clk_tb,\t reset_tb,\t q_tb");
$monitor("%g,\t %h,\t %h,\t %h",$time,clk_tb,reset_tb,q_tb);
reset_tb=1'b0;
#50 reset_tb=1'b1;
#100 reset_tb=1'b0;
#10000 $finish;
end
always
begin
#50 clk_tb=1'b1;
#50 clk_tb=1'b0;
end
endmodule

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DCD LABORATORY II B.Tech I Sem

RESULT:

VIVA QUESTIONS:

1. What is the Johnson counter?

2. What is the difference between the counting sequence of an up counter and a

down counter?

3. What down you mean by down counter?

4. What is the advantage of Ripple counter over Synchronous Counter?

5. What are the applications of the counters?

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DCD LABORATORY II B.Tech I Sem

Exp No: 7 Date:

UNIVERSAL SHIFT REGISTER

AIM: Verify the operation of 4-bit Universal Shift Register for different Modes of operation.

APPARATUS REQUIRED: Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

Shift registers are the sequential logic circuits that can store the data temporarily and provides
the data transfer towards its output device for every clock pulse. These are capable of
transferring/shifting the data either towards the right or left in serial and parallel modes. Based
on the mode of input/output operations, shift registers can be used as a serial-in-parallel-out shift
register, serial-in-serial-out shift register, parallel-in-parallel-out shift register, parallel-in-
parallel-out shift register. Based on shifting the data, there are universal shift registers and
bidirectional shift registers. Here is a complete description of the universal shift register.
What is a Universal Shift Register?
Definition: A register that can store the data and /shifts the data towards the right and left along
with the parallel load capability is known as a universal shift register. It can be used to perform
input/output operations in both serial and parallel modes. Unidirectional shift registers and
bidirectional shift registers are combined together to get the design of the universal shift register.
It is also known as a parallel-in-parallel-out shift register or shift register with the parallel load.
Universal shift registers are capable of performing 3 operations as listed below.
 Parallel load operation – stores the data in parallel as well as the data in parallel
 Shift left operation – stores the data and transfers the data shifting towards left in the
serial path
 Shift right operation – stores the data and transfers the data by shifting towards right in
the serial path.
Hence, Universal shift registers can perform input/output operations with both serial and parallel
loads.
 Serial input for shift-right control enables the data transfer towards the right and all the
serial input and output lines are connected to the shift-right mode. The input is given to
the AND gate-1 of the flip-flop -1 as shown in the figure via serial input pin.
 Serial input for shift-left enables the data transfer towards the left and all the serial input
and output lines are connected to shift-left mode.
 In parallel data transfer, all the parallel inputs and outputs lines are associated with the
parallel load.
 Clear pin clears the register and set to 0.
 CLK pin provides clock pulses to synchronize all the operations.
 In the control state, the information or data in the register would not change even though
the clock pulse is applied.
 If the register operates with a parallel load and shifts the data towards the right and left,
then it acts as a universal shift register.
 From the above figure, selected pins the mode of operation of the universal shift register.
Serial input shifts the data towards the right and left and stores the data within the
register.

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DCD LABORATORY II B.Tech I Sem

FIG: UNIVERSAL SHIFT REGISTER DESIGN

FUNCTION TABLE:

S0 S Mode of Operation
1
0
0 Locked state (No
change)
0
1 Shift-Left
Shift-Right
1 0
Parallel Loading
1 1

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 DCD LABORATORY II B.Tech I Sem

 Clear pin and CLK pin are connected to the flip-flop.

 M0, M1, M2, M3 are the parallel inputs while F0, F1, F2, F3 are the parallel outputs of
flip-flops
 When the input pin is active HIGH, then the universal shift register loads / retrieve the
data in parallel. In this case, the input pin is directly connected to 4×1 MUX
 When the input pin (mode) is active LOW, then the universal shift register shifts the data.
In this case, the input pin is connected to 4×1 MUX via NOT gate.
 When the input pin (mode) is connected to GND (Ground), then the universal shift
register acts as a Bi-directional shift register.
 To perform the shift-right operation, the input pin is fed to the 1st AND gate of the 1st
flip-flop via serial input for shit-right.
 To perform the shift-left operation, the input pin is fed to the 8th AND gate of the last
flip-flop via input M.
 If the selected pins S0= 0 and S1 = 0, then this register doesn’t operate in any mode. That
means it will be in a Locked state or no change state even though the clock pulses are
applied.
 If the selected pins S0 = 0 and S1 = 1, then this register transfers or shifts the data to left
and stores the data.
 If the selected pins S0 = 1 and S1 = 0, then this register shifts the data to right and hence
performs the shift-right operation.
 If the selected pins S0 = 1 and S1 = 1, then this register loads the data in parallel. Hence
it performs the parallel loading operation and stores the data.

Verilog Program:
module universal_shift_reg( clk, rst_n,select,p_din,
left_din,s_right_din,p_dout,s_left_dout,s_right_dout );
input clk, rst_n;
input [1:0] select; // select operation
input [3:0] p_din; // parallel data in
input s_left_din; // serial left data in
input s_right_din; // serial right data in
output [3:0] p_dout; //parallel data out
output s_left_dout; // serial left data out
output s_right_dout; // serial right data out
reg [3:0] p_dout;
always@(posedge clk)
begin
if(!rst_n)
p_dout <= 0;
else
begin
case(select)
2'h1: p_dout <= {s_right_din,p_dout[3:1]}; // Right Shift
2'h2: p_dout <= {p_dout[2:0],s_left_din}; // Left Shift
2'h3: p_dout <= p_din; // Parallel in - Parallel out
default: p_dout <= p_dout; // Do nothing
endcase
end
end

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 DCD LABORATORY II B.Tech I Sem

assign s_left_dout = p_dout[0];

assign s_right_dout = p_dout[3];
endmodule

module TB;
reg clk, rst_n;
reg [1:0] select;
reg [3:0] p_din;
reg s_left_din, s_right_din;
wire [3:0] p_dout; //parallel data out
wire s_left_dout, s_right_dout;
universal_shift_reg usr(clk, rst_n, select, p_din, s_left_din, s_right_din, p_dout,
s_left_dout, s_right_dout);
always #2 clk = ~clk;
initial begin
$monitor("select=%b, p_din=%b, s_left_din=%b, s_right_din=%b --> p_dout = %b,
s_left_dout = %b, s_right_dout = %b",select, p_din, s_left_din, s_right_din, p_dout,
s_left_dout, s_right_dout);
clk = 0; rst_n = 0;
#3 rst_n = 1;
p_din = 4'b1101;
s_left_din = 1'b1;
s_right_din = 1'b0;
select = 2'h3; #10;
select = 2'h1; #20;
p_din = 4'b1101;
select = 2'h3; #10;
select = 2'h2; #20;
select = 2'h0; #20;
$finish;
end
endmodule

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DCD LABORATORY II B.Tech I Sem

RESULT:

VIVA QUESTIONS:

1. What do you mean by shift register?

2. Explain the operation of a left shift register & a right shift register?

3. What is the difference between a register and shift register?

4. What is meant by universal shift register?

5. Explain the various modes in which the data can be entered or taken out from a register?

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DCD LABORATORY II B.Tech I Sem

Exp No: 8 Date:

MOD-8 RIPPLE COUNTER

AIM: Draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-Flip-Flops
and Test It with a low frequency clock and sketch the output waveforms.

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

Asynchronous counter:

A digital counter is a set of flip flop. An Asynchronous counter uses T flip flop to perform a
counting function. The actual hardware used is usually J-K flip-flop connected to logic 1.
In ripple counter, the first flip-flop is clocked by the external clock pulse & then each successive
flip-flop is clocked by the Q or /Q‘ output the previous flip-flop. Therefore in an asynchronous
counter the flip-flop are not clocked simultaneously. The input of MS-JK is connected to VCC
because when both inputs are one output is toggled. As MS-JK is negative edge triggered at each
high to low transition the next flip-flop is triggered. On this basis the design is done for MOD-8
counter.

1) Up Counter:

Fig shows 3 bit Asynchronous Up Counter. Here Flip-flop A act as a MSB Flip-flop and Flip-
flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock of flip-flop C. Output of
Flip-flop C (Qc) is connected to clock of next flip-flop(i.e. Flip-flop B) and so on. As soon as
clock pulse changes output is going to -change(at the negative edge of clock pulse) as a Up count
sequence. For 3 bit Up counter Truth table is as shown below.

2) Down Counter:

Fig shows 3 bit Asynchronous Down Counter. Here Flip-flop a act as a MSB Flip-flop
and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock of flip-flop C.
Output of Flip-flop C (Qc‘) is connected to clock of next flip- flop (i.e. Flip-flop B) and so on.
As soon as clock pulse changes output is going to change(at the negative edge of clock pulse) as
a down count sequence. For 3 bit down counter Truth table is as shown below.

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 DCD LABORATORY II B.Tech I Sem

Truth Table:

Up Counter Down Counter

Counter States F/F Output
Counter States F/F Output
QA QB QC
QA QB QC
7 1 1 1
0 0 0 0
6 1 1 0
1 0 0 1
5 1 0 1
2 0 1 0
4 1 0 1
3 0 1 1
3 0 1 1
4 1 0 0
2 0 1 0
5 1 0 1
1 0 0 1
6 1 1 0
0 0 0 0
7 1 1 1

LOGIC DIAGRAM:

FIG: 3- BIT ASYNCHRONOUS UP COUNTER

FIG: 3- BIT ASYNCHRONOUS DOWN COUNTER

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TIMING DIAGRAM:

1. 3 Bit Asynchronous Up Counter

CLK

Qa
0 0 0 0
3 1 1 1

Qb
0 0 1 1 0 0 1 1

Qc
0 0 0 0 1 1 1 1

2. 3 Bit Asynchronous Down Counter:

CLK

Qc
0 0 0 0
1 1 1 1

Qb
0 1 1 0 0 1 1 0

Qa
0 0 0 0
1 1 1 1

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Verilog Program

module up_counter(clk,reset,counter);
input clk, reset;
output [3:0] counter;
reg [3:0] counter;

// up counter
always @(posedge clk or posedge reset)
begin
if(reset)
counter <= 4'd0;
else
counter <= counter + 4'd1;
end
endmodule

module upcounter_testbench();
reg clk, reset;
wire [3:0] counter;
up_counter dut(clk, reset, counter);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial begin
$display("time,\t clk,\t reset,\t counter");
$monitor("%g,\t %h,\t %h,\t %h",$time,clk,reset,counter);
reset=1;
#20;
reset=0;
#10000 $finish;
end
endmodule

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RESULT:

VIVA QUESTIONS:

1. What do you understand by counter?

2. What is asynchronous counter?

3. What is synchronous counter?

4. Which flip flop is used in asynchronous counter?

5. Which flip flop is used in synchronous counter?

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Exp No: 9 Date:

MOD–8 SYNCHRONOUS COUNTER

AIM: To Design MOD–8 synchronous counter using T Flip-Flop.

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

A counter in which each flip-flop is triggered by the output goes to previous flip-flop.As all
the flip-flops do not change states simultaneously in asynchronous counter, spike occur at the
output. To avoid this, strobe pulse is required. Because of the propagation delay the operating
speed of asynchronous counter is low. This problem can be solved by triggering all the flip-flops
in synchronous with the clock signal and such counters are called synchronous counters.

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MOD 8 COUNTER:

LOGIC DIAGRAM:

FIG: 3 BIT SYNCHRONOUS COUNTER

TRUTH TABLE:

Present count Next count

QC QB QA
0 0 0 QC QB QA QC QB QA
0 0 1 0 0 0 0 0 1
0 1 0 0 0 1 0 1 0
0 1 1 0 1 0 0 1 1
1 0 0 0 1 1 1 0 0
1 0 1 1 0 0 1 0 1
1 1 0 1 0 1 1 1 0
1 1 1 1 1 0 1 1 1
0 0 0 1 1 1 0 0 0

T-FLIPFLOP EXCITATION TABLE:

States Input
Present Next T
0 0 0
0 1 1
1 0 1
1 1 0

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Verilog Program:

module synchronous_counter (clk, rst_n,up,cnt);

input clk, rst_n;
input up;
output [3:0] cnt;
reg [3:0] cnt;
always@(posedge clk)
begin if(!rst_n)
begin
cnt <= 4'h0;
end
else
begin
if(up) cnt <= cnt + 1'b1;
else cnt <= cnt - 1'b1;
end
end
endmodule

module tb;
reg clk, rst_n; reg up;
wire [3:0] cnt;
synchronous_counter dut(clk, rst_n, up, cnt);
initial
begin
$display("time,\t clk,\t rst_n,\t up,\t cnt");
$monitor("%g,\t %h,\t %h,\t %h,\t %h",$time,clk,rst_n,up,cnt);
clk = 0; rst_n = 0;
clk = 0; rst_n = 0;
up = 1;
#4;
rst_n = 1;
#80;
rst_n = 0;
#4;
rst_n = 1;
#4
up = 0;
#1000;
$finish;
end
always #2 clk = ~clk;
endmodule

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RESULT:

VIVA QUESTIONS:

1. What are synchronous counters?

2. What are the advantages of synchronous counters?

3. What is an excitation table?

4. Write the excitation table for D, T FF?

5. Design mod-5 synchronous counter using T FF?

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Exp No:10a Date:

A.SINGLE BIT COMPARATOR

AIM: Draw the circuit diagram of a single bit comparator and test the output.

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:
Magnitude Comparator is a logical circuit, which compares two signals A and B andgenerates
three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high
speed 4-bit Magnitude comparator , which compares two 4-bit words . The A = B Inputmust be
held high for proper compare operation.

Fig: 1- BIT COMPARATOR

INPUTS OUTPUTS
A>B = A B A B A>B A=B A<B
_ 0 0 0 1 0
A<B = A B
0 1 0 0 1 _ _

1 0 1 0 0 A=B = A B +AB
1 1 0 1 0

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Verilog Program:

module b_comp1 (a, b, L, E,G);

input a, b;
output L, E, G;
wire s1, s2;
not (s1, a);
not(s2, b);
and (L,s1, b);
and (G,s2, a);
xnor (E, a, b);
endmodule

RESULT:

VIVA QUESTIONS:

1. What is a comparator?

2. What are the applications of comparator?

3. Derive the Boolean expressions of one bit comparator and two bit comparators.

4. How do you realize a higher magnitude comparator using lower bit comparator

5. Design a 2 bit comparator using a single Logic gates?

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Exp No: 10b Date:

B.7 SEGMENT DISPLAY

AIM: Construct 7 Segment Display Circuit Using Decoder and7 Segment LED and test it.

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

THEORY:

The functions of LT, RBI, RBO and BI are given below. LT This is called the LAMP TEST
terminal and is used for segment testing. If it is connected to logic ‘0’ level, all the segements of
the display connected to the decoder will be ON. For normal decoding operation, this terminal is
to be connected to logic ‘1’ level. RBI For normal decoding operation, this is connected to logic
‘1’ level. If it is connected to logic ‘0’, the segment outputs will generate the data for normal 7-
segment decoding, for all BCD inputs except Zero. Whenever the BCD inputs correspond to
Zero, the 7-segment display switches off. This is used for zero blanking in multi-digit displays.
BI If it is connected to logic ‘0’ level, the display is switched-off irrespective of the BCD inputs.
This is used for conserving the power in multiplexed displays. RBO This output is used for
cascading purposes and is connected to the RBI terminal of the succeeding stage.

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CIRCUIT DIAGRAM:

FIG: SEVEN SEGMENT DISPLAY

TRUTH TABLE :

Display
D C B A a b c d e f g
Number

0 0 0 0 0 0 0 0 0 0 1

0 0 0 1 1 0 0 1 1 1 1

0 0 1 0 0 0 1 0 0 1 0

0 0 1 1 0 0 0 0 1 1 0

0 1 0 0 1 0 0 1 1 0 0

0 1 0 1 0 1 0 0 1 0 0

0 1 1 0 1 1 0 0 0 0 0

0 1 1 1 0 0 0 1 1 1 1

1 0 0 0 0 0 0 0 0 0 0

1 0 0 1 0 0 0 1 1 0 0

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 DCD LABORATORY II B.Tech I Sem

Verilog Program:

module segment7(bcd,seg);
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;

always @(bcd)
begin
case (bcd)
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
default : seg = 7'b1111111;
endcase
end
endmodule

module tb_segment7;
reg [3:0] bcd;
wire [6:0] seg; integer i;

segment7 uut ( .bcd(bcd),.seg(seg));

initial
begin
for(i = 0;i < 16;i = i+1)
begin
bcd = i;
#10;
end
end
initial
begin
$display("time,\t bcd,\t seg");
$monitor("%g,\t %h,\t %h",$time,bcd,seg);
end
endmodule

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DCD LABORATORY II B.Tech I Sem

RESULT:

VIVA QUESTIONS:

1. What are the applications of seven segment display?

2. Can you use the segments outputs of 7448 decoder directly to drive a 7-Segment LED?
If not suggest a suitable interface?

3. Describe the operation performed by the decoder?

4. What is the function of RBI input?

5. What is the difference between common anode & common cathode display?

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 DCD LABORATORY II B.Tech I Sem

Exp No: 11 Date:

11.BINARY TO GRAY AND GRAY TO BINARY CONVERSIONS

AIM: Construct 7 Segment Display Circuit Using Decoder and7 Segment LED and test it.

APPARATUS REQUIRED:
Desktop Computer, Synapticad Tool for Verilog Programming

Binary to Gray conversion :

The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given binary code.
Other bits of the output gray code can be obtained by Ex-ORing binary code bit at that index and previous
index.

There are four inputs and four outputs. The input variable are defined as B3, B2, B1, B0 and the output
variables are defined as G3, G2, G1, G0. From the truth table, combinational circuit is designed.The logical
expressions are defined as :
B3 = G 3

B2 ⊕ B 3 = G 2

B1 ⊕ B 2 = G 1

B0 ⊕B1 =G0

Figure-1: Binary to Gray Code Converter Circuit

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 DCD LABORATORY II B.Tech I Sem

Figure-2: Binary to Gray Code Converter Truth Table

Gray to binary conversion :

The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the given binary number.
Other bits of the output binary code can be obtained by checking gray code bit at that index. If current gray code bit is
0, then copy previous binary code bit, else copy invert of previous binary code bit.

There are four inputs and four outputs. The input variable are defined as G3, G2, G1, G0 and the output variables are
defined as B3, B2, B1, B0. From the truth table, combinational circuit is designed. The logical expressions are defined
as :

G 0 ⊕ G1 ⊕ G2 ⊕ G3 = B 0

G 1 ⊕ G2 ⊕ G3 = B 1

G 2 ⊕ G3 = B 2
G3 =B3

Figure-3: Gray to Binary Code Converter Circuit

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 DCD LABORATORY II B.Tech I Sem

Figure-4: Gray to Binary Code Converter Truth Table

Verilog Program:
module bin2gray (bin,G );
input [3:0] bin;
output [3:0] G;
assign G[3] = bin[3];
assign G[2] = bin[3] ^ bin[2];
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];
endmodule

module gray2bin (G,bin);

input [3:0] G;
output [3:0] bin;
assign bin[3] = G[3];
assign bin[2] = G[3] ^ G[2];
assign bin[1] = G[3] ^ G[2] ^ G[1];
assign bin[0] = G[3] ^ G[2] ^ G[1] ^ G[0];
endmodule

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 DCD LABORATORY II B.Tech I Sem

module tb();

reg [3:0] bin;

wire [3:0] G,bin_out;
bin2gray uut1(bin,G);
gray2bin uut2(G,bin_out);
always
begin
bin <= 0; #10;
bin <= 1;#10;
bin <= 2; #10;
bin <= 3; #10;
bin <= 4; #10;
bin <= 5; #10;
bin <= 6; #10;
bin <= 7; #10;
bin <= 8; #10;
bin <= 9; #10;
bin <= 10; #10;
bin <= 11; #10;
bin <= 12; #10;
bin <= 13; #10;
bin <= 14; #10;
bin <= 15; #10;
#100;
$stop;
end
initial
begin

$display("time,\t bin,\t G,\t bin_out");

$monitor("%g,\t %h,\t %h,\t %h",$time,bin,G,bin_out);
end
endmodule

RESULT:

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