Microprocessors and

Introduction to Microcontroller
(8085, 8086, 8051 - Architecture, Interfacing and Programming)

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 About the Author
A. P. Godse
· Completed M.S in Software Systems with distinction from Birla Institute of Technology.
· Completed B.E. in Industrial Electronics with distinction from University of Pune in 1990.
· Worked as a Professor at Vishwakarma Institute of Technology, Pune.
· Worked as a Technical Director at Noble Institute of Technology, Pune.
· Worked as selection Committee member for M. S. admission for West Virginia University,
Washington D.C.
· Developed Microprocessor Based Instruments in co-ordination with Anna Hazare for
Environmental Studies Laboratory, at Ralegan Siddhi.
· Developed Microprocessor Lab in-house for Vishwakarma Institute of Technology.
· Worked as Subject Expert for a State Level Technical Paper Presentation Competition, Pune.
· Awarded on 26th Jan 2001 by Pune Municipal Corporation for contributing in education field
and technical writing.
· Awarded as a “Parvati Bhushan Puraskar” for contributing in the education field.
· Since 1996, writing books on various engineering subjects. Over the years, many of books are
recommended as the reference books and text books in various national and international
engineering universities.

D. A. Godse
· Completed M.E and pursuing Ph.D. in Computer Engineering from Bharati Vidyapeeth’s
University Pune.
· Completed B.E. in Industrial Electronics from University of Pune in 1992.
· Working as a Professor and Head of Information Technology Department in B.V.C.O.E.W, Pune.
· Subject Expert for syllabus setting of Computer Engineering and Information Technology branches
at the faculty of Engineering of Pune University.
· Subject Expert and Group Leader for syllabus setting of Electronics, Electronics and
Telecommunication and Industrial Electronics branches at the faculty of Maharashtra State, Board
of Technical Education.
· Subject In-charge for Laboratory Manual Development, Technical Teacher’s Training Institute,
Pune.
· Subject In-charge for Question Bank Development Project, Technical Teacher’s Training Institute,
Pune.
· Subject In-charge for the preparation of Teacher’s Guide, Board of Technical Examination,
Maharashtra state.
· Subject Expert for a State Level Technical Paper Presentation Competition organized by Bharati
Vidyapeeth’s Jawaharlal Nehru Institute of Technology, Pune.
· Local Inquiry Committee (LIC) member of Engineering faculty of Pune University.
· Awarded on 15th August 2006 by Pune Municipal Corporation for contributing in education field
and technical writing.
· Awarded on the occasion of International Women’s Day at Yashawantrao Chavan Pratishthan
Sabhagrih, Mumbai by Bharatiya Shikshan Sanstha.
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 ®
Microprocessors and
Introduction to Microcontroller
(8085, 8086, 8051 - Architecture, Interfacing and Programming)
Atul P. Godse
M. S. Software Systems (BITS Pilani)
B.E. Industrial Electronics
Formerly Lecturer in Department of Electronics Engg.
Vishwakarma Institute of Technology
Pune

Mrs. Deepali A. Godse

B.E. Industrial Electronics, M. E. (Computer)
Head of Information Technology Dept.,
Bharati Vidyapeeth's College of Engineering for Women,
Pune

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Microprocessors and
Introduction to Microcontroller
(8085, 8086, 8051 - Architecture, Interfacing and Programming)

ISBN 9789350992609 (Printed Book)

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practical examples and solved problems. All the chapters in the book
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Authors
A. P. Godse
D. A. Godse

Dedicated to God

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 TT able of Contents
Chapter - 1 8085 Processor (1 - 1) to (1 - 22)
1.1 Features ............................................................................................................ 1 - 2
1.2 Architecture of 8085......................................................................................... 1 - 3
1.2.1 Register Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 4

1.2.2 Arithmetic Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 7

1.2.3 Instruction Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 7

1.2.4 Address Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8

1.2.5 Address/Data Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8

1.2.6 Incrementer/Decrementer Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8

1.2.7 Interrupt Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8

1.2.8 Serial I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 8

1.2.9 Timing and Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 9

1.3 Pin Definitions of 8085...................................................................................... 1 - 9
1.3.1 Power Supply and Frequency Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 10

1.3.2 Data Bus and Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 10

1.3.3 Control and Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 10

1.3.4 Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 11

1.3.5 Serial I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 11

1.3.6 DMA Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 11

1.3.7 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 11

1.4 Bus Organization............................................................................................. 1 - 12
1.4.1 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 12

1.4.2 Demultiplexing AD 7 -AD 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 13

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 1.4.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 13

1.4.4 Generation of Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 15

1.4.5 Bus Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 16

1.4.6 Typical Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 18

Review Questions ................................................................................................ 1 - 19
Two Marks Questions with Answers .............................................................. 1 - 20

Chapter - 2 8085 Instruction Set & ALP (2 - 1) to (2 - 68)

2.1 Instruction Classification................................................................................... 2 - 2
2.1.1 Data Transfer Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2

2.1.2 Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2

2.1.3 Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3

2.1.4 Branching Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3

2.1.5 Stack, Input / Output and Machine Control Operations . . . . . . . . . . . . . . . . . . . 2 - 3

2.2 Instruction Set of 8085 ..................................................................................... 2 - 4
2.2.1 Data Transfer Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4

2.2.2 Arithmetic Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 8

2.2.3 Logic Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 14

2.2.4 Rotate Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 19

2.2.5 Stack Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 21

2.2.6 Branch Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 25

2.2.7 Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 29

2.2.8 Machine Control Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 30

2.3 Addressing Modes ......................................................................................... 2 - 31
2.4 Instruction Set Summary ................................................................................ 2 - 33
2.5 Assembly Language Programming.................................................................. 2 - 37
2.5.1 Steps Involved in Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 38

2.5.2 Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 38

2.5.3 Assembly Language Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 39

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 2.5.4 Assembly Language Program to Machine Language Program . . . . . . . . . . . . . 2 - 40

2.5.5 Storing Hex Code in the Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41

2.5.6 Executing the Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 41

2.6 Programming Examples ...................................................................................2 - 42
2.7 Instruction Comparisons..................................................................................2 - 59
2.8 Instruction Formats .........................................................................................2 - 62
Review Questions ..................................................................................................2 - 63
Two Marks Questions with Answers ................................................................2 - 65

Chapter - 3 Looping, Counting, Time Delays and (3 - 1) to (3 - 64)

Code Conversion
3.1 Looping, Counting and Indexing ....................................................................... 3 - 2
3.2 Timers ..............................................................................................................3 - 39
3.2.1 Timer Delay using NOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 39

3.2.2 Timer Delay using Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 39

3.2.3 Timer Delay using Nested Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 41

3.3 Code Conversion..............................................................................................3 - 49
3.3.1 BCD to Binary Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 49

3.3.2 Binary to BCD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 51

3.3.3 BCD to Seven Segment Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 53

3.3.4 Binary to ASCII Code Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 54

3.3.5 ASCII Code to Binary Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 56

3.4 BCD Arithmetic ................................................................................................3 - 57
3.4.1 BCD Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 57

3.4.2 BCD Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 60

Review Questions ..................................................................................................3 - 61
Two Marks Questions with Answers ................................................................3 - 63

Chapter - 4 8085 Interrupts (4 - 1) to (4 - 12)

4.1 Necessity of Interrupts ..................................................................................... 4 - 2

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 4.2 8085 Interrupt Structure and Operation .......................................................... 4 - 4
4.2.1 Types of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4

4.2.2 Overall Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 4

4.2.2.1 Hardware Interrupts in 8085 . . . . . . . . . . . . . . . . . . . . . 4 - 4

4.2.2.2 Software Interrupts in 8085 . . . . . . . . . . . . . . . . . . . . . . 4 - 8

4.2.3 Masking / Unmasking of Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9

4.2.4 Pending Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9

Review Questions ................................................................................................ 4 - 12
Two Marks Questions with Answers .............................................................. 4 - 12

Chapter - 5 8085 Timing Diagrams (5 - 1) to (5 - 62)

5.1 Instruction Cycle, Machine Cycle and T-State ...................................................5 - 2
5.2 Representation of Signals ..................................................................................5 - 3
5.3 Signal Timings ....................................................................................................5 - 5
5.4 8085 Machine Cycles and their Timings ............................................................5 - 8
5.5 Timing Diagrams for 8085 Instructions............................................................5 - 24
Review Questions .................................................................................................5 - 58
Two Marks Questions with Answers ...............................................................5 - 60

Chapter - 6 8086 Processor (6 - 1) to (6 - 32)

6.1 Introduction.......................................................................................................6 - 2
6.2 Features .............................................................................................................6 - 2
6.3 Register Organization of 8086 ...........................................................................6 - 3
6.3.1 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3

6.3.2 Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 4

6.3.3 Pointers and Index Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5

6.3.4 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5

6.4 Architecture of 8086..........................................................................................6 - 5
6.4.1 Bus Interface Unit [BIU]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 6

6.4.2 Execution Unit [EU] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8

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 6.4.2.1 Control Circuitry, Instruction Decoder, ALU . . . . . . . . . . . . . . . 6 - 8

6.4.2.2 Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8

6.4.2.3 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . 6 - 10

6.4.3 Memory Segmentation / Real Mode Memory Addressing . . . . . . . . . . . . . . . . 6 - 10
6.4.3.1 Rules for Memory Segmentation . . . . . . . . . . . . . . . . . . . 6 - 10

6.4.3.2 Advantages of Memory Segmentation . . . . . . . . . . . . . . . . . 6 - 10

6.4.3.3 Generation of 20-bit Address . . . . . . . . . . . . . . . . . . . . . 6 - 11

6.4.3.4 Pointers and Index Registers . . . . . . . . . . . . . . . . . . . . . 6 - 12

6.4.3.5 Default and Alternate Register Assignments. . . . . . . . . . . . . . . 6 - 13

6.4.3.6 Segment Override Prefix . . . . . . . . . . . . . . . . . . . . . . . 6 - 15

6.5 Addressing Modes ...........................................................................................6 - 15
6.5.1 Data Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 15
6.5.1.1 Addressing Modes for Accessing Immediate and Register Data . . . . . . 6 - 16

6.5.1.2 Addressing Modes for Accessing Data in Memory . . . . . . . . . . . . 6 - 16

6.5.1.3 Addressing Modes for Accessing I/O Ports (I/O Modes) . . . . . . . . . . 6 - 23

6.5.2 Program Memory-Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 24

6.5.3 Stack Memory Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 25

6.5.3.1 Stack Structure of 8086/88 . . . . . . . . . . . . . . . . . . . . . . 6 - 26

6.5.3.2 PUSH and POP Operations . . . . . . . . . . . . . . . . . . . . . . 6 - 27

6.5.3.3 CALL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 27

6.5.3.4 RET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 28

6.5.3.5 Overflow and Underflow of Stack . . . . . . . . . . . . . . . . . . . 6 - 28

Review Questions ..................................................................................................6 - 29
Two Marks Questions with Answers ................................................................6 - 30

Chapter - 7 8086 CPU Hardware Design (7 - 1) to (7 - 24)

7.1 8086 Signals .......................................................................................................7 - 2
7.1.1 Signals with Common Functions in both Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3

7.1.2 Signal Definitions (24 to 31) for Minimum Mode . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 4

7.1.3 Signal Definitions (24 to 31) for Maximum Mode. . . . . . . . . . . . . . . . . . . . . . . . . 7 - 5

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 7.2 Addressing Memory ..........................................................................................7 - 6
7.3 Addressing I/O ...................................................................................................7 - 8
7.4 Minimum Mode 8086 System and Timings .......................................................7 - 8
7.4.1 Minimum Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8

7.4.2 Minimum Mode 8086 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 13

7.4.3 Bus Timings for Minimum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 14

7.4.3.1 Timings for Read and Write Operations. . . . . . . . . . . . . . . . . 7 - 14

7.4.3.2 HOLD Response Sequence . . . . . . . . . . . . . . . . . . . . . . 7 - 16

7.5 Maximum Mode 8086 System and Timings ....................................................7 - 16
7.5.1 Maximum Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 16

7.5.2 Maximum Mode 8086 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 18

7.5.3 Bus Timings for Maximum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 20

7.5.3.1 Timings for Read and Write Operations. . . . . . . . . . . . . . . . . 7 - 20

7.5.3.2 Timings for RQ GT Signals . . . . . . . . . . . . . . . . . . . . . . 7 - 21

Review Questions ..................................................................................................7 - 22

Two Marks Questions with Answers ................................................................7 - 23

Chapter - 8 8086 Interrupts (8 - 1) to (8 - 12)

8.1 Introduction.......................................................................................................8 - 2
8.2 Sources of Interrupts in 8086 ............................................................................8 - 2
8.2.1 External Signal (Hardware Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3

8.2.2 Special Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3

8.2.3 Condition Produced by Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3

8.3 8086 Interrupt Types .........................................................................................8 - 4
8.3.1 Divide by Zero Interrupt (Type 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4

8.3.2 Single Step Interrupt (Type 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4

8.3.3 Non Maskable Interrupt (Type 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6

8.3.4 Breakpoint Interrupt (Type 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6

8.3.5 Overflow Interrupt (Type 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 6

8.3.6 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7

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 8.3.7 Maskable Interrupt (INTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 7
8.4 Interrupt Priorities ............................................................................................8 - 8
Review Questions ....................................................................................................8 - 9
Two Marks Questions with Answers ................................................................8 - 10

Chapter - 9 Memory Interfacing (9 - 1) to (9 - 20)

9.1 Introduction.......................................................................................................9 - 2
9.2 Terminology and Operations .............................................................................9 - 2
9.3 Memory Structure and its Requirements ..........................................................9 - 3
9.4 Basic Concepts in Memory Interfacing with 8085 .............................................9 - 4
9.4.1 Interfacing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 8
Review Questions ..................................................................................................9 - 17
Two Marks Questions with Answers ................................................................9 - 18

Chapter - 10 I/O Interfacing (10 - 1) to (10 - 14)

10.1 Introduction...................................................................................................10 - 2
10.2 I/O Interfacing Techniques in 8085 ...............................................................10 - 3
10.2.1 I/O Mapped I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3

10.2.2 I/O Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4

10.2.3 Interfacing Input and Output Devices with Examples . . . . . . . . . . . . . . . . . . . 10 - 5

10.2.4 Memory Mapped I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 9

10.2.4.1 Comparison between Memory Mapped I/O and I/O Mapped I/O in 8085 . 10 - 11
10.3 Data Transfer Schemes ................................................................................10 - 12
Review Questions ................................................................................................10 - 13
Two Marks Questions with Answers ..............................................................10 - 14

Chapter - 11 PPI - 8255 (11 - 1) to (11 - 38)

11.1 Features of 8255A .........................................................................................11 - 2
11.2 Pin Diagram ...................................................................................................11 - 3
11.3 Block Diagram................................................................................................11 - 5
11.3.1 Data Bus Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 6
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 11.3.2 Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 6

11.3.3 Group A and Group B Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 6

11.4 Operation Modes...........................................................................................11 - 6
11.4.1 Bit Set-Reset (BSR) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 6

11.4.2 I/O Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 7

11.5 Control Word Formats...................................................................................11 - 8
11.5.1 For Bit Set/Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 8

11.5.2 For I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 9

11.6 8255 Programming and Operation..............................................................11 - 12
11.6.1 Programming in Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 12

11.6.2 Programming in Mode 1 (Input / Output with Handshake). . . . . . . . . . . . . . 11 - 14

11.6.3 Programming in Mode 2 (Strobes Bi-directional Bus I/O) . . . . . . . . . . . . . . . 11 - 20

Output Control Signals : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 20

Input Control Signals :. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 21

Mode Definition Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 23

11.7 Interfacing 8255 in I/O Mapped I/O ............................................................11 - 23
11.8 Parallel Communication between Two MP Kits using Mode 2 of 8255......11 - 24
Review Questions ................................................................................................11 - 34
Two Marks Questions with Answers ..............................................................11 - 35

Chapter - 12 PIC - 8259 (12 - 1) to (12 - 22)

12.1 8259A Programmable Interrupt Controller ...................................................12 - 2
12.2 Features of 8259A..........................................................................................12 - 2
12.3 Block Diagram of 8259A................................................................................12 - 3
12.4 Interrupt Sequence with 8085......................................................................12 - 5
12.5 Priority Modes and Other Features ...............................................................12 - 6
12.6 Programming the 8259A................................................................................12 - 8
12.7 8259A Interfacing with 8085 .......................................................................12 - 17
12.8 Cascading.....................................................................................................12 - 18

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 Review Questions ................................................................................................12 - 20
Two Marks Questions with Answers ..............................................................12 - 21

Chapter - 13 Serial Data Transfer (USART) 8251 (13 - 1) to (13 - 28)

13.1 Serial Communication Supported by 8085 ....................................................13 - 2
13.2 Features of 8251A (USART) ...........................................................................13 - 7
13.3 Pin Diagram of 8251A ....................................................................................13 - 8
13.4 Block Diagram..............................................................................................13 - 10
13.5 8251A Control Words ..................................................................................13 - 13
13.6 8251A Status Word......................................................................................13 - 14
13.7 Data Communication Types.........................................................................13 - 15
13.7.1 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 16

13.7.2 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 16

13.7.3 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 17

13.7.4 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 17

13.8 Interfacing 8251A in I/O Mapped I/O..........................................................13 - 18
13.9 Programming 8251A....................................................................................13 - 19
Review Questions ................................................................................................13 - 25
Two Marks Questions with Answers ..............................................................13 - 26

Chapter - 14 Keyboard and Display Controller - 8279 (14 - 1) to (14 - 54)

New Table of Contents
14.1 Keyboard Interfacing .....................................................................................14 - 2
14.1.1 Key Debounce using Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 2

14.1.2 Key Debouncing using Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 3

14.1.3 Simple Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 4

14.1.4 Matrix Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 5

14.2 Display Interfacing .......................................................................................14 - 10
14.2.1 Interfacing Static LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 10

14.2.2 Interfacing Multiplexed Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 11

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14.3 Features of 8279..........................................................................................14 - 15
14.4 Pin Description.............................................................................................14 - 16
14.4.1 CPU Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 17

14.4.2 Keyboard Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 18

14.4.3 Display Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 18

14.5 Block Diagram..............................................................................................14 - 19
14.5.1 CPU Interface and Control Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 19

14.5.2 Scan Section (Scan Counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 21

14.5.3 Keyboard Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 21

14.5.4 Display Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 22

14.6 Operating Modes.........................................................................................14 - 22
14.6.1 Input Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 22

14.6.2 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 25

14.6.2.1 Left Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 25

14.6.2.2 Right Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 26

14.7 8279 Commands..........................................................................................14 - 28
14.7.1 Keyboard / Display Mode Set Command (000). . . . . . . . . . . . . . . . . . . . . . . . 14 - 28

14.7.2 Program Clock Command (001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 30

14.7.3 Read FIFO / Sensor RAM Command (010). . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 30

14.7.4 Read Display RAM Command (011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 31

14.7.5 Write Display RAM Command (100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 32

14.7.6 Display Write Inhibit / Blanking Command (101) . . . . . . . . . . . . . . . . . . . . . . 14 - 32

14.7.7 Clear Command (110) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 33

14.7.8 End Interrupt / Error Mode Set Command (111) . . . . . . . . . . . . . . . . . . . . . . 14 - 34

14.8 Interfacing 8279 in I/O Mapped I/O ............................................................14 - 35
14.9 Applications .................................................................................................14 - 36
Review Questions ................................................................................................14 - 51
Two Marks Questions with Answers ..............................................................14 - 52

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Chapter - 15 Programmable Interval Timer/Counter (15 - 1) to (15 - 18)
8253/8254
15.1 Features .........................................................................................................15 - 2
15.2 Block Diagram................................................................................................15 - 3
15.3 Operational Description ................................................................................15 - 5
15.4 Mode Definition.............................................................................................15 - 7
15.5 Programming Examples ...............................................................................15 - 14
15.6 Interfacing of 8253/54 in I/O Mapped I/O ..................................................15 - 15
Review Questions ...............................................................................................15 - 16
Two Marks Questions with Answers .............................................................15 - 17

Chapter - 16 A/D and D/A Converter Interfacing (16 - 1) to (16 - 36)

16.1 Digital to Analog Converter ...........................................................................16 - 2
16.2 DAC 1408 .......................................................................................................16 - 3
16.3 Interfacing DAC 1408 / 0808 with Microprocessor using 8255.....................16 - 7
16.4 Analog to Digital Converter .........................................................................16 - 12
16.5 ADC 0808/0809 Family ................................................................................16 - 12
16.6 ADC 7109 .....................................................................................................16 - 14
16.7 Interfacing ADC 0808 with 8085..................................................................16 - 15
16.8 Interfacing ADC 7109 with 8085..................................................................16 - 18
16.9 Temperature Control System ......................................................................16 - 21
16.10 Asynchronous, Synchronous and Interrupt Modes of Interfacing ADC.....16 - 27
16.11 Sample and Hold Circuit and Multiplexer..................................................16 - 29
16.11.1 Data Acquisition System using 8085 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 - 31

16.11.2 Another Way of Connecting MUX and SH Circuits . . . . . . . . . . . . . . . . . . . . 16 - 33

Review Questions ...............................................................................................16 - 33
Two Marks Questions with Answers .............................................................16 - 35

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Chapter - 17 8051 Microcontroller (17 - 1) to (17 - 36)
17.1 Introduction to 8051 Microcontroller ...........................................................17 - 2
17.2 Features of 8051 and 8051 Family Microcontrollers.....................................17 - 3
17.3 Architecture of 8051......................................................................................17 - 4
17.3.1 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 4

17.3.2 A and B CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 4

17.3.3 Data Pointer (DPTR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 4

17.3.4 The Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 6

17.3.5 8051 Flag Bits and the PSW Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 6

17.3.6 Special Function Register of 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 7

17.4 Pin Description of 8051 ...............................................................................17 - 10
17.5 Internal and External Memories..................................................................17 - 12
17.5.1 Internal RAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 12
17.5.1.1 8051 Register Banks (Working Registers) . . . . . . . . . . . . . . . 17 - 15

17.5.1.2 Bit / Byte Addressable . . . . . . . . . . . . . . . . . . . . . . 17 - 15

17.5.1.3 General Purpose RAM . . . . . . . . . . . . . . . . . . . . . . . 17 - 15

17.5.2 ROM Space in the 8051. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 15
17.6 Interfacing and Timing Diagrams for Memory Interfacing ..........................17 - 15
17.6.1 External Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 16

17.6.2 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 18

17.6.3 Important Points to Remember in Accessing External Memory . . . . . . . . . . 17 - 20

17.6.4 Interfacing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 - 21

17.7 Stack and Stack Pointer ...............................................................................17 - 30
Review Questions ...............................................................................................17 - 30
Two Marks Questions with Answers .............................................................17 - 32

Chapter - 18 8051 Instruction Set and Programming (18 - 1) to (18 - 82)

18.1 8051 Addressing Modes ................................................................................18 - 2
18.1.1 Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 2

18.1.2 Direct Byte Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 2

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 18.1.3 Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 3

18.1.4 Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 3

18.1.5 Register Specific. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 4

18.1.6 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 4

18.1.7 Stack Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 4

18.2 Classification of Instruction Set of 8051 ........................................................18 - 5
18.3 Data Transfer Instructions .............................................................................18 - 5
18.3.1 Instructions to Access External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 9

18.3.2 Instructions to Access External ROM / Program Memory . . . . . . . . . . . . . . . 18 - 11

18.3.3 Data Transfer with Stack (PUSH and POP) Instructions . . . . . . . . . . . . . . . . . 18 - 12

18.3.4 Data Exchange Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 13

18.4 Byte Level Logical Instructions.....................................................................18 - 15
18.5 Arithmetic Instructions ................................................................................18 - 20
18.5.1 Incrementing and Decrementing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 20

18.5.2 Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 23

18.5.3 Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 25

18.5.4 Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 26

18.5.5 Decimal Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 27

18.6 Bit Level Logical Instructions .......................................................................18 - 28
18.7 Rotate and Swap Instructions......................................................................18 - 32
18.8 Jump and CALL Instructions.........................................................................18 - 35
18.8.1 Jump and Call Program Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 36

18.8.2 Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 36

18.8.3 CALL and Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 39

18.9 Time Delay for 8051.....................................................................................18 - 40
18.10 Introduction to Assembly Language Programming ...................................18 - 42
18.10.1 Comparison between Assembly Language and Machine Language . . . . . . 18 - 43

18.10.2 Assembly Language Programming Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 43

18.10.3 Assembling and Running an 8051 Program . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 44

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 18.10.4 Data Types of 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 45

18.10.5 Assembler Directives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 - 45

18.11 Program Examples .....................................................................................18 - 47
Method 2 : Use immediate and register addressing ......................................... 18 - 48
Program 4 : Add two 8-bit numbers. .................................................................. 18 - 48
Program 5 : Add two 16-bit numbers. ................................................................ 18 - 48
Program 6 : Find the 2's complement of a number in R0................................... 18 - 48
Program 7 : Unpack the packed BCD number stored in the accumulator and save the
result in R0 and R1 such that (R0)¬ LSB and (R1) ¬ MSB. ........... 18 - 48
Program 8 : Subtract two 8-bit numbers and exchange digits. .......................... 18 - 48
Program 9 : Subtract the contents of R1 of Bank0 from the contents of
R0 of Bank2. .................................................................................... 18 - 49
Program 10 : Division two 8-bit numbers........................................................... 18 - 49
Program 11 : Multiply two 8-bit numbers. ......................................................... 18 - 49
Program 12 : Program to convert 8-bit binary number to its equivalent BCD. .. 18 - 49
Program 13 : Binary to Gray conversion............................................................. 18 - 50
Program 14 : To add two 16-bit BCD numbers. .................................................. 18 - 52
Program 16 : Subtract two 16-bit numbers. ....................................................... 18 - 53
Program 17 : Generate BCD up counter and send each count to port A. .......... 18 - 53
Program 18 : Find the maximum number from a given 8-bit ten numbers. ...... 18 - 54
Program 19 : Arrange the given ten 8-bit numbers in the ascending order....... 18 - 55
Program 20 : Find the number of negative and
positive numbers in a given array. ................................................ 18 - 57
Program 21 : Count number of one’s in a number............................................. 18 - 58
Program 22 : Count number of zero’s in a number. ........................................... 18 - 59
Program 23 : Count number of one’s and zero’s in a number. .......................... 18 - 60
Program 24 : To generate a square wave on the port 1..................................... 18 - 61

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Program 25 : To generate a square wave on the port pin P1.0.......................... 18 - 61
Program 26 : To find the sum of 10 numbers stored in the array. ..................... 18 - 62
Program 27 : Data transfer from memory block B1 to memory block B2. ......... 18 - 64
Program 28 : Data transfer from memory block B1 to memory block B2. ......... 18 - 65
Program 29 : To search a byte in a given numbers............................................. 18 - 66
Program 30 : Multiply two 8-bit numbers using repetitive addition.................. 18 - 68
Program 31 : To find the average of given N numbers....................................... 18 - 69
Program 32 : To find factorial of a number ........................................................ 18 - 71
Program 33 : To find Fibonacci series of N given terms. .................................... 18 - 72
Program 34 : Write an assembly language program to move 5 bytes of data stored
at location 8000H onwards to the location C000H onwards and
vice-versa. ..................................................................................... 18 - 73
Program 35 : An array of 10 numbers is stored at location 4000H onwards ..... 18 - 74
Program 36 : Write an assembly language program to realize following logic circuit
using Boolean instructions of 8051............................................... 18 - 75
Program 37 : Write a program to load accumulator with values 55H and complement
70 times........................................................................................ 18 - 75
Program 38 : Program to count the number of ONE's and ZERO's in two consecutive
data memory locations. ................................................................ 18 - 75
Program 39 : Write a program to save the status of bits P1.3 and P1.4 on RAM bit
location 5 and 6 respectively. ....................................................... 18 - 76
Program 40 : What is the content of R5 after execution of the following program ? ...
.............................................................................................................................18 - 76
Review Questions ................................................................................................18 - 77
Two Marks Questions with Answers ..............................................................18 - 78

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Chapter - 19 8051 I/O Ports, Timer, Serial Port
& Interrupts (19 - 1) to (19 - 48)

19.1 8051 I/O Ports Structure................................................................................19 - 2

19.2 8051 I/O Port Programming ..........................................................................19 - 5
19.2.1 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 5

19.2.2 Demultiplexing P0.7 - P0.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 5

19.2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 6

19.2.4 Pull-up Resistors for Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 7

19.3 I/O Bit Manipulation Programming ...............................................................19 - 8
19.4 8051 Timers ...................................................................................................19 - 9
19.4.1 Structure of TMOD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 9

19.4.2 Structure of TCON Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 10

19.5 8051 Timer Modes and Programming .........................................................19 - 11
19.6 8051 Counter Programming ........................................................................19 - 18
19.7 8051 Serial Port ...........................................................................................19 - 27
19.7.1 Operating Modes for Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 29

19.7.2 Generating Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 30

19.7.3 Programming 8051 for Serial Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 32

19.7.4 Programming 8051 for Receiving Data Serially. . . . . . . . . . . . . . . . . . . . . . . . 19 - 34

19.7.5 Doubling the Baud Rate in the 8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 35

19.7.6 8051 Connection to RS 232C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 36

19.8 8051 Interrupt Structure .............................................................................19 - 37
19.8.1 Interrupt Control (Enabling and Disabling Interrupts using IE) . . . . . . . . . . . 19 - 37

19.8.2 Interrupt Priority and Interrupt Destinations (Vector Locations) . . . . . . . . . 19 - 39

19.9 Programming Interrupts ..............................................................................19 - 40
19.9.1 Programming Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 40

19.9.2 Programming External Hardware Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . 19 - 41

19.9.3 Programming the Serial Communication Interrupts . . . . . . . . . . . . . . . . . . . 19 - 42

Review Questions ................................................................................................19 - 45
Two Marks Questions with Answers ..............................................................19 - 46
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Chapter - 20 Microcontroller Applications (20 - 1) to (20 - 32)
20.1 Keyboard Interface ........................................................................................20 - 2
20.1.1 Key Debounce using Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 - 2

20.1.2 Key Debouncing using Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 - 3

20.1.3 Simple Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 - 3

20.1.4 Matrix Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 - 5

20.2 Display Interface ............................................................................................20 - 9
20.2.1 LED Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 - 9

20.2.2 Multiplexed 7-Segment Display Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . 20 - 11

20.2.3 LCD Interfacing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 - 17

20.3 Closed Loop Control of Servomotor ............................................................20 - 21
20.4 Stepper Motor Control ................................................................................20 - 23
20.5 Washing Machine Control ...........................................................................20 - 27
Review Questions ................................................................................................20 - 30
Two Marks Question with Answer .................................................................20 - 32

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Lab Experiments
Lab Experiment 1 : Store 8-bit data in memory.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 42

Lab Experiment 2 : Exchange the contents of memory locations. . . . . . . . . . . . . . . . . . . 2 - 42

Lab Experiment 3 : Add two 8-bit numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 43

Lab Experiment 4 : Subtract two 8-bit numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 43

Lab Experiment 5 : Add two 16-bit numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 44

Lab Experiment 6 : Subtract two 16-bit numbers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 45

Lab Experiment 7 : Check results after execution of INR B, INR C and INX B instructions. . . 2 - 47

Lab Experiment 8 : Check results after execution of DCR C, DCR B and DCX B instructions. 2 - 47

Lab Experiment 9 : Find the 1’s complement of a number. . . . . . . . . . . . . . . . . . . . . . . . 2 - 48

Lab Experiment 10 : Find the 2’s complement of a number. . . . . . . . . . . . . . . . . . . . . . . 2 - 48

Lab Experiment 11 : Pack the two unpacked BCD numbers. . . . . . . . . . . . . . . . . . . . . . . 2 - 49

Lab Experiment 12 : Unpack the BCD number.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 49

Lab Experiment 13 : Sample subroutine program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 50

Lab Experiment 14 : Add contents of two memory locations. . . . . . . . . . . . . . . . . . . . . . 2 - 51

Lab Experiment 15 : Right shift data within the 8-bit register. . . . . . . . . . . . . . . . . . . . . . 2 - 53

Lab Experiment 16 : Right shift data within 16-bit register. . . . . . . . . . . . . . . . . . . . . . . . 2 - 53

Lab Experiment 17 : Left shift 16-bit data within 16-bit register.. . . . . . . . . . . . . . . . . . . . 2 - 54

Lab Experiment 18 : Alter the contents of flag register. . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 55

Lab Experiment 19 : Find 2's complement of 16-bit number. . . . . . . . . . . . . . . . . . . . . . 2 - 55

Lab Experiment 20 : Simulation of CALL and RET instructions. . . . . . . . . . . . . . . . . . . . . 2 - 55

Lab Experiment 21 : Find the factorial of a number.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 57

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Lab Experiment 22 : Calculate the sum of series of numbers. . . . . . . . . . . . . . . . . . . . . . . 3 - 4

Lab Experiment 23 : Data transfer from memory block B1 to memory block B2. . . . . . . . . . 3 - 6

Lab Experiment 24 : Multiply two 8-bit numbers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 7

Lab Experiment 25 : Divide 16-bit number by 8-bit number.. . . . . . . . . . . . . . . . . . . . . . . 3 - 8

Lab Experiment 26 : Find the negative numbers in a block of data. . . . . . . . . . . . . . . . . . . 3 - 9

Lab Experiment 27 : Find the largest of given numbers. . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 11

Lab Experiment 28 : Count number of one's in a number. . . . . . . . . . . . . . . . . . . . . . . . 3 - 12

Lab Experiment 29 : Arrange numbers in the ascending order. . . . . . . . . . . . . . . . . . . . . 3 - 13

Lab Experiment 30 : Calculate the sum of series of even numbers. . . . . . . . . . . . . . . . . . 3 - 15

Lab Experiment 31 : Calculate the sum of series of odd numbers. . . . . . . . . . . . . . . . . . . 3 - 16

Lab Experiment 32 : Find the square of given number.. . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 18

Lab Experiment 33 : Search a byte in a given number. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 19

Lab Experiment 34 : Add two decimal numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 20

Lab Experiment 35 : Add each element of array with the elements of another array.. . . . . . 3 - 21

Lab Experiment 36 : Separate even numbers from given numbers. . . . . . . . . . . . . . . . . . 3 - 22

Lab Experiment 37 : Transfer contents to overlapping memory blocks.. . . . . . . . . . . . . . . 3 - 24

Lab Experiment 38 : Inserting string in a given array of characters.. . . . . . . . . . . . . . . . . . 3 - 24

Lab Experiment 39 : Deleting string in a given array of characters.. . . . . . . . . . . . . . . . . . 3 - 25

Lab Experiment 40 : Add parity bit to 7-bit ASCII characters. . . . . . . . . . . . . . . . . . . . . . 3 - 26

Lab Experiment 41 : Find the number of negative, zero and positive numbers. . . . . . . . . . 3 - 27

Lab Experiment 42 : Multiply two eight bit numbers with shift and add method. . . . . . . . . . 3 - 29

Lab Experiment 43 : Divide 16-bit number with 8-bit number using shifting technique. . . . 3 - 30

Lab Experiment 44 : Simulate DAA instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 33

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Lab Experiment 45 : Program to test RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 35

Lab Experiment 46 : Write an assembly language program to generate fibonacci number. 3 - 35

Lab Experiment 47 : Program to evaluate a 2 + b 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 36

Lab Experiment 48 : Program to count given data in a set of numbers . . . . . . . . . . . . . . . 3 - 38

Lab Experiment 49 : Program to multiply two 16-bit numbers. . . . . . . . . . . . . . . . . . . . . 3 - 38

Lab Experiment 50 : Generate a delay of 0.4 seconds. . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 42

Lab Experiment 51 : Generate and display binary up counter. . . . . . . . . . . . . . . . . . . . . 3 - 42

Lab Experiment 52 : Generate and display BCD up counter with frequency 1 Hz. . . . . . . . 3 - 44

Lab Experiment 53 : Generate and display BCD down counter with frequency 1 Hz . . . . . 3 - 45

Lab Experiment 54 : Generate and display the contents of decimal counter.. . . . . . . . . . . 3 - 47

Lab Experiment 55 : Identify the error and correct the given delay routine. . . . . . . . . . . . . 3 - 48

Lab Experiment 56 : 2-Digit BCD to binary conversion. . . . . . . . . . . . . . . . . . . . . . . . . 3 - 49

Lab Experiment 57 : Binary to BCD conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 51

Lab Experiment 58 : Find the 7-segment codes for given numbers. . . . . . . . . . . . . . . . . . 3 - 53

Lab Experiment 59 : Find the ASCII character. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 55

Lab Experiment 60 : Add two 2-digit BCD numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 58

Lab Experiment 61 : Add two 4-digit BCD numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 59

Lab Experiment 62 : Subtraction of two BCD numbers. . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 60

Lab Experiment 63 : Multiply two 2-digit BCD numbers . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 61

Lab Experiment 64 : Blink port C bit 0 of 8255. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 11

Lab Experiment 65 : Output byte from SOD pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 2

Lab Experiment 66 : Output square wave from SOD pin. . . . . . . . . . . . . . . . . . . . . . . . . 13 - 3

Lab Experiment 67 : Receive ASCII character through SID pin. . . . . . . . . . . . . . . . . . . . . 13 - 4

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Lab Experiment 68 : Transmit message using 8251. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 20

Lab Experiment 69 : Receive message using 8251. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 23

Lab Experiment 70 : Hardware and software for 64-key matrix keyboard interface . . . . . . 14 - 7

Lab Experiment 71 : Hardware and software for interfacing 8-digit 7-segment display. . . 14 - 13

Lab Experiment 72 : Hardware and software for 8 ´ 8 keyboard interface using 8279. . . 14 - 36

Lab Experiment 73 : Hardware and software to interface 8 ´ 4 matrix keyboard using 8279 . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 41

Lab Experiment 74 : Hardware and software to interface eight 7-segment digits using 8279. . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 42

Lab Experiment 75 : Write an assembly language program to roll message ‘HELLO123’. 14 - 45

Lab Experiment 76 : Interface 4´ 4 matrix keyboard and 4 digit 7-segment display using 8279 .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 47

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1 8085 Processor

Contents
1.1 Features . . . . . . . . . . . . . . . . . . April/May-04
1.2 Architecture of 8085 . . . . . . . . . . . . . . . . . . April/May-04, Nov./Dec.-04,
. . . . . . . . . . . . . . . . . . Dec.-07, 08, 09, 10, June-06,
. . . . . . . . . . . . . . . . . . May-10, 11
1.3 Pin Definitions of 8085 . . . . . . . . . . . . . . . . . . May/June-09, Nov./Dec.-06, 08, 09,
. . . . . . . . . . . . . . . . . . April/May-10
1.4 Bus Organization . . . . . . . . . . . . . . . . . . Nov./Dec.-04

(1 - 1)
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Microprocessors and Microcontroller 1-2 8085 Processor

8085A is an 8-bit microprocessor suitable for a wide range of applications. It is a

single-chip, NMOS device implemented with approximately 6200 transistors on a 164 ´ 222
mil chip contained in a 40-pin dual-in-line package.
In this chapter we will see features, architecture, pin diagram and bus organization of
8085 microprocessor.

1.1 Features April/May-04

The features of 8085 include :

1. It is an 8-bit microprocessor i.e. it can accept, process, or provide 8-bit data
simultaneously.
2. It operates on a single +5 V power supply connected at VCC; power supply ground
is connected to Vss.
3. It operates on clock cycle with 50 % duty cycle.
4. It has on chip clock generator. This internal clock generator requires tuned circuit
like LC, RC or crystal. The internal clock generator divides oscillator frequency by
2 and generates clock signal, which can be used for synchronizing external devices.
5. It can operate with a 3 MHz clock frequency. The 8085A-2 version can operate at
the maximum frequency of 5 MHz.
6. It has 16 address lines, hence it can access (2 16 ) 64 kbytes of memory.
8
7. It provides 8-bit I/O addresses to access (2 ) 256 I/O ports.
8. In 8085, the lower 8-bit address bus (A 0 - A 7 ) and data bus (D0 - D7 ) are
multiplexed to reduce number of external pins. But due to this, external hardware
(latch) is required to separate address lines and data lines.
9. It supports 74 instructions with the following addressing modes :
a) Immediate b) Register c) Direct d) Indirect e) Implied.
10. The Arithmetic Logic Unit (ALU) of 8085 performs :
a) 8-bit binary addition with or without carry.
b) 16-bit binary addition. c) 2 digit BCD addition.
d) 8-bit binary subtraction with or without borrow.
e) 8-bit logical AND, OR, EX-OR, complement (NOT), and bit shift operations.
11. It has 8-bit accumulator, flag register, instruction register, six 8-bit general purpose
registers (B, C, D, E, H and L) and two 16-bit registers (SP and PC). Getting the
operand from the general purpose registers is more faster than from memory.
Hence skilled programmers always prefer general purpose registers to store
program variables than memory.

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Microprocessors and Microcontroller 1-3 8085 Processor

12. It provides five hardware interrupts : TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
13. It has serial I/O control which allows serial communication.
14. It provides control signals (IO/M, RD, WR) to control the bus cycles and hence
external bus controller is not required.
15. The external hardware (another microprocessor or equivalent master) can detect
which machine cycle microprocessor is executing using status signals
(IO/M, S0, S1). This feature is very useful when more than one processors are
using common system resources (memory and I/O devices).
16. It has a mechanism by which it is possible to increase its interrupt handling
capacity.
17. The 8085 has an ability to share system bus with Direct Memory Access controller.
This feature allows to transfer large amount of data from I/O device to memory or
from memory to I/O device with high speeds.
18. It can be used to implement three chip microcomputer with supporting I/O
devices like IC 8155 and IC 8355.

1.2 Architecture of 8085

April/May-04, Nov./Dec.-04, Dec.-07, 08, 09, 10, June-06, May-10, 11

Fig. 1.1 (See Fig. 1.1 on next page) shows the architecture of 8085.
It consists of various functional blocks as listed below :
· Registers
· Arithmetic and Logic Unit
· Instruction decoder and machine cycle encoder
· Address buffer
· Address/Data buffer
· Incrementer/Decrementer address latch
· Interrupt control
· Serial I/O control
· Timing and control circuitry.

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Microprocessors and Microcontroller 1-4 8085 Processor

INTA RST 6.5 TRAP

INTR RST 5.5 RST 7.5 SID SOD

Interrupt control Serial I/O control

8-bit internal data bus

Temporary Instruction W Reg Z Reg

Accumulator Flag register
register register
B Reg C Reg
D Reg E Reg
H Reg L Reg
Arithmetic Stack pointer
logic Instruction
decoder Program
unit counter
(ALU) and
machine
cycle Incrementer/
encoder Decrementer
+5 V address latch
POWER
SUPPLY
GND

X Timing and Control

CLK 1
IN X2
CLK Address Address / Data
CONTROL STATUS DMA RESET buffer buffer
GEN

CLK OUT RD ALE S1 HOLD RESET IN

A15 - A8 AD7 - AD0
READY WR S0 IO/M HLDA RESET OUT
Address bus Data / Address
bus
Fig. 1.1 Architecture of 8085

1.2.1 Register Structure

Temporary The Fig. 1.2 shows the register structure of 8085.
register The shaded portion of this register model is called
W Reg Z Reg programmer's model of 8085. It includes six 8-bit
A Reg Flag Reg
registers- (B, C, D, E, H and L) one accumulator, one
flag register and two 16-bit registers (SP and PC). All
B Reg C Reg these registers are accessible to programmer and hence
D Reg E Reg they are included in the programmer's model. The
remaining registers - temporary, W and Z are not
H Reg L Reg
accessible to the programmers; they are used by
Stack Pointer (SP) microprocessor for internal, intermediate operations.
Program Counter (PC)

Fig. 1.2 Register structure of

8085
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Microprocessors and Microcontroller 1-5 8085 Processor

The 8085 registers are classified as :

1. General Purpose Registers

2. Temporary Registers
a) Temporary data register b) W and Z registers.

3. Special Purpose Registers

a) Accumulator b) Flag registers c) Instruction register.

4. Sixteen bit Registers

a) Program Counter (PC) b) Stack Pointer (SP).

1. General Purpose Registers :

B, C, D, E, H and L are 8-bit general purpose registers can be used as a separate 8-bit
registers or as 16-bit register pairs, BC, DE and HL. When used in register pair mode, the
high order byte resides in the first register (i.e. in B when BC is used as a register pair)
and the low order byte in the second (i.e. in C when BC is used as a register pair).
HL pair also functions as a data pointer or memory pointer. These are also called
scratchpad registers, as user can store data in them. To store and read data from these
registers bus access is not required, it is an internal operation. Thus it provides an efficient
way to store intermediate results and use them when required. The efficient programmer
prefers to use these registers to store intermediate results than the memory locations which
require bus access and hence more time to perform the operation.

2. Temporary Registers :
a) Temporary Data Register : The ALU has two inputs. One input is supplied by the
accumulator and other from temporary data register. The programmer cannot access this
temporary data register. However, it is internally used for execution of most of the
arithmetic and logical instructions.
For example : ADD B is the instruction in the arithmetic group of instructions which
adds the contents of register A and register B and stores result in register A. The addition
operation is performed by ALU. The ALU takes inputs from register A and temporary
data register. The contents of register B are transferred to temporary data register for
applying second input to the ALU.
b) W and Z registers : W and Z registers are temporary registers. These registers are
used to hold 8-bit data during execution of some instructions. These registers are not
available for programmer, since 8085 uses them internally.

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Microprocessors and Microcontroller 1-6 8085 Processor

Use of W and Z registers :

The CALL instruction is used to transfer program control to a subprogram or
subroutine. This instruction pushes the current PC contents onto the stack and loads the
given address into the PC. The given address is temporarily stored in the W and Z
registers and placed on the bus for the fetch cycle. Thus the program control is transferred
to the address given in the instruction. XCHG instruction exchanges the contents of H with
D and L with E. At the time of exchange W and Z registers are used for temporary
storage of data.

3. Special Purpose Registers :

a) Register A (Accumulator) : It is a tri-state eight bit register. It is extensively used in
arithmetic, logic, load and store operations, as well as in, input/output (I/O) operations.
Most of the times the result of arithmetic and logical operations is stored in the register A.
Hence it is also identified as accumulator.
b) Flag Register : It is an 8-bit register, in which five of the bits carry significant
information in the form of flags : S (Sign flag), Z (Zero flag), AC (Auxiliary carry flag),
P (Parity flag), and CY (carry flag), as shown in Fig. 1.3.
D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY

Fig. 1.3 Flag register

S-Sign flag : After the execution of arithmetic or logical operations, if bit D7 of the
result is 1, the sign flag is set. In a given byte if D7 is 1, the number will be viewed as
negative number. If D7 is 0, the number will be considered as positive number.
Z-Zero flag : The zero flag sets if the result of operation in ALU is zero and flag resets
if result is non zero. The zero flag is also set if a certain register content becomes zero
following an increment or decrement operation of that register.
AC-Auxiliary Carry flag : This flag is set if there is an overflow out of bit 3 i.e. , carry
from lower nibble to higher nibble (D3 bit to D4 bit). This flag is used for BCD operations
and it is not available for the programmer.
P-Parity flag : Parity is defined by the number of ones present in the accumulator.
After an arithmetic or logical operation if the result has an even number of ones, i.e. even
parity, the flag is set. If the parity is odd, flag is reset.
CY-Carry flag : This flag is set if there is an overflow out of bit 7. The carry flag also
serves as a borrow flag for subtraction. In both the examples shown below, the carry flag
is set.
ADDITION SUBTRACTION

9B H 1001 1011 89 H 1000 1001

+ 75 H + 0111 0101 – AB H – 1010 1011
Carry 1 10 H 1 0001 0000 Borrow 1 DE H 1 1101 1110
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Microprocessors and Microcontroller 1-7 8085 Processor

c) Instruction Register : In a typical processor operation, the processor first fetches the
opcode of instruction from memory (i.e. it places an address on the address bus and
memory responds by placing the data stored at the specified address on the data bus). The
CPU stores this opcode in a register called the instruction register. This opcode is further
sent to the instruction decoder to select one of the 256 alternatives.

4. Sixteen Bit Registers :

a) Program Counter (PC) : Program is a sequence of instructions. As mentioned earlier,
microprocessor fetches these instructions from the memory and executes them sequentially.
The program counter is a special purpose register which, at a given time, stores the
address of the next instruction to be fetched. Program Counter acts as a pointer to the next
instruction. How processor increments program counter depends on the nature of the
instruction; for one byte instruction it increments program counter by one, for two byte
instruction it increments program counter by two and for three byte instruction it
increments program counter by three such that program counter always points to the
address of the next instruction.
In case of JUMP and CALL instructions, address followed by JUMP and CALL
instructions is placed in the program counter. The processor then fetches the next
instruction from the new address specified by JUMP or CALL instruction. In conditional
JUMP and conditional CALL instructions, if the condition is not satisfied, the processor
increments program counter by three so that it points the instruction followed by
conditional JUMP or CALL instruction; otherwise processor fetches the next instruction
from the new address specified by JUMP or CALL instruction.
b) Stack Pointer (SP) : The stack is a reserved area of the memory in the RAM where
temporary information may be stored. A 16-bit stack pointer is used to hold the address of
the most recent stack entry.

1.2.2 Arithmetic Logic Unit (ALU)

The 8085’s ALU performs arithmetic and logical functions on eight bit variables. The
arithmetic unit performs bitwise fundamental arithmetic operations such as addition and
subtraction. The logic unit performs logical operations such as complement, AND, OR and
EX-OR, as well as rotate and clear. The ALU also looks after the branching decisions.

1.2.3 Instruction Decoder

As mentioned earlier, the processor first fetches the opcode of instruction from
memory and stores this opcode in the instruction register. It is then sent to the instruction
decoder. The instruction decoder decodes it and accordingly gives the timing and control
signals which control the register, the data buffers, ALU and external peripheral signals
(explained in later sections) depending on the nature of the instruction.

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The 8085 executes seven different types of machine cycles. It gives the information
about which machine cycle is currently executing in the encoded form on the S0, S1 and
IO/M lines. This task is done by machine cycle encoder.

1.2.4 Address Buffer

This is an 8-bit unidirectional buffer. It is used to drive external high order address
bus (A15-A8). It is also used to tri-state the high order address bus under certain conditions
such as reset, hold, halt, and when address lines are not in use.

1.2.5 Address/Data Buffer

This is an 8-bit bi-directional buffer. It is used to drive multiplexed address/data bus,
i.e. low order address bus (A7-A0) and data bus (D7-D0). It is also used to tri-state the
multiplexed address/data bus under certain conditions such as reset, hold, halt and when
the bus is not in use.
The address and data buffers are used to drive external address and data buses
respectively. Due to these buffers the address and data buses can be tri-stated when they
are not in use.

1.2.6 Incrementer/Decrementer Address Latch

This 16-bit register is used to increment or decrement the contents of program counter
or stack pointer as a part of execution of instructions related to them.

1.2.7 Interrupt Control

The processor fetches, decodes and executes instructions in a sequence. Sometimes it is
necessary to have processor the automatically execute one of a collection of special
routines whenever special condition exists within a program or the microcomputer system.
The most important thing is that, after execution of the special routine, the program
control must be transferred to the program which processor was executing before the
occurrence of the special condition. The occurrence of this special condition is referred as
interrupt. The interrupt control block has five interrupt inputs RST 5.5, RST 6.5, RST 7.5,
TRAP and INTR and one acknowledge signal INTA.

1.2.8 Serial I/O Control

In situations like, data transmission over long distance and communication with
cassette tapes or a CRT terminal, it is necessary to transmit data bit by bit to reduce the
cost of cabling. In serial communication one bit is transferred at a time over a single line.
The 8085’s serial I/O control provides two lines, SOD and SID for serial communication.
The serial output data (SOD) line is used to send data serially and serial input data (SID)
line is used to receive data serially.

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1.2.9 Timing and Control Circuitry

The control circuitry in the processor 8085 is responsible for all the operations. The
control circuitry and hence the operations in 8085 are synchronized with the help of clock
signal. Along with the control of fetching and decoding operations and generating
appropriate signals for instruction execution, control circuitry also generates signals
required to interface external devices to the processor, 8085.

1.3 Pin Definitions of 8085 May/June-09, Nov./Dec.-09, April/May-10

Fig. 1.4 (a) and (b) show 8085 pin configuration and functional pin diagram of 8085
respectively. The signals of 8085 can be classified into seven groups according to their
functions.
+5 V GND

1 2 40 20
X1 X2 VCC VSS
X1 1 40 VCC Serial SID 5
I/O
SOD 4
X2 2 39 HOLD ports
28
RESET OUT 3 38 HLDA A15
High-order
SOD 4 37 A8 address bus
CLK(OUT)
TRAP 6 21
SID 5 36 RESET IN RST 7.5 7
Externally initiated signals

19
RST 6.5 8
TRAP 6 35 READY AD0
RST 5.5 9 Multiplexed
RST 7.5 7 34 IO / M address / data
INTR 10
AD7 bus
RST 6.5 8 33 S1
12
READY 35
RST 5.5 9 32 RD
HOLD 39
INTR 10 31 WR RESET IN 36
8085A
INTA 11 30 ALE 8085A

AD0 12 29 S0
acknowledgment

INTA 11
External signal

AD1 13 28 A15 HLDA 36 30

ALE
AD2 14 27 A14 29
S0
33 S1 Control
AD3 15 26 A13 and
34
AD4 IO / M status
16 25 A12 signals
32
RD
AD5 17 24 A11 31
WR
AD6 18 23 A10

AD7 19 22 A9

VSS 20 21 A8 3 37

RESET OUT CLK OUT

Fig. 1.4 (a) Pin configuration Fig. 1.4 (b) Functional pin diagram
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a) Power supply and frequency signals.

b) Data bus and address bus
c) Control bus
d) Interrupt signals
e) Serial I/O signals
f) DMA signals
g) Reset signals

1.3.1 Power Supply and Frequency Signals

i) VCC : It requires a single +5 V power supply.
ii) VSS : Ground reference.
iii) X1 and X2 : A tuned circuit like LC, RC or crystal is connected at these two pins.
The internal clock generator divides oscillator frequency by 2, therefore, to operate a
system at 3 MHz, the crystal of tuned circuit must have a frequency of 6 MHz.
iv) CLK OUT : This signal is used as a system clock for other devices. Its frequency is
half the oscillator frequency.

1.3.2 Data Bus and Address Bus

A) AD0 to AD7 : The 8-bit data bus (D0 - D7) is multiplexed with the lower half
(A0 - A7) of the 16-bit address bus. During first part of the machine cycle (T1), lower 8 bits
of memory address or I/O address appear on the bus. During remaining part of the
machine cycle (T2 and T3) these lines are used as a bi-directional data bus.
B) A8 to A15 : The upper half of the 16-bit address appears on the address lines A8 to
A15. These lines are exclusively used for the most significant 8 bits of the 16-bit address
lines.

1.3.3 Control and Status Signals Nov./Dec.-06, 08

A) ALE (Address Latch Enable) : We know that AD0 to AD7 lines are multiplexed and
the lower half of address (A0 - A7) is available only during T1 of the machine cycle. This
lower half of address is also necessary during T2 and T3 of machine cycle to access specific
location in memory or I/O port. This means that the lower half of an address must be
latched in T1 of the machine cycle, so that it is available throughout the machine cycle.
The latching of lower half of an address bus is done by using external latch and ALE
signal from 8085.
B) RD and WR : These signals are basically used to control the direction of the data
flow between processor and memory or I/O device/port. A low on RD indicates that the
data must be read from the selected memory location or I/O port via data bus. A low on
WR indicates that the data must be written into the selected memory location or I/O port
via data bus.
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C) IO/M, S0 and S1 : IO/M indicates whether I/O operation or memory operation is

being carried out. S1 and S0 indicate the type of machine cycle in progress.
D) READY : It is used by the microprocessor to sense whether a peripheral is ready or
not for data transfer. If not, the processor waits. It is thus used to synchronize slower
peripherals to the microprocessor.

1.3.4 Interrupt Signals April/May-10

The 8085 has five hardware interrupt signals : RST 5.5, RST 6.5, RST 7.5, TRAP and
INTR. The microprocessor recognizes interrupt requests on these lines at the end of the
current instruction execution.
The INTA (Interrupt Acknowledge) signal is used to indicate that the processor has
acknowledged an INTR interrupt.

1.3.5 Serial I/O Signals

A) SID (Serial I/P Data) : This input signal is used to accept serial data bit by bit from
the external device.
B) SOD (Serial O/P Data) : This is an output signal which enables the transmission of
serial data bit by bit to the external device.

1.3.6 DMA Signal

A) HOLD : This signal indicates that another master is requesting for the use of
address bus, data bus and control bus.
B) HLDA : This active high signal is used to acknowledge HOLD request.

1.3.7 Reset Signals

A) RESET IN : A low on this pin
1) Sets the program counter to zero (0000H).
2) Resets the interrupt enable and HLDA flip-flops.
3) Tri-states the data bus, address bus and control bus.
(Note : Only during RESET is active).
4) Affects the contents of processor’s internal registers randomly.
On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction
from address 0000H. For proper reset operation reset signal must be held low for at least 3
clock cycles. The power-on reset circuit can be used to ensure execution of first instruction
from address 0000H.
B) RESET OUT : This active high signal indicates that processor is being reset. This
signal is synchronized to the processor clock and it can be used to reset other devices
connected in the system.

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1.4 Bus Organization

In this section we are going to see how we can use various buses of 8085, how to
demultiplex address and data bus, how to generate control signals, how to provide clock
and reset signals to 8085 and so on.

1.4.1 Clock Circuits

The 8085 has on chip clock generator.
VCC(+5V) Clk Out Fig. 1.5 shows the internal block diagram of
the on chip clock generator. The internal
f1 clock generator requires tuned circuit like
T Q
LC, RC or crystal, or external clock source
X1 Clk as an input to generate the clock. The
Q f2
internal T-flip flop divides the frequency by
2. Hence the operating frequency of the
X2
8085 is always half of the oscillator
Fig. 1.5 Block diagram of built-in clock frequency.
generator

LC Tuned Circuit :
It is a LC resonant tank circuit. The
resonant frequency for this circuit is given by
X1
1
L C fr =
2p L ( C ext + C int )
X2
Where Cint is the internal capacitance and
it is normally 15 pF. The output frequency of
Fig. 1.6 LC circuit this circuit has 10 % variations. To minimize
the variations in the output frequency, it is
recommended to have C ext at least twice that of Cint i.e. 30 pF.

RC Tuned Circuit : Fig. 1.7 shows the RC tuned

circuit. The output frequency of this circuit is also not
exactly stable. But this circuit has an advantage that its X1
component cost is less.
C R

Crystal Oscillator Circuit : Fig. 1.8 shows the crystal X2

oscillator circuit. It is the most stable circuit. The 20 pF
capacitor in the circuit is connected to assure oscillator
start-up at the correct frequency.
Fig. 1.7 RC Circuit

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+5 V

X1 Pull-up
resistance
Crystal
External
X1
X2 clock
8085
C
Non-connected X2
(NC)

Fig. 1.8 Crystal clock circuit Fig. 1.9 External frequency source

External Clock :
Fig. 1.9 shows how to drive clock input of 8085 with external frequency source. Here
external clock is applied at X 1 input and X 2 input is kept open.

1.4.2 Demultiplexing AD 7 -AD 0 Nov./Dec.-04

We know that AD0 to AD7 lines are multiplexed and the lower half of address
(A0 - A7) is available only during T1 of the machine cycle. This lower half of address is
also necessary during T2 and T3 of machine cycle to access specific location in memory or
I/O port. This means that the lower half of an address bus must be latched in T1 of the
machine cycle, so that it is available throughout the machine cycle. The latching of lower
half of an address is done by using external latch and ALE signal from 8085. The Fig. 1.10
shows the hardware connection for latching the lower half of an address. The IC 74LS373
is an 8-bit latch, having 8 D flip-flops. The input is transferred to the output only when
clock is high. This clock signal is driven by ALE signal from 8085. The ALE signal is
activated only during T1, so input is transferred to the output only during T1 i.e. address
(A0 - A7) on the AD0 to AD7 multiplexed bus. In the remaining part of the machine cycle,
ALE signal is disabled so output of the latch (A0 - A7) remains unchanged. To latch lower
half of an address, in each machine cycle, the 8085 gives ALE signal high during T1 of
every machine cycle.

1.4.3 Reset Circuit

On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction
from address 0000H. For proper reset operation reset signal must be held low for at least
3 clock cycles. The power-on reset circuit can be used to ensure execution of first
instruction from address 0000H. Fig. 1.11 shows the power-on reset circuit with typical R,
C values. (Note : R, C values may vary due to power supply ramp up time).
Upon power-up, RESET IN must remain low for at least 10 ms after minimum Vcc has
been reached, in the circuit shown in Fig. 1.11. Upon power up or key press, the
RESET IN goes low and slowly rises to +5 V, providing sufficient time for the processor to
reset the system. The diode is connected to discharge the capacitor immediately when
power supply is switched OFF.
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IC 74LS373

AD0 D Q A0
AD1 A1
AD2 A2
CLK
AD3 A3
AD4 A4
AD5 A5
AD6 A6
AD7 A7
G OC
Enable Output control
ALE
D0
D1
D2
D3
D4
D5
D6
D7

Fig. 1.10 Latching circuit

+5 V

IN 4148 75 K

To 8085
Reset
100 W
1 mF

No
contact

Fig. 1.11 Power on reset

After RESET, 8085 loads 0000H in PC register and clears the INTE flag. Before going to
execute interrupt service routine, it is necessary to setup certain parameters, required to
execute interrupt service routine. To avoid interrupt to occur before completion of these
initial requirements, after power on or reset, INTE flip-flop is cleared to disable interrupts.
It can be enabled by EI instruction after initial settings.

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As we know that, after power up or reset 8085 fetches its first instruction from 0000H
address, and it has to be the first instruction from monitor program. Therefore EPROM
consisting of monitor program must be located from address 0000H in any
8085 microprocessor system.

1.4.4 Generation of Control Signals

The 8085 microprocessor provides RD and WR signals to initiate read or write cycle.
Because these signals are used both for reading/writing memory and for reading/writing
an input device, it is necessary to generate separate read and write signals for memory
and I/O devices.
The 8085 provides IO/M signal to indicate whether the initiated cycle is for I/O device
or for memory device. Using IO/M signal along with RD and WR, it is possible to
generate separate four control signals :
MEMR (Memory Read) : To read data from memory.
MEMW (Memory Write) : To write data in memory.
IOR (I/O Read) : To read data from I/O device.
IOW (I/O Write) : To write data in I/O device.
Fig. 1.12 shows the circuit which generates MEMR, MEMW, IOR and IOW signals.

8085
IO/M
MEMR
RD
WR
MEMW

IOR

IOW

Fig. 1.12 Generation of MEMR, MEMW, IOR and IOW signals

We know that for OR gate, when both the inputs are low then only output is low.
Table 1.1 shows the truth table used to generate MEMR, MEMW, IOR and IOW signals.
The signal IO/M goes low for memory operation. This signal is logically ORed with RD
and WR to get MEMR and MEMW signals. When both RD and IO/M signals go low,
MEMR signal goes low. Similarly, when both WR and IO/M signals go low, MEMW
signal goes low. To generate IOR and IOW signals for I/O operation, IO/M signal is first
inverted and then logically ORed with RD and WR signals.

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IO M RD WR MEMR MEMW IOR IOW

RD + IO M WR + IO M RD + IO M WR + IO M

0 0 0 Condition never exists, because RD and WR signals does not go

low simultaneously

0 0 1 0 1 1 1

0 1 0 1 0 1 1

0 1 1 1 1 1 1

1 0 0 Condition never exists, because RD and WR signals does not go

low simultaneously

1 0 1 1 1 0 1

1 1 0 1 1 1 0

1 1 1 1 1 1 1

Table 1.1
Same truth table can be implemented using 3:8 decoder as shown in Fig. 1.13.

+5V

G VCC Y0
Y1
MEMR
Y2
3:8 MEMW
WR A Decoder Y3
RD B Y4
IO/M C (74LS138) Y5
IOR
Y6
IOW
Y7
G1 G2

Fig. 1.13 Generation of control signals using 3:8 decoder

1.4.5 Bus Drivers

Typically, the 8085 buses can source 400 mA and sink 2 mA of current, i.e. it can drive
only one TTL load. Therefore, it is necessary to increase driving capacity of the 8085 buses.
Bus drivers, buffers are used to increase the driving capacity of the buses.

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Unidirectional Buffers : 1
20
1A1 VCC 1G 1Y1
As we know, the address bus is 2 18
unidirectional, 8-bit unidirectional buffer,
1A2 1Y2
74LS244 is used to buffer higher address 4 16

bus. The Fig. 1.14 shows the logic 1A3 1Y3

6 14
diagram of 74LS244. It consists of eight
non-inverting buffers with tri-state 1A4 1Y4
8 12
outputs. Each one can sink 24 mA and
2A5 2Y1
source 15 mA of current. These buffers 11 9

are divided into two groups. The 2Y2

2A6
13 7
enabling and disabling of these groups
are controlled by 1G and 2G lines. 2A7 2Y3
15 5

Bi-directional Buffer : 17
2A8 2Y4
3

To increase the driving capacity of GND 2G

data bus, bi-directional buffer is used. 10 19
Fig. 1.15 shows the logic diagram of the
bi-directional buffer 74LS245, also called Fig. 1.14 Logic diagram of the 74LS244
an octal bus transceivers. It consists of
sixteen non-inverting buffers, eight for each direction, with tri-state output. The direction
of data flow is controlled by the pin DIR. When DIR is high, data flows from the A bus to
the B bus; when it is low, data flows from B to A. The active low enable signal and the
DIR signal are ANDed to activate the bus lines. Each buffer in this device can sink 24 mA
and source 15 mA of current.
20 74LS245 10
VCC GND
2 A1 B1 18
Function table
3 A2 B2 17
Direction
4 A3 B3 16 Enable control Operation
G DIR
5 A4 B4 15
L L B Data to A Bus
6 A5 B5 14 L H A Data to B Bus
H X Isolation
7 A6 B6 13

8 A7 B7 12 H=High level,L=Low level,X=Irrelevant

9 A8 B8 11
DIR G
1 19
Direction Enable
control

Fig. 1.15 Logic diagram of the 74LS245

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1.4.6 Typical Configuration

Fig. 1.16 shows schematic of the 8085 microprocessor demultiplexed address bus and
control signals.
+5 V
20
A15 17 3
VCC A15
15 5 A14
13 7 A13 High-
11 74LS244 Octal 9
Bus A12 order
8 12 A11 Address
6 Driver 14 A10 bus
4 16 A9
A8 2 18
A8

1 19 10

+5 V +5 V

40 35 20
AD7
1 VCC READY 18 VCC 19
X1 A7
17 16
A15 28 A6
2MHz 14 15
crystal 2 74LS373 A5 Low
X2 A8 13 12
20 pF A4 order
21 8 9 A3 Address
7 6
AD7 19 A2 bus
4 4 5
SOD AD0 A1
AD0 3 2
5 SID G OC GND A0
12
33 S 11 1 10
1 30
NC 29 8085 A ALE
S0 34 +5 V
37 IO/M
CLK OUT 32
38 RD 9 11
100K HLDA 31 D7
11 WR 8 12 D6
INTA 7 13
36 74LS245 D5
6 14
RESET IN Bidirectional D4 Data
1mF 6 5 15
TRAP Bus D3 bus
1K 7 4 16
Driver D2
RST7.5 3 17
8 D1
RST6.5 2 18 D0
RESET DIR G GND
9
RST5.5 OUT
10 1 19 10 20
INTR
From 39
Interrupt HOLD +5 V
source Vss
6 16
20 VCC
G3
O7
O6 9
IO/M IOW Control
3 74LS138 10 bus
A O5 IOR
RD 2 2 3-to-8 13
A decoder O2 MEMW
WR 1 1 14
A O1 MEMR
5 0
G2 O0
G1 GND
4 8

Fig. 1.16 Typical 8085 configuration

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It also shows clock and reset circuits. Interrupt lines which are not in use are
grounded. This is necessary because floating interrupt line may cause false triggering of
interrupt. Similarly, since the DMA controller is not used, HOLD line is also grounded. As
we know READY signal is used to synchronize slow peripherals with the microprocessor.
When it is low, microprocessor enters in the wait state and when it is high, it indicates
that the memory or peripheral is ready to send or receive data. Here, the READY signal is
tied high to prevent the microprocessor from entering the wait state. ALE signal is
connected to the clock input of the latch, to latch the low order address in T1 of the
machine cycle. To control the direction of the bi-directional buffer 74LS245, RD signal from
8085 is connected to DIR input of the bi-directional buffer. Thus, when RD signal is low,
DIR is low and data flows from memory or I/O device to the microprocessor, performing
read operation. When RD signal is high, DIR is high and data flows from microprocessor
to memory or I/O device performing write operation.

Review Questions

Section 1.1
Q.1 Explain architectural features of 8085. May-04, Marks 4

Section 1.2
Q.1 With neat functional block diagram, explain the architecture of 8085 microprocessor.
June-06, Dec.-07, Dec.-04,08,09,10, May-04,10,11,12, Marks 16

Q.2 Explain the architecture, data flow and instruction execution of 8085 microprocessor.
May-11, Marks 8

Q.3 Give the format of flag register in 8085. Explain each flag.
Q.4 Define the function of parity flag and zero flag in 8085. June-12, Marks 2

Section 1.3

Q.1 Write about the pin configuration of 8085 processor and explain them in detail.
June-09, Marks 16

Q.2 Draw the pin diagram of 8085 microprocessor. June-12, Marks 4

Q.3 Explain different control signals used by 8085.

Q.4 What is the use of ALE signal ?
Q.5 What is the use of CLKOUT and RESET OUT signals of 8085 processor ?
Q.6 Describe the function of following pins in 8085.
a. READY b. ALE c. IO/M d. HOLD e. RESET
Q.7 Explain the signals used in DMA operation in 8085.

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Section 1.4
Q.1 Draw the schematic of latching low-order address bus in 8085 microprocessor.
Dec.-11, Marks 2

Q.2 Why AD0-AD7 lines are multiplexed ?

Q.3 Draw and explain typical 8085 configuration.
Q.4 Write a note on bus drivers.

Two Marks Questions with Answers

Q.1 What is Microprocessor? Give the power supply and clock frequency of 8085?
Ans. : A microprocessor is a multipurpose, programmable logic device that reads
binary instructions from a storage device called memory accepts binary data as input
and processes data according to those instructions and provides result as output. The
power supply of 8085 is +5 V and clock frequency in 3 MHz.

Q.2 What are the functions of an accumulator?

Ans. : The accumulator is the register associated with the ALU operations and
sometimes I/O operations. It is an integral part of ALU. It holds one of data to be
processed by ALU. It also temporarily stores the result of the operation performed by
the ALU.

Q.3 List the 16 - bit registers of 8085 microprocessor.

Ans. : Stack pointer (SP) and Program counter (PC).

Q.4 List the allowed register pairs of 8085.

Ans. :
B-C register pair
D-E register pair
H-L register pair
Q.5 Mention the purpose of SID and SOD lines.
Ans. : SID (Serial input data line): It is an input line through which the
microprocessor accepts serial data. SOD (Serial output data line): It is an output line
through which the microprocessor sends output serial data.

Q.6 What is the function of IO/M signal in the 8085?

Ans. : It is a status signal. It is used to differentiate between memory locations and
I/O operations. When this signal is low (IO/M = 0) it denotes the memory related
operations. When this signal is high (IO/M = 1) it denotes an I/O operation.

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Q.7 What is the signal classification of 8085 ?

Ans. : All the signals of 8085 can be classified into 6 groups
i) Address bus ii) Data bus
iii) Control and status signals iv) Power supply and frequency signals
v) Externally initiated signals vi) Serial I/O ports
Q.8 What is the use of bi-directional buffers?
Ans. : It is used to increase the driving capacity of the data bus. The data bus of a
microcomputer system is bi-directional, so it requires a bi-directional buffer that allows
the data to flow in both directions.

Q.9 Explain the signals HOLD, READY and SID.

Ans. : HOLD indicates that a peripheral such as DMA controller is requesting the use
of address bus, data bus and control bus. READY is used to delay the microprocessor
read or write cycles until a slow responding peripheral is ready to send or accept data.
SID is used to accept serial data bit by bit.

Q.10 What is the need for ALE signal in 8085 microprocessor? Dec.-04,09, May-10

Ans. : The ALE signal is used to demultiplex (separate) AD0 - AD7 lines to A0 - A7
(address lines) and D0 - D7 (data lines). The separation of address lines and data lines is
achieved by connecting a external latch to AD0 - AD7 lines and enabling the latch when
ALE signal is active.

Q.11 How performance of a microprocessor is measured interms of MIPS ? June-07

Ans. : The performance of a microprocessor is measured interms of MIPS (Million
Instructions per Second). It is given as,
1
MIPS rate =
Average time required for the execution of instruction ´ 10 6

Q.12 A microprocessor takes n µs is for executing an instruction. What design

change will make the microprocessor to execute the same instruction in is
n/2 µs ? June-07
Ans. : By replacing the crystal of double frequency than that of existing one we can
execute the same instruction in half time.

Q.13 If a 5 MHz crystal is connected with 8085; what is the value of system clock
frequency and one T-state ? Dec.-07
Crystal frequecny 5 MHz
Ans. : System clock frequency = = = 2.5 MHz,
2 2
1
one T-state = = 0.4 µsec.
2.5 ´ 10 6
Q.14 What are the important control signals in 8085 microprocessor ? Dec.-08
Ans. : The important control signals in 8085 microprocessor are : ALE, IO M, RD and
WR

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Q.15 What is tri-state logic ? June-09

Ans. : Logic outputs have two normal states, LOW and HIGH, corresponding to logic
values 0 and 1. However, some outputs have a third electrical state that is not logic
state at all, called the high-impedance or floating state. In this state the output behaves
as if it isn't even connected to the circuit, except for a small leakage current that may
flow into or out of the output pin. The circuit having such three states is called tri-state
logic.
Q.16 What is the function of the Ready signal of 8085 ?
Ans. : It is used by the microprocessor to sense whether a peripheral is ready or not
for data transfer. If not, the processor waits. It is thus used to synchronize slower
peripherals to the microprocessor.
Q.17 List the five interrupt pins available in 8085. May-10
Ans. : The five interrupt pins available in 8085 are : TRAP, RST 7.5, RST 6.5, RST 5.5,
and INTR.
Q.18 Specify the size of data, address, memory word and memory capacity of 8085
microprocessor. May-11
Ans. : Size of data bus = 8-bits Size of address bus = 16-bits
Size of memory word = 8-bits Memory capacity = 64 kbytes
Q.19 List the special purpose registers of 8085
Ans. : The special purpose registers of 8085 are :
1. A (Accumulator) 2. Flag register
3. Instruction register 4. program counter 5. Stack pointer.
Q.20 List the signals provided for DMA operation by 8085 and explain their use.
Ans. : HOLD : This signal indicates that another master is requesting for the use of
address bus, data bus and control bus.
HLDA : This active high signal is used to acknowledge HOLD request.
Q.21 What are the content of PC and INTE flag after reset ?
Ans. : After reset, PC is loaded with 0000H and INTE flag is cleared.
Q.22 What is the need of bus drivers ?
Ans. : Typically, the 8085 buses can source 400 mA and sink 2 mA of current, i.e. it
can drive only one TTL load. Therefore, it is necessary to increase driving capacity of
the 8085 buses. Bus drivers, buffers are used to increase the driving capacity of the
buses.
Q.23 What is the function of program counter ?
Ans. : Program counter stores the address of the next instruction to be fetched. Thus it
is used as pointer to the instruction.
Q.24 What is stack and what is the function of stack pointer ? Dec.-07
Ans. : The stack is a reserved area of the memory in the RAM where temporary
information may be stored. A 16-bit stack pointer is used to hold the address of the
most recent stack entry.
Q.25 What are flags available in 8085 ?
Ans. : Various flags in 8085 are : S (Sign flag), Z (Zero flag), AC (Auxiliary carry flag),
P (Parity flag), and CY (Carry flag)
qqq
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Contents
2.1 Instruction Classification
2.2 Instruction Set of 8085 . . . . . . . . . . . . . . . . . . May/June-07,09; April/May-04, 10
. . . . . . . . . . . . . . . . . . Nov./Dec.-07, 08, 09
2.3 Addressing Modes
2.4 Instruction Set Summary
2.5 Assembly Language Programming
2.6 Programming Examples
2.7 Instruction Comparisons
2.8 Instruction Formats

(2 - 1)
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In the previous chapter we have studied block diagram of microprocessor 8085. The
block diagram shows microprocessor's functions for data processing and data handling. It
also shows how each of these logic functions are connected together. Such microprocessor
performs a particular task by executing proper sequence of instructions. Thus to perform a
task in a particular microprocessor system, programmer has to know the instructions
supported by microprocessor used in the microprocessor system.
This chapter explains the set of instructions supported by the 8085 microprocessor and
explains how to write programs (set of instructions written in a proper sequence to
perform a particular task) using them. This chapter also gives a large number of programs
to perform different tasks.

2.1 Instruction Classification

The instructions provided by the 8085 can be categorized into five different groups
based on the nature of function of the instructions.
· Data transfer operations
· Arithmetic operations
· Logical operations
· Branch operations and
· Stack, Input/Output and Machine control operations

2.1.1 Data Transfer Operations

The data transfer instructions load given data into register, copy data from register to
register, copy data from register to memory location, and vice versa. In other words we
can say that data transfer instructions copy data from source to destination. Source can be
data or contents of register or contents of memory location whereas destination can be
register or memory location. These instructions do not affect the flag register of the
processor.

2.1.2 Arithmetic Operations

The arithmetic instructions provided by 8085 perform addition, subtraction, increment
and decrement operations.
· Addition : Any 8-bit number, or the contents of a register, or the contents of a
memory location can be added to the contents of the accumulator and the
resulted sum is stored in the accumulator. The resulted carry bit is stored in the
carry flag. In 8085, no two other registers can be added directly, i.e. the contents

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of B and C registers cannot be added directly. To add two 16-bit numbers the
8085 provides DAD instruction. It adds the data within the register pair to the
contents of the HL register pair and resulted sum is stored in the HL register
pair.
· Subtraction : Any 8-bit number, or the contents of a register, or the contents of a
memory location can be subtracted from the contents of the accumulator and the
result is stored in the accumulator. The resulted borrow bit is stored in the carry
flag. In 8085, no two other registers can be added directly.
· Increment/Decrement : The 8085 has the increment and decrement instructions
to increment and decrement the contents of any register, memory location or
register pair by 1.

2.1.3 Logical Operations

The logical instructions provided by 8085 perform logical, rotate, compare and
complement operations.
· Logical : Using logical instructions, any 8-bit number, or the contents of a
register, or of a memory location can be logically ANDed, ORed, or
Exclusive-ORed with the contents of the accumulator and the result is stored in
the accumulator. The result also affects the flags according to definition of flags.
For example, the zero result sets the zero flag.
· Rotate : These instructions allow shifting of each bit in the accumulator either
left or right by 1 bit position.
· Compare : Any 8-bit number, or the contents of a register, or the contents of a
memory location can be compared for equality, greater than, or less than, with
the contents of the accumulator.
· Complement : The result of accumulator can be complemented with this
instruction. It replaces all 0 s by 1s and all 1s by 0 s.

2.1.4 Branching Operations

These instructions allow the 8085 to change the sequence of the program, either
unconditionally or under certain test conditions. These instructions include branch
instructions, subroutine call and return instructions and restart instructions.

2.1.5 Stack, Input / Output and Machine Control Operations

These instructions control the stack operations, input/output operations and machine
operations. The stack instructions allow the transfer of data from register pair to stack
memory and from stack memory to the register pair. The input/output instruction allows
the transfer of 8-bit data to input/output port. On the other hand machine instructions
control the machine operations such as interrupt, halt, or do nothing.

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2.2 Instruction Set of 8085 May/June-09; April/May-10

In this section, the instructions from all groups are explained with the help of
examples. Before to discuss these instructions, let us get familiar with the notations used in
the explanation of instructions. These are:
Notation Meaning
M Memory location pointed by HL register pair
r 8-bit register
rp 16-bit register pair
rs Source register
rd Destination register
addr 16-bit address / 8-bit address

2.2.1 Data Transfer Group May/June-07, Nov./Dec.-07

1. MVI r, data (8) This instruction directly loads a specified register with an 8-bit data
given within the instruction. The register r is an 8-bit general
purpose register such as A, B, C, D, E, H and L.

Operation : r ¬ 8-bit data (byte)

Example :
MVI B, 60H ; This instruction will load 60H directly into the B register.

2. MVI M, data (8) This instruction directly loads an 8-bit data given within the
instruction into a memory location. The memory location is specified
by the contents of HL register pair.

Operation : M ¬ byte or (HL) ¬ byte

Example : H = 20H and L = 50H

MVI M, 40H ; This instruction will load 40H into memory whose address is
2050H.

Before Execution After Execution

204FH 204FH

HL = 2050H MVI M, 40H HL = 2050H 40

2051H 2051H

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3. MOV rd, rs This instruction copies data from the source register into destination
register. The rs and rd are general purpose registers such as A, B, C,
D, E, H and L. The contents of the source register remain unchanged
after execution of the instruction.

Operation : rd ¬ rs

Example : A = 20H
MOV B, A ; This instruction will copy the contents of register A (20H) into
register B.

4. MOV M, rs This instruction copies data from the source register into memory
location pointed by the HL register pair. The rs is an 8-bit general
purpose register such as A, B, C, D, E, H and L.

Operation : (HL) ¬ rs

Example : If HL = 2050H, B = 30H.

MOV M, B ; This instruction will copy the contents of B register (30H) into the
memory location whose address is specified by HL (2050H).

5. MOV rd, M This instruction copies data from memory location whose address is
specified by HL register pair into destination register. The contents of
the memory location remain unchanged. The rd is an 8-bit general
purpose register such as A, B, C, D, E, H and L.

Operation : rd ¬ (HL)

Example : HL = 2050H, contents at 2050H memory location = 40H

MOV C, M ; This instruction will copy the contents of memory location pointed
by HL register pair (40H) into the C register.

6. LXI rp, data (16) This instruction loads immediate 16 bit data specified within the
instruction into register pair or stack pointer. The rp is 16-bit register
pair such as BC, DE, HL or 16-bit stack pointer.

Operation : rp ¬ data (16)

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Example :
LXI B,1020H ; This instruction will load 10H into B register and 20H into C
register.

7. STA addr This instruction stores the contents of A register into the memory
location whose address is directly specified within the instruction.
The contents of A register remain unchanged.

Operation : (addr) ¬ A

Example : A = 50H
STA 2000H ; This instruction will store the contents of A register (50H) to
memory location 2000H.

8. LDA addr This instruction copies the contents of the memory location whose
address is given within the instruction into the accumulator. The
contents of the memory location remain unchanged.

Operation : A ¬ (addr)

Example : (2000H) = 30H

LDA 2000H ; This instruction will copy the contents of memory location 2000H
i.e. data 30H into the A register

9. SHLD addr This instruction stores the contents of L register in the memory
location given within the instruction and contents of H register at
address next to it. This instruction is used to store the contents of H
and L registers directly into the memory. The contents of the H and
L registers remain unchanged.

Operation : (addr) ¬ L and (addr + 1) ¬ H

Example : H = 30H, L = 60H

SHLD 2500H ; This instruction will copy the contents of L register at address
2500H and the contents of H register at address 2501H.

10. LHLD addr This instruction copies the contents of the memory location given
within the instruction into the L register and the contents of the next
memory location into the H register.

Operation : L ¬ (addr), H ¬ (addr + 1)

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Example : (2500H) = 30H, (2501H) = 60H

LHLD 2500H ; This instruction will copy the contents of memory location 2500H
i.e. data 30H into the L register and the contents at memory
location 2501H i.e. data 60H into the H register.

11. STAX rp This instruction copies the contents of accumulator into the memory
location whose address is specified by the specified register pair. The
rp is BC or DE register pair. This register pair is used as a memory
pointer. The contents of the accumulator remain unchanged.

Operation : (rp) ¬ A

Example : BC = 1020H, A = 50H

STAX B ; This instruction will copy the contents of A register (50H) to the
memory location specified by BC register pair (1020H).

12. LDAX rp This instruction copies the contents of memory location whose
address is specified by the register pair into the accumulator. The rp
is BC or DE register pair. The register pair is used as a memory
pointer.

Operation : A ¬ (rp)

Example : DE = 2030H, (2030H) = 80H

LDAX D This instruction will copy the contents of memory location specified
by DE register pair (80H) into the accumulator.

13. XCHG This instruction exchanges the contents of the register H with that of
D and of L with that of E.

Operation : H « D and L « E

Example : DE = 2040H, HL = 7080H

XCHG ; This instruction will load the data into registers as follows
H = 20H, L = 40H, D = 70H and E = 80

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2.2.2 Arithmetic Group Nov./Dec.-07

1. ADD r This instruction adds the contents of the specified register to the
contents of accumulator and stores result in the accumulator. The r
is 8-bit general purpose register such as A, B, C, D, E, H and L.

Operation : A ¬A + r

Example : A = 20H, C = 30H.

ADD C ; This instruction will add the contents of C register, i.e. data 30H to
the contents of accumulator, i.e. data 20H and it will store the
result 50H in the accumulator.

2. ADD M This instruction adds the contents of the memory location pointed by
HL register pair to the contents of accumulator and stores result in
the accumulator. The HL register pair is used as a memory pointer.
This instruction affects all flags.

Operation : A ¬A + M

Example : A = 20H, HL = 2050H, (2050H) = 10H

ADD M ; This instruction will add the contents of memory location pointed
by HL register pair, 2050H i.e. data 10H to the contents of
accumulator i.e. data 20H and it will store the result, 30H in the
accumulator.

3. ADI data (8) This instruction adds the 8 bit data given within the instruction to
the contents of accumulator and stores the result in the accumulator.

Operation : A ¬ A + data (8)

Example : A = 50H
ADI 70H ; This instruction will add 70H to the contents of the accumulator
(50H) and it will store the result in the accumulator (C0H).

4. ADC r This instruction adds the contents of specified register to the contents
of accumulator with carry. This means, if the carry flag is set by
some previous operation, it adds 1 and the contents of the specified
register to the contents of accumulator, else it adds the contents of
the specified register only. The r is 8-bit general purpose register
such as A, B, C, D, E, H and L.

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Operation : A ¬ A + r + CY

Example : Carry flag = 1, A = 50H, C = 20H

ADC C ; This instruction will add the contents of C (20H) register to the
contents of accumulator (50H) with carry (1) and it will store result,
71H (50H + 20H + 1 = 71H) in the accumulator

5. ADC M This instruction adds the contents of memory location pointed by HL

register pair to the contents of accumulator with carry and stores the
result in the accumulator. HL register pair is used as a memory
pointer.

Operation : A ¬ A + M + CY

Example : Carry flag = 1, HL = 2050H, A = 20H, (2050H) = 30H.

ADC M ; This instruction will add the contents of memory location pointed
by HL register pair, 2050H, i.e. data 30H to the contents of
accumulator, i.e. data 20H with carry flag (1). It will store the
result (30+20+1=51H) in the accumulator.

6. ACI data (8) This instruction adds 8 bit data given within the instruction to the
contents of accumulator with carry and stores result in the
accumulator.

Operation : A ¬ A + data (8) + CY

Example : A = 30H, Carry flag = 1

ACI 20H ; This instruction will add 20H to the contents of accumulator, i.e.
data 30H with carry (1) and stores the result,
51H (30 + 20 + 1 = 51H) in the accumulator.

7. DAD rp This instruction adds the contents of the specified register pair to the
contents of the HL register pair and stores the result in the HL
register pair. The rp is 16-bit register pair such as BC, DE, HL or
stack pointer. Only higher order register is to be specified for register
pair within the instruction.

Operation : HL ¬ HL + rp

Example : DE = 1020H, HL = 2050H

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DAD D ; This instruction will add the contents of DE register pair, 1020H to
the contents of HL register pair, 2050H. It will store the result,
3070H in the HL register pair.

8. SUB r This instruction subtracts the contents of the specified register from
the contents of the accumulator and stores the result in the
accumulator. The register r is 8-bit general purpose register such as
A, B, C, D, E, H and L.

Operation : A ¬A – r

Example : A = 50H, B = 30H.

SUB B ; This instruction will subtract the contents of B register (30H) from
the contents of accumulator (50H) and stores the result (20H) in
the accumulator.

9. SUB M This instruction subtracts the contents of the memory location

pointed by HL register pair from the contents of accumulator and
stores the result in the accumulator. The HL register pair is used as a
memory pointer.

Operation : A ¬A – M

Example : HL = 1020H, A = 50H, (1020H) = 10H

SUB M ; This instruction will subtract the contents of memory location
pointed by HL register pair, 1020H, i.e. data 10H from the contents
accumulator, i.e. data 50H and stores the result (40H) in
accumulator.

10. SUI data (8) This instruction subtracts an 8 bit data given within the instruction
from the contents of the accumulator and stores the result in the
accumulator.

Operation : A ¬ A – data (8)

Example : A = 40H,
SUI 20H ; This instruction will subtract 20H from the contents of accumulator
(40H). It will store the result (20H) in the accumulator.

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11. SBB r This instruction subtracts the specified register contents and borrow
flag from the accumulator contents. This means, if the carry flag
(borrow for subtraction) is set by some previous operation, it
subtracts 1 and the contents of the specified register from the
contents of accumulator, else it subtracts the contents of the specified
register only. The register r is 8-bit register such as A, B, C, D, E, H
and L.

Operation : A ¬ A – r – CY

Example : Carry flag = 1, C = 20H, A = 40H

SBB C ; This
; instruction will subtract the contents of C register (20H) and
carry flag (1) from the contents of accumulator (40H). It will store
the result (40H – 20H – 1 = 1FH) in the accumulator.

12. SBB M This instruction subtracts the contents of memory location pointed by
HL register pair from the contents of accumulator and borrow flag
and stores the result in the accumulator.

Operation : A ¬ A – M – CY

Example : Carry flag = 1, HL = 2050H, A = 50H, (2050H) = 10H.

SBB M ; This instruction will subtract the contents of memory location;
pointed by HL register pair, 2050H, i.e. data 10H and borrow
(Carry flag=1) from the contents of accumulator (50H) and
stores the result 3FH in the accumulator (50 – 10 – 1 = 3F).

13. SBI data (8) This instruction subtracts 8 bit data given within the instruction and
borrow flag from the contents of accumulator and stores the result in
the accumulator.

Operation : A ¬ A - data(8) - CY

Example : Carry flag = 1, A = 50H

SBI 20H ; This instruction will subtract 20H and the carry flag (1) from the
contents of the accumulator (50H). It will store the result
(50H – 20H – 1 = 2FH) in the accumulator.

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14. DAA This instruction adjusts accumulator to packed BCD (Binary Coded
Decimal) after adding two BCD numbers.
Instruction works as follows :
1. If the value of the low - order four bits (D3-D0) in the accumulator
is greater than 9 or if auxiliary carry flag is set, the instruction adds
6 (06) to the low-order four bits.
2. If the value of the high-order four bits (D7 - D4) in the
accumulator is greater than 9 or if carry flag is set, the instruction
adds 6 (60) to the high-order four bits.

Example :
If, A = 0011 1001 = 39 BCD
and C = 0001 0010 = 12 BCD then
ADD C ; Gives A = 0100 1011 = 4BH
DAA ; adds 0110 because 1011>9,
; A=0101 0001 = 51 BCD
If A = 1001 0110 = 96 BCD
and D = 0000 0111 = 07 BCD then
ADD D ; Gives A = 1001 1101 = 9DH
DAA ; adds 0110 because 1101 > 9,
A = 1010 0011 = A3H,
1010 > 9 so adds 0110 0000,
A = 0000 0011 = 03 BCD, CF = 1.

15. INR r This instruction increments the contents of specified register by 1.

The result is stored in the same register. The register r is 8-bit
general purpose register such as A, B, C, D, E, H and L.

Operation : r ¬r + 1

Example : B = 10H
INR B ; This instruction will increment the contents of B register (10H) by
one and stores the result (10+1 = 11H) in the same i.e. B register.

16. INR M This instruction increments the contents of memory location pointed
by HL register pair by 1. The result is stored at the same memory
location. The HL register pair is used as a memory pointer.

Operation : M¬ M+1

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Example : HL = 2050H, (2050H) = 30H

INR M ; This instruction will increment the contents of memory location
pointed by HL register pair, 2050H, i.e. data 30H by one. It will
store the result (30 + 1 = 31H) at the same place.

17. INX rp This instruction increments the contents of register pair by one. The
result is stored in the same register pair. The rp is register pair such
as BC, DE, HL or stack pointer (SP).

Operation : rp ¬ rp + 1

Example : HL = 10FFH
INX H ; This instruction will increment the contents of HL register pair
(10FFH) by one. It will store the result (10FF + 1 = 1100H) in the
same i.e. HL register pair.

18. DCR r This instruction decrements the contents of the specified register by
one. It stores the result in the same register. The register r is 8-bit
general purpose register such as A, B, C, D, E, H and L.

Operation : r ¬r – 1

Example : E = 20H
DCR E ; This instruction will decrement the contents of E register (20H) by
one. It will store the result (20 – 1 = 1FH) in the same, i.e. E
register.

19. DCR M This instruction decrements the contents of memory location pointed
by HL register pair by 1. The HL register pair is used as a memory
pointer. The result is stored in the same memory location.

Operation : M ¬M – 1

Example : HL = 2050H, (2050H) = 21H

DCR M ; This instruction will decrement the contents of memory location
pointed by HL register pair, 2050H, i.e. data 21H by one. It will
store the result (21 – 1 = 20H) in the same memory location.

20. DCX rp This instruction decrements the contents of register pair by one. The
result is stored in the same register pair. The rp is register pair such

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as BC, DE, HL or stack pointer (SP). Only higher order register is to

be specified within the instruction.

Operation : rp ¬ rp – 1

Example : DE = 1020H
DCX D ; This instruction will decrement the contents of DE register pair
(1020H) by one and store the result (1020 – 1 = 101FH) in the
same, DE register pair.

2.2.3 Logic Group

1. ANA r This instruction logically ANDs the contents of the specified register
with the contents of accumulator and stores the result in the
accumulator. Each bit in the accumulator is logically ANDed with the
corresponding bit in register r, i.e. D0 bit in A with D0 bit in
register r, D1 in A with D1 in r and so on upto D7 bit. The register r
is 8-bit general purpose register such as A, B, C, D, E, H and L.

Operation : A¬ AÙr

Example : A = 10101010 (AAH), B = 00001111 (0FH)

ANA B ; This instruction will logically AND the contents of B register with
the contents of accumulator. It will store the result (0AH) in the
accumulator.

1010 1010
0000 1111
————————
0 0 0 0 1 0 1 0 = 0AH
2. ANA M This instruction logically ANDs the contents of memory location
pointed by HL register pair with the contents of accumulator. The
result is stored in the accumulator. The HL register pair is used as a
memory pointer.
Operation : A¬ AÙM
Example : A = 01010101 = (55H), HL = 2050H(2050H) ® 10110011 = (B3H)
ANA M ; This instruction will logically AND the contents of memory location
pointed by HL register pair (B3H) with the contents of accumulator
0101 0101
(55H). It will store the result (11H) in the accumulator.
1011 0011
–––––––––––––––
0 0 0 1 0 0 0 1 = 11H
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3. ANI data This instruction logically ANDs the 8 bit data given in the instruction
with the contents of the accumulator and stores the result in the
accumulator.
Operation : A ¬ A Ù data (8)

Example : A = 1011 0011 = (B3H)

ANI 3FH ; This instruction will logically AND the contents of accumulator
(B3H) with 3FH. It will store the result (33H) in the accumulator.
1011 0011
0011 1111
————————
0 0 1 1 0 0 1 1 = 33H
The AND operation clears bits of a binary number. The task of clearing a bit in a
binary number is called masking. The Fig. 2.1 shows the process of masking.

X X X X X X X X Unknown 8-bit binary number

1 1 1 1 0 0 0 0 Masking pattern

X X X X 0 0 0 0 Result

Masked bits

Fig. 2.1 Masking using AND operation

4. XRA r This instruction logically XORs the contents of the specified register
with the contents of accumulator and stores the result in the
accumulator. The register r is 8-bit general purpose register such as
A, B, C, D, E, H and L.
Operation : A¬ AÅ r
Example : A = 1010 1010 (AAH), C = 0010 1101 (2DH)
XRA C ; This instruction will logically XOR the contents of C register with
the contents of accumulator. It will store the result (87H) in the
1010 1010
0010 1101 accumulator.
—————————
1 0 0 0 0 1 1 1 = (87H)

5. XRA M This instruction logically XORs the contents of memory location

pointed by HL register pair with the contents of accumulator. The
HL register pair is used as a memory pointer.
Operation : A¬ AÅ M

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Example : A = 0101 0101 = (55H), HL = 2050H (2050H) ® 1011 0011 =(B3H)

XRA M ; This instruction will logically XOR the contents of memory location
pointed by HL register pair (2050H) i.e. data B3H with the contents
01 0 1 0 1 0 1
of accumulator (55H). It will store the result (E6H) in the
10 1 1 0 0 1 1
———————— accumulator.
1 1 1 0 0 1 1 0 = E6H
6. XRI data This instruction logically XORs the 8 bit data given in the instruction
with the contents of the accumulator and stores the result in the
accumulator.

Operation : A ¬ A Å data
Example : A = 10110011 = (B3H)
XRI 39H ; This instruction will logically XOR the contents of accumulator
1011 0011 (B3H) with 39H. It will store the result (8AH) in the accumulator.
00 1 1 1 0 0 1
————————
1 0 0 0 1 0 1 0 = 8AH
The XOR instruction is used if some bits of a register or memory location must be
inverted. This instruction allows part of a number to be inverted or complemented. This is
illustrated in Fig. 2.2.

X X X X X X X X Unknown 8-bit binary number

+ 0 0 0 0 1 1 1 1 Pattern for inverting lower 4-bits

X X X X X X X X Result

Inverted bits
Fig. 2.2 Inversion of part of a number using XOR operation
7. ORA r This instruction logically ORs the contents of specified register with
the contents of accumulator and stores the result in the accumulator.
Each bit in the accumulator is ORed with corresponding bit in
register r. i.e. D0 bit in accumulator is ORed with D 0 bit in register r,
D1 in A with D1 in r and so on upto D7 bit. The register r is 8-bit
general purpose register such as A, B, C, D, E, H and L.
Operation : A¬ AÚ r

Example : A = 1010 1010 (AAH), B = 0001 0010 (12H)

ORA B ; This instruction will logically OR the contents of B register with
1010 1010 the contents of accumulator. It will store the result (BAH) in the
0001 0010 accumulator.
—————————
1011 1010= BAH
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8. ORA M This instruction logically ORs the contents of memory location

pointed by HL register pair with the contents of accumulator. The
result is stored in the accumulator. The HL register pair is used as a
memory pointer.
Operation : A¬ AÚ M
Example : A = 0101 0101 = (55H) HL = 2050H
(2050H) ® 1011 0011 = (B3H)
ORA M ; This instruction will logically OR the contents of memory location
pointed by HL register pair (B3H) with the contents of accumulator
0101 0101
(55H). It will store the result (F7H) in the accumulator.
1011 0011
————————
1 1 1 1 0 1 1 1 = F7H
9. ORI data This instruction logically ORs the 8 bit data given in the instruction
with the contents of the accumulator and stores the result in the
accumulator.

Operation : A Ú data (8)

Example : A = 1011 0011 = (B3H)
ORI 08H ; This instruction will logically OR the contents of accumulator (B3H)
1 011 0011 with 08H. It will store the result (BBH) in the accumulator.
0 000 1000
——————-—-
1 0 1 1 1 0 1 1 = BBH
The OR instruction is used to set (make one) any bit in the binary number. This is
illustrated in Fig. 2.3.

X X X X X X X X Unknown 8-bit binary number

+ 1 1 1 1 0 0 0 0 Setting pattern

1 1 1 1 X X X X Result

Set bits

Fig. 2.3 Setting bit/s using OR operation

10. CMP r This instruction subtracts the contents of the specified register from
contents of the accumulator and sets the condition flags as a result of
the subtraction. It sets zero flag if A = r and sets carry flag if A < r.
The register r is 8-bit general purpose register such as A, B, C, D, E,
H and L.

Operation : A– r
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Example : A = 1011 1000 (B8H) and D = 1011 1001 (B9H)

CMP D ; This instruction will compare the contents of D register with the
contents of accumulator. Here A < D so carry flag will set after the
execution of the instruction.

11. CMP M This instruction subtracts the contents of the memory location
specified by HL register pair from the contents of the accumulator
and sets the condition flags as a result of subtraction. It sets zero flag
if A = M and sets carry flag if A < M. The HL register pair is used
as a memory pointer.

Operation : A – M

Example : A = 1011 1000 (B8H), HL = 2050H and (2050H) = 1011 1000 (B8H)
CMP M ; This instruction will compare the contents of memory location
(B8H) and the contents of accumulator. Here A = M so zero flag
will set after the execution of the instruction.

12. CPI data This instruction subtracts the 8 bit data given in the instruction from
the contents of the accumulator and sets the condition flags as a
result of subtraction. It sets zero flag if A = data and sets carry flag
if A < data.

Operation : A – data (8)

Example : A = 1011 1010 = (BAH)

CPI 30H ; This instruction will compare 30H with the contents of accumulator
(BAH). Here A > data so zero and carry both flags will reset after
the execution of the instruction.

13. STC This instruction sets carry flag = 1

Operation : CY ¬ 1

Example : Carry flag = 0

STC ; This instruction will set the carry flag = 1

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14. CMC This instruction complements the carry flag.

Operation : CY ¬ CY

Example : Carry flag = 1

CMC ; This instruction will complement the carry flag i.e. carry flag = 0

15. CMA This instruction complements each bit of the accumulator.

Operation : A ¬A

Example : A = 1000 1000 = 88H

CMA ; This instruction will complement each bit of accumulator
A = 0111 0111 = 77H

2.2.4 Rotate Group

1. RLC This instruction rotates the contents of the accumulator left by one
position. Bit B7 is placed in B0 as well as in CY.

Operation :

Before Execution
CY B7 B6 B5 B4 B3 B2 B1 B0

After Execution

B7 B6 B5 B4 B3 B2 B1 B0 B7

Example : A = 01010111 (57H) and CY = 1

RLC ; After execution of the instruction the accumulator contents will be
(1010 1110) AEH and carry flag will reset.

2. RRC This instruction rotates the contents of the accumulator right by one
position. Bit B0 is placed in B7 as well as in CY.

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Operation :

Before execution

B7 B6 B5 B4 B3 B2 B1 B0 CY

After execution

B0 B7 B6 B5 B4 B3 B2 B1 B0

Example : A = 1001 1010 (9AH) and CY = 1

RRC ; After execution of the instruction the accumulator contents will be
(0100 1101) 4DH and carry flag will reset.
3. RAL This instruction rotates the contents of the accumulator left by one
position. Bit B7 is placed in CY and CY is placed in B0.

Operation :

Before execution

CY B7 B6 B5 B4 B3 B2 B1 B0

After execution

B7 B6 B5 B4 B3 B2 B1 B0 CY

Example : A = 10101101 (ADH) and CY = 0

RAL ; After execution of the instruction accumulator contents will be
(0101 1010) 5AH and carry flag will set.

4. RAR This instruction rotates the contents of the accumulator right by one
position. Bit B0 is placed in CY and CY is placed in B7.

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Operation :
Before execution

B7 B6 B5 B4 B3 B2 B1 B0 CY

After execution

CY B7 B6 B5 B4 B3 B2 B1 B0

Example : A = 1010 0011 (A3H) and CY = 0

RAR ; After execution of the instruction accumulator contents will be
(0101 0001) 51H and carry flag will set.

2.2.5 Stack Operations April/May-04, 08; May/June-07, Nov./Dec.-07, 09

The stack is a portion of read/write memory set aside by the user for the purpose of
storing information temporarily. When the information is written on the stack, the
operation is called PUSH. When the information is read from stack, the operation is called
POP.
The microprocessor stores the information, much like stacking plates. Using this
analogy of stacking plates it is easy to illustrate the stack operation.
Fig. 2.4 shows the stacked plates. Here, we realize that if it is
3
desired to take out the first stacked plate we will have to remove
2 all plates above the first plate in the reverse order. This means
1 that to remove first plate we will have to remove the third plate,
then the second plate and finally the first plate. This means that,
Fig. 2.4 Stacked the first information pushed on to the stack is the last
plates information popped off from the stack. This type of operation is
known as a first in, last out (FILO). This stack is implemented
with the help of special memory pointer register. The special pointer register is called the
stack pointer. During PUSH and POP operation, stack pointer register gives the address of
memory where the information is to be stored or to be read. The stack pointer’s contents
are automatically manipulated to point to stack top. The memory location currently
pointed by stack pointer is called top of stack.

1. PUSH rp This instruction decrements stack pointer by one and copies the
higher byte of the register pair into the memory location pointed by
stack pointer. It then decrements the stack pointer again by one and
copies the lower byte of the register pair into the memory location
pointed by stack pointer. The rp is 16-bit register pair such as BC,
DE, HL. Only higher order register is to be specified within the
instruction.
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Operation : SP ¬ SP – 1, (SP) ¬ rpH, SP ¬ SP – 1, (SP) ¬ rpL.

SP Lower byte

SP Higher byte Higher byte

SP

(a) Initial Position (b) Decrements SP and (c) Decrements SP and

stores higher byte stores lower byte
Fig. 2.5 Steps involved in PUSH Operation

Example : SP = 2000H, DE = 1050H.

PUSH D ; This instruction will decrement the stack pointer (2000H) by one
(SP = 1FFFH) and copies the contents of D register (10H) into the
memory location 1FFFH. It then decrements the stack pointer again
by one (SP = 1FFEH) and copies the contents of E register (50H)
into the memory location 1FFEH.

Before Execution After Execution

SP 2000 1FFEH SP 1FFE 1FFEH 50

B C B C 10
1FFFH PUSH D 1FFFH
D 10 E 50 D 10 E 50
2000H 2000H
H L H L

2. PUSH PSW This instruction decrements stack pointer by one and copies the
accumulator contents into the memory location pointed by stack
pointer. It then decrements the stack pointer again by one and copies
the flag register into the memory location pointed by the stack
pointer.

Operation : SP ¬ SP – 1
(SP) ¬ A
SP ¬ SP – 1
(SP) ¬ Flag register
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Example : SP = 2000H, A = 20H, Flag register = 80H

PUSH PSW ; This instruction decrements the stack pointer (SP = 2000H) by one
(SP = 1FFFH) and copies the contents of the accumulator (20H)
into the memory location 1FFFH. It then decrements the stack
pointer again by one (SP = 1FFEH) and copies the contents of the
flag register (80H) into the memory location 1FFEH.

Before Execution After Execution

2000 1FFEH 1FFE 1FFEH 80

20 80 PUSH PSW 20 80
1FFFH 1FFFH 20

2000H 2000H

3. POP rp This instruction copies the contents of memory location pointed by

the stack pointer into the lower byte of the specified register pair and
increments the stack pointer by one. It then copies the contents of
memory location pointed by stack pointer into the higher byte of the
specified register pair and increments the stack pointer again by one.
The rp is 16-bit register pair such as BC, DE, HL. Only higher order
register is to be specified within the instruction.

Operation : rpL ¬ (SP)

SP ¬ SP + 1
rpH ¬ (SP), SP ¬ SP + 1

SP Lower byte Lower byte Lower byte

Higher byte SP Higher byte Higher byte

SP

(a) Initial position, (b) Increments SP and (c) Increments SP

reads lower byte reads higher byte
Fig. 2.6 Steps Involved in POP Operation
Example : SP = 2000H, (2000H) = 30H, (2001H) = 50H
POP B ; This instruction will copy the contents of memory location pointed
by stack pointer, 2000H (i.e. data 30H) into the C register. It will
then increment the stack pointer by one, 2001H and will copy the
contents of memory location pointed by stack pointer, 2001H
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(i.e. data 50H) into B register, and increment the stack pointer
again by one.

Before Execution After Execution

2000 2000H 30 2002 2000H 30

POP B
50 50 30 50
2001H 2001H

2002H 2002H

4. POP PSW This instruction copies the contents of memory location pointed by
the stack pointer into the flag register and increments the stack
pointer by one. It then copies the contents of memory location
pointed by stack pointer into the accumulator and increments the
stack pointer again by one.

Operation : Flag register ¬ (SP)

SP ¬ SP + 1
A ¬ (SP)
SP ¬ SP + 1

Example : SP = 2000H, (2000H) = 30H, (2001H) = 50H

POP PSW ; This instruction will copy the contents of memory location pointed
by the stack pointer, 2000H (i.e. data 30H) into the flag register. It
will then increment the stack pointer by one, 2001H and will copy
the contents of memory location pointed by stack pointer into the
accumulator and increment the stack pointer again by one.
Before Execution After Execution

2000 2000H 30 2002 2000H 30

POP PSW
50 50 30 50
2001H 2001H

2002H 2002H

5. SPHL This instruction copies the contents of HL register pair into the stack
pointer. The contents of H register are copied to higher order byte of
stack pointer and contents of L register are copied to the lower byte
of stack pointer.

Operation : SP ¬ HL
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Example : HL = 2500H
SPHL ; This instruction will copy 2500H into stack pointer. So after
execution of instruction stack pointer contents will be 2500H.

6. XTHL This instruction exchanges the contents of memory location pointed

by the stack pointer with the contents of L register and the contents
of the next memory location with the contents of H register. This
instruction does not modify stack pointer contents.

Operation : L « (SP)
H « (SP + 1)

Example : HL = 3040H and SP = 2700H, (2700H) = 50H, (2701H) = 60H

XTHL ; This instruction will exchange the contents of L register(40H) with
the contents of memory location 2700H (i.e. 50H) and the contents
of H register (30H) with the contents of memory location 2701H
(i.e. 60H).

Before Execution After Execution

2700 2700H 50 2700 2700H 40

30 40 60 XTHL 60 50 30
2701H 2701H

2702H 2702H

2.2.6 Branch Group May/June-07, Nov./Dec.-07, 09, April/May-10

1. JMP addr This instruction loads the PC with the address given within the
instruction and resumes the program execution from this location.

Operation : PC ¬ addr

Example :
JMP 2000H ; This instruction will load PC with 2000H and processor will fetch
next instruction from this address.

2. Jcond addr This instruction causes a jump to an address given in the instruction
if the desired condition occurs in the program before the execution of
the instruction. The Table 2.1 shows the possible conditions for
jumps.

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Instruction code Description Condition for jump

JC Jump on carry CY = 1
JNC Jump on not carry CY = 0
JP Jump on positive S = 0
JM Jump on minus S = 1
JPE Jump on parity even P = 1
JPO Jump on parity odd P = 0
JZ Jump on zero Z = 1
JNZ Jump on not zero Z = 0

Table 2.1 Conditional jumps

Example : Carry flag = 1

JC 2000H ; This instruction will cause a jump to an address 2000H i.e.
program counter will load with 2000H since CF =1.

3. CALL addr A subroutine is a group of instructions, performs a particular subtask

which is executed number of times. It is written separately. The
microprocessor executes this subroutine by transferring program
control to the subroutine program. After completion of subroutine
program execution, the program control is returned back to the main
program.
The CALL instruction is used to transfer program control to a
subprogram or subroutine. This instruction pushes the current PC
contents onto the stack and loads the given address into the PC.
Thus the program control is transferred to the address given in the
instruction. Stack pointer is decremented by two.
When the subroutine is called, the program control is transferred
from calling program to the subroutine. After execution of subroutine
it is necessary to transfer program control back to the calling
program. To do this processor must remember the address of the
instruction next to the CALL instruction. Processor saves this address
on the stack when the CALL instruction is executed.

Note : The stack is a part of read/write memory set aside for storing
intermediate results and addresses.

Operation : (SP – 1) ¬ PCH

(SP – 2) ¬ PCL
SP ¬ SP – 2
PC ¬ addr
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Example : Stack pointer = 3000H.

6000H CALL 2000H ; This instruction will store the address of instruction next
to CALL (i.e. 6003H) on the stack and load PC with
2000H.
6003H —-
Before Execution After Execution

3000 2FFEH 2FFE 2FFEH 03

CALL 2000H
6000 2000 60
2FFFH 2FFFH

3000H 3000H

4. C cond addr This instruction calls the subroutine at the given address if a
specified condition is satisfied. Before call it stores the address of
instruction next to the call on the stack and decrements stack pointer
by two. The Table 2.2 shows the possible conditions for calls.
Instruction code Description Condition for CALL
CC Call on carry CY = 1
CNC Call on not carry CY = 0
CP Call on positive S = 0
CM Call on minus S = 1
CPE Call on parity even P = 1
CPO Call on parity odd P = 0
CZ Call on zero Z = 1
CNZ Call on not zero Z = 0

Table 2.2 Conditional calls

Operation : If condition true (SP – 1) ¬ PCH

(SP – 2) ¬ PCL
PC ¬ addr
else PC ¬ PC + 3

Example : Carry flag = 1, stack pointer = 4000H.

2000H CC 3000H ; This instruction will store the address of the next instruction
i.e. 2003H on the stack and load the program counter with
3000H, since the carry flag is set.

5. RET This instruction pops the return addr (address of the instruction next
to CALL in the main program) from the stack and loads program
counter with this return address. Thus transfers program control to
the instruction next to CALL in the main program.
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Operation : PCL ¬ (SP)

PCH ¬ (SP+1)
SP ¬ SP + 2

Example : If SP = 27FDH and contents on the stack are as shown then

SP ® 27FD 00

27FE 62

27FF

RET ; This instruction will load PC with 6200H and it will transfer
program control to the address 6200H. It will also increment the
stack pointer by two.
Before Execution After Execution

SP 27FD 27FDH 00 SP 27FF 27FDH 00

RET
PC 27FEH 62 PC 6200 62
27FEH

27FFH 27FFH

6. R condition This instruction returns the control to the main program if the
specified condition is satisfied. Table 2.3 shows the possible
conditions for return.
Instruction code Description Condition for RET
RC Return on carry CY = 1
RNC Return on not carry CY = 0
RP Return on positive S = 0
RM Return on minus S = 1
RPE Return on parity even P = 1
RPO Return on parity odd P = 0
RZ Return on zero Z = 1
RNZ Return on not zero Z = 0
Table 2.3 Conditions for return

7. PCHL This instruction loads the contents of HL register pair into the
program counter. Thus the program control is transferred to the
location whose address is in HL register pair.

Operation : PC ¬ HL

Example : HL = 6000H
PCHL ; This instruction will load 6000H into the program counter.
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8. RST n This instruction transfers the program control to the specific memory
address as shown in Table 2.4. This instruction is like a fixed address
CALL instruction. These fixed addresses are also referred to as vector
addresses. The processor multiplies the RST number by 8 to calculate
these vector addresses. Before transferring the program control to the
instruction following the vector address RST instruction saves the
current program counter contents on the stack like CALL instruction
Instruction code Vector Address
RST 0 0 ´ 8 = 0000H
RST 1 1 ´ 8 = 0008H
RST 2 2 ´ 8 = 0010H
RST 3 3 ´ 8 = 0018H
RST 4 4 ´ 8 = 0020H
RST 5 5 ´ 8 = 0028H
RST 6 6 ´ 8 = 0030H
RST 7 7 ´ 8 = 0038H
Table 2.4 Vector addresses for return instructions

Operation : (SP – 1) ¬ PCH

(SP – 2) ¬ PCL
SP ¬ SP – 2, PC ¬ (n ´ 8) in hex

Example : SP = 3000H
2000H RST 6 ; This instruction will save the current contents of the program
counter (i.e. address of next instruction 2001H) on the stack and it
will load the program counter with vector address
6 ´ 8= 4810= 30H) 0030H.

2.2.7 Input/Output April/May-10

1. IN addr(8-bit) This instruction copies the data at the port whose address is specified
in the instruction into the accumulator.

Operation : A ¬ (addr)

Example : Port address = 80H, data stored at port address 80H, (80H) = 10H
IN 80H ; This instruction will copy the data stored at address 80H, i.e. data
10H in the accumulator.

2. OUT addr(8-bit) This instruction sends the contents of accumulator to the output port
whose address is specified within the instruction.
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Operation : (addr) ¬ A

Example : A = 40H
OUT 50H ; This instruction will send the contents of accumulator(40H) to the
output port whose address is 50H.

2.2.8 Machine Control Group Nov./Dec.-08

1. EI This instruction sets the interrupt enable flip flop to enable

interrupts. When the microprocessor is reset or after interrupt
acknowledge, the interrupt enable flip-flop is reset. This instruction is
used to reenable the interrupts.

Operation : IE (F/F) ¬ 1

2. DI This instruction resets the interrupt enable flip-flop to disable

interrupts. This instruction disables all interrupts except TRAP since
TRAP is non-maskable interrupt (cannot be disabled. It is always
enabled).

Operation : IE (F/F) ¬ 0

3. NOP No operation is performed.

4. HLT This instruction halts the processor. It can be restarted by a valid

interrupt or by applying a RESET signal.

5. SIM This instruction masks the interrupts as desired. It also sends out
serial data through the SOD pin. For this instruction command byte
must be loaded in the accumulator.

D7 D6 D5 D4 D3 D2 D1 D0

SOD SOE X RST 7.5 MSE M 7.5 M 6.5 M 5.5

Mask RST 5.5

Serial output data 1 - Mask
either 1 or 0 0 - Unmask
Serial output enable
0- Disable Mask RST 6.5
1 - Enable 1 - Mask
0 - Unmask
Reset RST 7.5 flip-flop
Mask RST 7.5
Mask set enable. It should be 1 - Mask
1 to make D2-D0 effective 0 - Unmask

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Example : i) A = 0EH
D7 D6 D5 D4 D3 D2 D1 D0
Register A
SOD SOE X RST7.5 MSE M7.5 M6.5 M5.5
0 0 0 0 1 1 1 0 = 0EH

SIM ; This instruction will mask RST 7.5 and RST 6.5 interrupts where as
RST 5.5 interrupt will be unmasked. It will also disable serial
output.

6. RIM : This instruction copies the status of the interrupts into the
accumulator. It also reads the serial data through the SID pin.

D7 D6 D5 D4 D3 D2 D1 D0

SID I 7.5 I 6.5 I 5.5 IE M 7.5 M 6.5 M 5.5

Serial input data Set if RST 5.5 is masked

Set if RST 7.5 is pending Set if RST 6.5 is masked
Set if RST 6.5 is pending
Set if RST 7.5 is masked
Set if RST 5.5 is pending
Set if interrupt enable flip-flop is set

Example :
RIM ; After execution of RIM instruction if the contents of accumulator
are 4BH then we get following information.
D7 D6 D5 D4 D3 D2 D1 D0

SID I 7.5 I 6.5 I 5.5 IE M7.5 M6.5 M5.5 Register A

0 1 0 0 1 0 1 1 = 4BH

i.e. a) RST 7.5 is pending

b) RST 5.5 and RST 6.5 are masked
c) Interrupt Enable flip-flop is set
d) Serial i/p data is zero.

2.3 Addressing Modes

Part of the programming flexibility for each microprocessor is the number and
different kind of ways the programmer can refer to data stored in the memory. The
different ways that a microprocessor can access data are referred to as addressing modes.
The 8085 has 5 addressing modes. These are :
1. Immediate 2. Register
3. Direct 4. Indirect
5. Implied
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1. Immediate addressing mode :

In an immediate addressing mode, 8 or 16 bit data can be specified as a part of
instruction. In 8085, the instructions having ‘I’ letter fall under this category. ‘I’ indicates
immediate addressing mode.

Example :
MVI A, 20H ; Moves 8 bit immediate data (20H) into accumulator
MVI M, 30H ; Moves 8 bit immediate data (30H) into the
; memory location pointed by HL register pair.
LXI SP, 2700H ; Moves 16 bit immediate data (2700H) into SP.
LXI D, 10FFH ; Moves 16 bit immediate data (10FFH) into DE
; register pair ( D = 10H and E = FFH).

2. Register addressing mode :

The register addressing mode specifies the source operand, destination operand, or
both to be contained in an 8085 registers. This results in faster execution, since it is not
necessary to access memory locations for operands.

Example :
MOV A, B ; Moves the contents of register B into the accumulator.
SPHL ; Moves the contents of HL register pair into stack pointer.
ADD C ; Adds the contents of register C into the contents of accumulator
; and stores result in the accumulator.

3. Direct addressing mode :

The direct addressing mode specifies the 16 bit address of the operand within the
instruction itself. The second and third bytes of instruction contain this 16 bit address.

Example :
LDA 2000H ; Loads the 8 bit contents of memory location
; 2000H into the accumulator.
SHLD 3000H ; Stores the HL register pair into two consecutive memory
; locations. Lower byte i.e. the contents of L register into memory
; location 3000H and higher byte i.e. the contents of H register
; into memory location 3001H.

4. Indirect addressing mode :

In indirect addressing mode, the memory address where the operand located is
specified by the contents of a register pair.

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Example :
LDAX B ; Loads the accumulator with the contents of
; memory location pointed by BC register pair.
MOV M, A ; Stores the contents of accumulator into the
; memory location pointed by HL register pair.

5. Implied Addressing Mode :

In implied addressing mode, opcode specifies the address of the operands.

Example :
CMA ; Complements contents of accumulator.
RAL ; Rotates the contents of accumulator left through carry.
Note : Many of the advanced processors support addressing mode called index
addressing mode. In this mode, the address of the operand within the memory is
generated by adding the offset/displacement to the register specified in the instruction.
The offset/displacement is also a part of the instruction. In 8085 such addressing mode is
not available. However, we can implement such kind of program structure, by using
memory pointer (HL register), any other register pair and a instruction sequence given
below :
LXI H, Base_addr ; Loads the base address
LXI B, Offset/Displacement ; Loads the offset or displacement
DAD B ; Gives the addition of HL and BC in HL register pair.
MOV A, M ; Load the data from memory in the accumulator
By incrementing or decrementing contents of BC register or loading another contents,
we can change the index/offset/displacement.

2.4 Instruction Set Summary

Data Transfer Group

Sr. Instruction Operation Flags No. of Addressing mode

No. affected bytes

1. MVI r, data (8) r ¬ data(8) No 2 Immediate

2. MVI M, data (8) (HL) ¬ data (8) No 2 Immediate and Indirect

3. MOV rd, rs rd ¬ rs No 1 Register

4. MOV M, rs (HL) ¬ rs No 1 Indirect

5. MOV rd, M rd ¬ (HL) No 1 Indirect

6. LXI rp, data (16) rp ¬ data (16) No 3 Immediate

7. STA addr (addr) ¬ A No 3 Direct

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8. LDA addr A ¬ (addr) No 3 Direct

9. SHLD addr (addr) ¬ L No 3 Direct

(addr + 1) ¬ H

10. LHLD addr L ¬ (addr) No 3 Direct

HL ¬ (addr+1)

11. STAX rp (rp) ¬ A No 1 Indirect

12. LDAX rp A ¬ (rp) No 1 Indirect

13 XCHG H « D, L « E No 1 Register

Arithmetic Group

Sr. Instruction Operation Flags affected No. of Addressing

No. bytes mode

1. ADD r A ¬A + r All 1 Register

2. ADD M A ¬ A + (HL) All 1 Register Indirect

3. ADI data(8) A ¬ A + data (8) All 2 Immediate

4. ADC r A ¬ A + r + CY All 1 Register

5. ADC M A ¬ A + (HL) + CY All 1 Register indirect

6. ACI data (8) A ¬ A + data(8) + CY All 2 Immediate

7. DAD rp HL ¬ HL + rp CY 1 Register

8. Sub r A ¬A – r All 1 Register

9. Sub M A ¬ A – (HL) All 1 Register Indirect

10. SUI data (8) A ¬ A – data (8) All 2 Immediate

11. SBB r A ¬ A – r – CY All 1 Register

12. SBB M A ¬ A – (HL) – CY All 1 Register Indirect

13. SBI data A ¬ A – data(8) – CY All 2 Immediate

14. DAA A(BCD) ¬ A(Binary) All 1 Implied

15. INR r r ¬r + 1 S, Z, P, A, C 1 Register

16 INR M (HL) ¬ (HL) + 1 S, Z, P, A, C 1 Register Indirect

17. INX rp rp ¬ rp + 1 No 1 Register

18. DCR r r ¬r – 1 S, Z, P, A, C 1 Register

19. DCR M (HL) ¬ (HL) – 1 S, Z, P, A, C 1 Register Indirect

20. DCX rp rp ¬ rp – 1 No 1 Register

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Logic Group

1. ANA r A ¬A Ùr All, CY = 0 AC = 1 1 Register

2. ANA M A ¬ A Ù (HL) All, CY = 0 AC = 1 1 Register Indirect

3. ANI data(8) A ¬ A Ù data(8) All, CY = 0 AC = 1 2 Immediate

4. XRA r A ¬A Å r All, CY = 0 AC = 0 1 Register

5. XRA M A ¬ A Å (HL) All, CY = 0 AC = 0 1 Register Indirect

6. XRI data (8) A ¬ A Å data (8) All, CY = 0 AC = 0 2 Immediate

7. ORA r A ¬A Úr All, CY = 0 AC = 0 1 Register

8. ORA M A ¬ A Ú (HL) All, CY = 0 AC = 0 1 Register Indirect

9. ORI data (8) A ¬ A Ú data (8) All, CY = 0 AC = 0 2 Immediate

10. CMP r A – r All 1 Register

11. CMP M A – (HL) All 1 Register Indirect

12. CPI data (8) A – data (8) All 2 Immediate

13. STC CY ¬ 1 CY 1 Implied

14. CMC CY ¬ CY CY 1 Implied

15. CMA A ¬A No 1 Implied

Rotate Group

Sr. Instruction Operation Flags No. of Addressing

No. affected bytes mode

1. RLC Bi + 1 ¬ Bi, B0 ¬ B7 CY ¬ B7 CY 1 Implied

2. RRC Bi – 1 ¬ Bi, B7 ¬ B0 CY ¬ B0 CY 1 Implied

3. RAL Bi + 1 ¬ Bi, B0 ¬ CY CY ¬ B7 CY 1 Implied

4. RAR Bi – 1 ¬ Bi, B7 ¬ CY CY ¬ B0 CY 1 Implied

Branch Group

Sr. Instruction Operation Flags No. of Addressing

No. affected bytes mode

1. JMP addr PC ¬ addr No 3 Immediate

2. J cond addr If condition true PC ¬ addr No 3 Immediate

3. PCHL PC ¬ HL No 1 Register

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4. CALL addr (SP – 1) ¬ PCH No 3 Immediate

(SP – 2) ¬ PCL
SP ¬ SP – 2
PC ¬ addr

5. CALL cond If condition true No 3 Immediate

addr (SP – 1) ¬ PCH
(SP – 2) ¬ PCL
SP ¬ SP – 2
PC ¬ addr

6. RET PCL ¬ (SP) No 1 Register Indirect

PCH ¬ (SP + 1)
SP ¬ SP + 2

7. RET cond If condition true No 1 Register Indirect

PCL ¬ (SP)
PCH ¬ (SP + 1)
SP ¬ SP + 2

8. RST n (SP – 1) ¬ PCH No 1 Register Indirect

(SP – 2) ¬ PCL
SP ¬ SP – 2
PC ¬ (n ´ 8) in hex

Stack Group

Sr. Instruction Operation Flags No. of Addressing

No. affected bytes mode

1. PUSH rp SP ¬ SP – 1 No 1 Register Indirect

(SP) ¬ rpH
SP ¬ SP – 1
(SP) ¬ rpL

2. PUSH PSW SP ¬ SP – 1 No 1 Register Indirect

(SP) ¬ A
SP ¬ SP – 1
(SP) flag register

3. POP rp rpL ¬ (SP) No 1 Register Indirect

SP ¬ SP + 1
rPH ¬ (SP)
SP ¬ SP + 1

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4. POP PSW flag register ¬ (SP) No 1 Register Indirect

SP ¬ SP + 1
A ¬ (SP)
SP ¬ SP + 1

5. SPHL SP ¬ HL No 1 Register

6. XTHL L « (SP) No 1 Register Indirect

H « (SP + 1)

Input/Output Group

Sr. Instruction Operation Flags No. of Addressing

No. affected bytes mode

1. IN addr (8) A ¬ (addr) No 2 Direct

2. OUT addr (8) (addr) ¬ A No 2 Direct

Machine Control Group

Sr. Instruction Operation Flags No. of Addressing

No. affected bytes mode

1. EI IE(F/F) ¬ 1 No 1 –

2. DI IE(F/F) ¬ 0 No 1 –

3. NOP No operation No 1 –

4. HLT Halts the processor No 1 –

5. SIM Serial interrupt mask No 1 –

6. RIM Read interrupt mask No 1 –

2.5 Assembly Language Programming

A program is a set of instructions arranged in the specific sequence to do the specific
task. It tells the microprocessor what it has to do. The process of writing the set of
instructions which tells the microprocessor what to do is called “Programming”. In other
words, we can say that programming is the process of telling the processor exactly how to
solve a problem. To do this, the programmer must “speak” to the processor in a language
which processor can understand.

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2.5.1 Steps Involved in Programming

· Specifying the problem : The first step in the programming is to find out which
task is to be performed. This is called specifying the problem. If the programmer
does not understand what is to be done, the programming process cannot begin.
· Designing the problem-solution : During this process, the exact step by step
process that is to be followed (program logic) is developed and written down.
· Coding : Once the program is specified and designed, it can be implemented.
Implementation begins with the process of coding the program. Coding the
program means to tell the processor the exact step by step process in its
language. Each processor has a set of instructions. Programmer has to choose
appropriate instructions from the instruction set to build the program.
· Debugging : Once the program or a part of program is coded, the next step is
debugging the code. Debugging is the process of testing the code to see if it does
the given task. If program is not working properly, debugging process helps in
finding and correcting errors.

To write a program, programmer should know :

· How to develop program logic?
· How to tell the program to the processor?
· How to code the program?
· How to test the program?

2.5.2 Flowchart
To develop the programming logic programmer has to
write down various actions which are to be performed in
proper sequence. The flow chart is a graphical tool that
allows programmer to represent various actions which are to
be performed. The graphical representation is very useful for
clear understanding of the programming logic.
The Fig. 2.7 shows the graphic symbols used in the
flowchart.
Oval : It indicates start or stop operation.
Arrow : It indicates flow with direction.
Parallelogram : It indicates input/output operation.
Rectangle : It indicates process operation.
Diamond : It indicates decision making operation.
A Double sided Rectangle : It indicates execution of
Fig. 2.7 Graphic symbols pre-defined process (subroutine).
used in flowchart Circle with alphabet : It indicates continuation.
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A : Any alphabet
The Fig. 2.8 shows sample flowchart.

2.5.3 Assembly Language Program

Start

Input process
parameters

Call subroutine

Process

Display results

Stop

Fig. 2.8 Sample flowchart

Let us define a program statement as 'write an assembly language program to add two
numbers'. The three tasks are involved in this program :
· Load two hex numbers
· Add numbers and
· Store the result in the memory
These tasks can be symbolically presented as flow chart, as shown in the Fig. 2.9.
(See Fig. 2.9 on next page)
Next job is to find the suitable 8085 assembly language instruction/s for each task.
These instructions are as follows :

Task 1 instructions :
MVI A, 20H ; Load 20H as a first number in register A
MVI B, 40H ; Load 40H as a second number in register B
Task 2 instruction :
ADD B ; Add two numbers and save result in register A
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Start

Load two hex

numbers

Add
numbers

Store the
result

Stop

Fig. 2.9 Flowchart for addition of two numbers

Task 3 instruction :
STA 2200H ; Store the result in memory location 2000H
HLT ; Stop the program execution
We want to execute three tasks in a sequence, thus writing corresponding instructions
in the same sequence constitutes an assembly language program.

2.5.4 Assembly Language Program to Machine Language Program

Once the assembly language program is ready, it is necessary to convert it in the
machine language program. It is possible to do this by referring the proper hex code for
each assembly instruction from the 8085 instruction set manual. This process is known as
hand assembly and the resulted machine language program is also known as hex code.
Let us see the hex code for our program.

Mnemonics Hex code

MVI A, 20H 3EH ¬ Opcode

20H ¬ Operand
MVI B, 40H 06H ¬ Opcode
40H ¬ Operand

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ADD B 80H ¬ Opcode

STA 2200H 32H ¬ Opcode
00H ¬ Operand (lower byte of address)
22H ¬ Operand (higher byte of address)
HLT 76H ¬ Opcode

2.5.5 Storing Hex Code in the Memory

Once the hex code is ready, it has to be loaded in the memory of specially designed
microprocessor system (Microprocessor training kit) for execution. To perform this task we
should know the address range of read/write memory in the system. Let us assume that
the read/write memory ranges from 2000H to 22FFH. The microprocessor training kit has
keypad to enter the hex code in the memory. It provides a special routines (monitor
program) to enter a hex code byte by byte and execute the program. Typical steps for
storing hex code in the memory from address from address 2000H are as follows :
1. Reset the microprocessor system by pressing the RESET key.
2. Enter into store mode by pressing SET key.
3. Enter the address of the memory 2000H, where the first hex code (starting address
of the program) is to be stored using hex keys.
4. Enter the hex code using hex keys.
5. Increment the memory address by 1 using INC key.
6. Repeat steps 4 and 5 until the last hex code.

2.5.6 Executing the Program

The microprocessor training kit provides a procedure to execute the program. To
activate the procedure we have to enter the starting address of the program (2000H in our
example). To enter this address we have to go into execute mode by pressing GO key and
enter the starting address using hex keys. Once the starting address is entered, the
program can be executed by pressing EXECUTE key. The EXECUTE key procedure loads
the starting address of our program, 2000H into the program counter and program control
is transferred from monitor program to our program.
After this microprocessor reads one hex code at a time, and when it fetches the
complete instruction, it executes that instruction. Then it fetches the next instruction and
this process continues until the last instruction in the program is executed.

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2.6 Programming Examples

Lab Experiment 1 : Store 8-bit data in memory.

Statement : Store the data byte 52H into memory location 2000H.
Program 1 :
A, 52H ; Store 52H in the accumulator
STA 2000H ; Copy accumulator contents at address 2000H
HLT ; Terminate program execution
Program 2 :
LXI H, 2000H ; Load HL with 2000H
MVI M, 52H ; Store 52H in memory location pointed
; by HL register pair (2000H)
HLT ; Terminate program execution
The result of both programs will be the same. In program 1 direct addressing
instruction is used, whereas in program 2 indirect addressing instruction is used.

Lab Experiment 2 : Exchange the contents of memory locations.

Statement : Exchange the contents of memory locations 1000H and 2000H
Program 1 :
LDA 1000H ; Get the contents of memory location 1000H into accumulator
MOV B, A ; save the contents in B register
LDA 2000H ; Get the contents of memory location 2000H into accumulator.
STA 1000H ; Store the contents of accumulator at address 1000H.
MOV A, B ; Get the saved contents back into A register
STA 2000H ; Store the contents of accumulator at address 2000H
HLT ; Terminate program execution
Program 2 :
LXI H, 1000H ; Initialize HL register pair as a pointer
; to memory location 1000H
LXI D, 2000H ; Initialize DE register pair as a pointer
; to memory location 2000H
MOV B, M ; Get the contents of memory location 1000H into B register
LDAX D ; Get the contents of memory location 2000H into A register
MOV M, A ; Store the contents of A register into memory location 1000H
MOV A, B ; Copy the contents of B register into accumulator
STAX D ; Store the contents of A register into memory location 2000H.
HLT ; Terminate program execution
In Program 1 direct addressing instructions are used, whereas in Program 2 indirect
addressing instructions are used.
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Lab Experiment 3 : Add two 8-bit numbers.

Statement : Add the contents of memory locations 2000H and 2001H and place the result
in memory location 2002H.

Flowchart
Sample problem
(2000H) = 14H Start
(2001H) = 89H
Result = 14H + 89H = 9DH
Get the first number

Source program
LXI H, 2000H ; HL points 2000H Get the second number
MOV A, M ; Get first operand
INX H ; HL points 2001H
ADD M ; Add second operand Add two numbers
INX H ; HL points 2002H
MOV M, A ; Store result at 2002H
HLT ; Terminate program execution Store the result

Lab Experiment 4 : Subtract two 8-bit numbers.

End
Statement :Subtract the contents of memory location 2001H
from the memory location 2000H and place the result in
memory location 2002H.
Flowchart
Sample problem
Start
(2000H) = 51H
(2001H) = 19H
Result = 51H – 19H = 38H Get the first number

Source program Get the second number

LXI H, 2000H ; HL points 2000H
MOV A, M ; Get first operand
Subtract second number from first number
INX H ; HL points 2001H
SUB M ; Subtract second operand
INX H ; HL points 2002H Store the result

MOV M, A ; Store result at 2002H

HLT ; Terminate program execution End

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Lab Experiment 5 : Add two 16-bit numbers.

Statement : Add the 16-bit number in memory locations 2000H and 2001H to the 16-bit
number in memory locations 2002H and 2003H. The most significant eight bits of the two
numbers to be added are in memory locations 2001H and 2003H. Store the result in
memory locations 2004H and 2005H with the most significant byte in memory location
2005H.
Sample problem
(2000H) = 15H
(2001H) = 1CH
(2002H) = B7H
(2003H) = 5AH
Result = 1C15 + 5AB7H = 76CCH
(2004H) = CCH
(2005H) = 76H

Flowchart

Start

Get the lower byte of first number

Get the lower byte of second number

Add two lower bytes

Get the higher byte of first number

Get the higher byte of second number

Add two higher bytes and carry

from the previous addition

Store the result

End

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Source Program 1
LHLD 2000H ; Get first 16-bit number in HL
XCHG ; Save first 16-bit number in DE
LHLD 2002H ; Get second 16-bit number in HL
MOV A, E ; Get lower byte of the first number
ADD L ; Add lower byte of the second number
MOV L, A ; Store result in L register
MOV A, D ; Get higher byte of the first number
ADC H ; Add higher byte of the second number with carry
MOV H, A ; Store result in H register
SHLD 2004H ; Store 16-bit result in memory locations 2004H and 2005H.
HLT ; Terminate program execution
Source program 2
LHLD 2000H ; Get first 16-bit number
XCHG ; Save first 16-bit number in DE
LHLD 2002H ; Get second 16-bit number in HL
DAD D ; Add DE and HL
SHLD 2004H ; Store 16-bit result in memory locations 2004H and 2005H.
HLT ; Terminate program execution
In program 1 eight bit addition instructions are used (ADD and ADC) and addition is
performed in two steps. First lower byte addition using ADD instruction and then higher
byte addition using ADC instruction. In program 2 16-bit addition instruction (DAD) is
used.

Lab Experiment 6 : Subtract two 16-bit numbers.

Statement : Subtract the 16-bit number in memory locations 2002H and 2003H from the
16-bit number in memory locations 2000H and 2001H. The most significant eight bits of
the two numbers are in memory locations 2001H and 2003H. Store the result in memory
locations 2004H and 2005H with the most significant byte in memory location 2005H.
Sample problem
(2000H) = 19H
(2001H) = 6AH
(2002H) = 15H
(2003H) = 5CH
Result = 6A19H – 5C15H = 0E04H
(2004H) = 04H
(2005H) = 0EH

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Source program
LHLD 2000H ; Get first 16-bit number in HL
XCHG ; Save first 16-bit number in DE
LHLD 2002H ; Get second 16-bit number in HL
MOV A, E ; Get lower byte of the first number
SUB L ; Subtract lower byte of the second number
MOV L, A ; Store the result in L register
MOV A, D ; Get higher byte of the first number
SBB H ; Subtract higher byte of second number with borrow
MOV H, A ; Store 16-bit result in memory locations 2004H and 2005H.
SHLD 2004H ; Store 16-bit result in memory locations 2004H and 2005H.
HLT ; Terminate program execution.

Flowchart

START

Get the lower byte of first number

Get the lower byte of second number

Subtract lower byte of second

number from lower byte of
first number

Get the higher byte of first number

Get the higher byte of second number

Subtract higher byte of second

number and borrow from the
previous subtraction

Store the result

END

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Lab Experiment 7 : Check results after execution of INR B, INR C and INX B instructions.
Statement : If the contents of B = FFH and C = FFH then after execution of following
instructions give the contents of register B and register C.
Instructions :
1. INR B
2. INR C
3. INX B
1. INR B
B ® FFH
+ 01H
®B
00H
\ B = 00H and C = FFH
2. INR C
C ® FFH
+ 01H
00H ® C
\ B = FFH and C = 00H
3. INX B
BC ® FF FF H
+ 00 01 H
00 00 H ® B C
\ B = 00H and C = 00H

Lab Experiment 8 : Check results after execution of DCR C, DCR B and DCX B instructions.
Statement : If the contents of B = 00H and C = 00H then after execution of following
instructions give the contents of register B and register C.
Instructions :
1. DCR C
2. DCR B
3. DCX B
1. DCR C
C ® 00H
– 01H
FFH ®C
\ B = 00H and C = FFH

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2. DCR B
B ® 00H
– 01H
FFH ® B
\ B = FFH and C = 00H
3. DCX B
BC ® 0 0 0 0 H
– 0 0 0 1 H
F F F F H ® BC
\ B = FFH and C = FFH

Lab Experiment 9 : Find the 1’s complement of a number.

Start
Statement : Find the 1’s complement of the number stored at
memory location 2200H and store the complemented number at
Get the number
memory location 2300H.
Sample problem
Complement the
(2200H) = 55H number
Result = (2300H) = AAH
Source program Store the result
LDA 2200H ; Get the number
CMA ; Complement number
STA 2300H ; Store the result End

HLT ; Terminate program execution

Lab Experiment 10 : Find the 2’s complement of a number.

Statement : Find the 2’s complement of the number stored at memory location 2200H and
store the complemented number at memory location 2300H. Flowchart
Sample problem Start
(2200H) = 55H
Result = (2300H) = AAH + 1 = ABH
Get the number

Source program
LDA 2200 H ; Get the number Complement the
number
CMA ; Complement the number
ADI, 01H ; Add one in the number
Add one
STA 2300H ; Store the result
HLT ; Terminate program execution
Store the result

End

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Lab Experiment 11 : Pack the two unpacked BCD numbers.

Statement : Pack the two unpacked BCD numbers stored in memory locations 2200H and
2201H and store result in memory location 2300H. Assume the least significant digit is
stored at 2200H. Flowchart
Sample problem
Start
(2200H) = 04
(2201H) = 09
Get the number for the
Result = (2300H) = 94 most significant BCD digit
Source program
LDA 2201H ; Get the Most significant BCD digit Rotate 4 times
to the left and make least
RLC significant digit zero
RLC
RLC Add the number for
lower significant BCD digit
RLC ; Adjust the position into rotated number
ANI F0H ; Make least significant BCD digit zero
MOV C, A ; store the partial result Store the result
LDA 2200H ; Get the lower BCD digit
ADD C ; Add lower BCD digit End
STA 2300H ; Store the result
HLT ; Terminate program execution

Lab Experiment 12 : Unpack the BCD number.

Statement : Two digit BCD number is stored in memory location 2200H. Unpack the BCD
number and store the two digits in memory locations 2300H and 2301H such that memory
location 2300H will have lower BCD digit.
Sample problem
(2200H) = 58
Result = (2300H) = 08 and (2301H) = 05

Flowchart
(See flowchart on next page)
Source program
LDA 2200H ; Get the packed BCD number
ANI F0H ; Mask lower nibble
RRC
RRC
RRC
RRC ; Adjust higher BCD digit as a lower digit

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STA 2301H ; Store the partial result

LDA 2200H ; Get the original BCD number
ANI 0FH ; Mask higher nibble
STA 2201H ; Store the result
HLT ; Terminate program execution

Start

Get the packed BCD number

Mask lower BCD digit

Adjust higher BCD digit

to the lower BCD digit

Store the adjusted result

Get the original BCD number

Mask higher BCD digit

Store the result

END

Lab Experiment 13 : Sample subroutine program.

Statement : Read the program given below and state the contents of all registers after the
execution of each instruction in sequence.
Main program :
6000H LXI SP, 27FFH
6003H LXI H, 2000H
6006H LXI B, 1020H
6009H CALL SUB
600CH HLT

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Subroutine program :
6100H SUB : PUSH B
6101H PUSH H
6102H LXI B, 4080H
6105H LXI H, 4090H
6108H DAD B
6109H SHLD 2200H
610CH POP H
610DH POP B
610EH RET
Solution : The Table 2.5 shows the instruction sequence and the contents of all registers
and stack after execution of each instruction.

Sr. Instructions Registers contents in Hex Memory locations

No. A B C D E H L SP PC (addresses are in Hex)

1 LXI SP,27FF X X X X X X X 27FF 6003

2 LXI H,2000 X X X X X 20 00 27FF 6006

3 LXI B,1020 X 10 20 X X 20 00 27FF 6009

4 CALL SUB X 10 20 X X 20 00 27FD 6100 27FE ¬ 60, 27FD ¬ 0C

5 PUSH B X 10 20 X X 20 00 27FB 6101 27FC ¬ 10, 27FB ¬ 20

6 PUSH H X 10 20 X X 20 00 27F9 6102 27FA ¬ 20, 27F9 ¬ 00

7 LXI B,4080 X 40 80 X X 20 00 27F9 6105

8 LXI H,4090 X 40 80 X X 40 90 27F9 6108

9 DAD B X 40 80 X X 81 10 27F9 6109

10 SHLD 2200 X 40 80 X X 81 10 27F9 610C 2200 ¬ 10, 2201 ¬ 81

11 POP H X 40 80 X X 20 00 27FB 610D

12 POP B X 10 20 X X 20 00 27FD 610E

13 RET X 10 20 X X 20 00 27FF 600C

14 HLT X 10 20 X X 20 00 27FF 600D

Table 2.5

Lab Experiment 14 : Add contents of two memory locations.

Statement : Add the contents of memory locations 2000H and 2001H and place the result
in the memory locations 2002H and 2003H.
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Sample problem :
(2000H) = 7FH
(2001H) = 89H
Result = 7FH + 89H = 108H
(2002H) = 08H
(2003H) = 01H

Flowchart

Start

Get the first number

Get the second number

Add two number

Store the lower

byte of result

Store the higher

byte of result

End

Source program :
LXI H, 2000H ; HL Points 2000H
MOV A, M ; Get first operand
INX H ; HL Points 2001H
ADD M ; Add second operand
INX H ; HL Points 2002H
MOV M, A ; Store the lower byte of result at 2002H
MVI A, 00 ; Initialize higher byte result with 00H
ADC A ; Add carry in the high byte result
INX H ; HL Points 2003H
MOV M, A ; Store the higher byte of result at 2003H
HLT ; Terminate program execution

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Lab Experiment 15 : Right shift data within the 8-bit register.

Statement : Write a program to shift an eight bit data four bits right. Assume that data is
in register C.
Source program :
MOV A, C
RAR
RAR
RAR
RAR
MOV C, A
HLT

Flowchart

Start

Get the number in

accumulator from
C register

Rotate 4 times
right

Store result in
C register

End

Lab Experiment 16 : Right shift data within 16-bit register.

Statement : Write a program to shift an 16-bit data 1 bit right. Assume data is in the BC
register pair.

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Flowchart
Start

Get the number in accumulator

from register B

Rotate accumulator right

such that LSB of A register
will move in the carry

Store result in B register

Get the number in accumulator

from register C

Rotate accumulator right

such that carry
will move in the MSB of
A register

Store result in C register

Stop

Source program :
MOV A, B
RAR
MOV B, A
MOV A, C
RAR
MOV C, A
HLT

Lab Experiment 17 : Left shift 16-bit data within 16-bit register.

Statement : Write a program to shift an 16-bit data 1 bit left. Assume data is in the HL
register pair.

Flowchart

Start

Add HL with
HL

Stop

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Sample problem :
HL = 1025 = 0001 0000 0010 0101
\ HL = 0001 0000 0010 0101
+ HL = 0001 0000 0010 0101
-----------------------------------------------
Result = 0010 0000 0100 1010
Source program :
DAD H

Lab Experiment 18 : Alter the contents of flag register.

Statement : Write a set of instructions to alter the contents of flag register in 8085.
Source Program :
PUSH PSW ; Save flags on stack
POP H ; Retrieve flags in ‘L’
MOV A, L ; Flags in accumulator
CMA ; Complement accumulator
MOV L, A ; Accumulator in ‘L’
PUSH H ; Save on stack
POP PSW ; Back to flag register
HLT ; Terminate program execution
Lab Experiment 19 : Find 2's complement of 16-bit number.
Let x = 2000 H y = 4000 H
\ x + 1 = 2001 H \ y + 1 = 4001 H
Source Program :
LDA 2000H ; Load Accumulator with contents of 2000H location
CMA ; complement the lower byte
ADD 01H ; add 01 to the accumulator
STA 4000H ; Store the accumulator data to 4000H location
LDA 2001H ; Load accumulator with data from memory location 2001H
CMA ; complement the higher byte
ADC 00H ; add with carry to accumulator
HLT ; Stop

Lab Experiment 20 : Simulation of CALL and RET instructions.

Statement : If CALL and RET instructions are not provided in the 8085, could it be
possible to write subroutines for this microprocessor ? If so how will you call and return
from the subroutine?

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Solution : We know that,

1. CALL instruction transfers the program control to the subroutine program by
loading the address of the subroutine program in the program counter, and before
transferring program control it saves the address of the instruction after the CALL
instruction on the stack.
2. RET instruction loads the program counter with return address from the stack and
thus transfers the program control back to the instruction following the CALL.
Now our task is to implement the operation performed by these two instructions with
the help of other instructions of 8085.
Let us implement RET instruction first. To implement this it is necessary to load
program counter with return address. To load program counter with 16-bit address we
have two instructions : JMP address and PCHL. But JMP address instruction cannot be
used for our purpose because JMP address loads program counter with fix address and
the return address is not fix, it depends on, from where the subroutine is ‘CALLed’ in the
main program. The other instruction, PCHL loads 16-bit contents of HL register pair into
PC. If we manage to load return address into HL register pair, every time subroutine is
called, then it is possible to implement RET instruction with the help of PCHL instruction.
We can load the HL register pair with return address before we make a CALL for
subroutine program.
The task to implement CALL instruction is simplified because we are going to store
return address into the HL register pair before we make a ‘CALL’ for subroutine program.
Now it is only required to load program counter with the subroutine address. This can be
implemented by executing JMP instruction. Here JMP instruction is suitable because
subroutine starting address is a ‘fix’ address. The table shows how we can ‘Call’ and
‘Return’ from the subroutine without using CALL and RET instructions.

Main program Main program without CALL instruction

6000H LXI SP, 27FFH 6000H LXI SP, 27FFH ; Initialize stack pointer

:
:

6010H CALL 2200H 6010H PUSH H ; Saves HL register contents in stack,

since HL is used for implementation of
CALL and RET. After subroutine
program execution the original HL
contents are retrieved by executing POP
H instruction

6013H 6011H LXI H, 6018H ; Loads HL with return address.

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6014H PUSH H ; Stores return address in the stack

6015H JMP 2200H ; Loads program counter with 2200H

6018H POP H ; Loads HL with original contents of HL

; from the stack

Table 2.6

Subroutine program Subroutine program without RET instruction

2200 . . . 2200H :
:
2200H RET 2220H POP H ; Loads HL with return address
2221H PCHL ; Loads program counter with return
; address
Table 2.7

Lab Experiment 21 : Find the factorial of a number.

Statement : Write a program to calculate the factorial of a number between 0 to 8.
Solution : Main Program :
LXI SP, 27FFH ; Initialize stack pointer
LDA 2200H ; Get the number
CPI 02H ; Check if number is greater than 1
JC LAST
MVI D, 00H ; Load number as a result
MOV E, A
DCR A
MOV C, A ; Load counter one less than number
CALL FACTO ; Call subroutine facto
XCHG ; Get the result in HL
SHLD 2201H ; Store result in the memory
JMP END
LAST : LXI H,0001H ; Store result = 01
SHLD 2201H ;
END: HLT

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Flowchart :

Start

Initialize stack pointer

Facto
Get the number

Result = Result X no

Yes If
number < 2 No = No – 1
?

No Is
No
no = 0
Result = 1 Load counter ?
initialize result
Yes

CALL facto RET

Store result

End

Subroutine Program :
FACTO : LXI H,0000H
MOV B, C ; Load counter
BACK : DAD D ;
DCR B ;
JNZ BACK ; Multiply by successive addition
XCHG ; Store result in DE
DCR C ; Decrement counter
CNZ FACTO ; Call subroutine FACTO
RET ; Return to main program

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2.7 Instruction Comparisons

ß Example 2.1 : Compare instructions SUB A and MVI A, 00H.

Solution :

Parameter SUB A MVI A, 00H

Number of instruction bytes One byte instruction Two byte instruction

Opcode 97H 3EH

Operation This instruction subtracts the This instruction loads 00H in

contents of register A from itself register A.
and stores result (00H) in
register A

Addressing mode Register addressing mode Immediate addressing mode

Flags This instruction affects all flags. This instruction does not affect
flags

T-states required 4 7

Machine cycles required 1. Opcode fetch 1. Opcode fetch

2. Memory read

ß Example 2.2 : Compare instructions SUB B and CMP B.

Solution :

Parameter SUB B CMP B

Number of instruction bytes One byte instruction One byte instruction

Opcode 90H B8H

Operation This instruction subtracts the This instruction subtracts the

contents of register B from contents of register B from
register A and stores result in register A and affects the flags
register A and affects the flags according to contents of
according to contents of register registers A and B.
A and B.

Result Result of A – B is stored in Result of A – B is not stored in

register A register A. The contents of
register A are unchanged.

Addressing mode Register Register

Flags This instruction affects all flags This instruction affects all flags

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T-states required 4 4

Machine cycles required 1. Opcode fetch 1. Opcode fetch

ß Example 2.3 : Compare instructions LXI H, 2000H and LHLD 2000H.

Solution :

Parameter LXI H, 2000 H LHLD 2000 H

Number of instruction bytes Three byte instruction Three byte instruction

Opcode 21H 2AH

Operand 2000H 2000H

Operation This instruction loads 2000 H in This instruction loads contents of

the HL register pair 2000H memory location into L
register and contents of 2001H
memory location into H register

Addressing mode Immediate Direct

Flags This instruction does not affect This instruction does not affect
flags flags

Required T-states 10 16

Required machine cycles 1. Opcode fetch 1. Opcode fetch

2. Memory read 2. Memory read

3. Memory read 3. Memory read

4. Memory read

5. Memory read

ß Example 2.4 : Compare instruction JMP 2000 H and PCHL

Solution :

Parameter JMP 2000H PCHL

Number of bytes Three byte instruction One byte instruction

Opcode C3H E9H

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Operand 2000H Contents of HL register

Operation This instruction copies 2000H in This instruction copies the

PC so that processor fetches contents of HL register pair into
next instruction from address PC so that processor fetches
2000H next instruction from address
specified by HL register pair.

Addressing Mode Direct Indirect

Flags This instruction does not affect This instruction does not affect
flags flags

Required T-states 10 6

Required Machine Cycles 1. Opcode fetch 1. Opcode fetch

2. Memory read

3. Memory read

ß Example 2.5 : Compare instructions HLT and NOP

Solution :

Parameter HLT NOP

Number of instruction byte One byte instruction One byte instruction

Opcode 76H 00H

Operation This instruction halts the No operation is performed

processor

Flags This instruction does not affect This instruction does not affect
flags flags

Required T-states T-states required are undefined 4-T states. After this instruction
because this instruction halts processor fetches the next
the processor. The processor instruction after NOP
can be restarted by a valid
interrupt or by applying a
RESET signal

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ß Example 2.6 List out differences and similarities between CALL - RET and PUSH-POP
instructions.
Solution : Differences :

Sr. No. CALL-RET PUSH-POP

1 These instructions are used for the These instructions are used to store register
execution of subroutine data temporarily in memory.
2 CALL instruction store the address of next PUSH instruction stores register contents in
instruction after it in the stack and loads PC the stack.
with address given in the instruction.
3 RET instruction loads the address from POP instruction gets the register contents
stack into PC. from the stack.

Similarities :
1. They use stack memory.
2. CALL and PUSH instructions decrement stack pointer by 2.
3. RET and POP instructions increment stack pointer by 2
4. Instructions do not affect flags except POP PSW instruction.

2.8 Instruction Formats

The 8085A instruction set consists of one, two and three byte instructions. The first
byte is always the opcode; in two-byte instructions the second byte is usually data; in
three byte instructions the last two bytes present address or 16-bit data.

1. One byte instruction :

For Example : MOV A, B whose opcode is 78H
Format : Opcode which is one byte. This instruction copies the
1 byte contents of B register in A register.

2. Two byte instruction :

For Example : MVI B, 02H. The opcode for this
instruction is 06H and is always followed by a byte
Format : Opcode Operand data (02H in this case). This instruction is a two byte
instruction which copies immediate data into B
2 bytes
register.

3. Three byte instruction :

For Example : JMP 6200H. The opcode for this instruction is C3H and is always
followed by 16-bit address (6200H in this case). This instruction is a three byte
instruction which loads 16-bit address into program counter.
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Review Questions

Section 2.1
Q.1 Explain the classification of the instruction set of 8085 microprocessor with suitable
examples.

Section 2.2
Q.1 Explain the operations carried out when 8085 executes the instructions.
i) MOV A, M ii) XCHG
iii) DAD B iv) DAA Dec.-07, Marks 16

Q.2 With suitable examples, Explain the function of various data transfer and data
manipulation instructions of 8085. May-10,11, Marks 10

Q.3 How are the 8085 instructions classified according to the functional categories ?
Dec.-11, Marks 2

Q.4 Describe with suitable examples the data transfer, loading and storing instructions.
June-12, Marks 8

Q.5 What is stack ? And what is the function of stack pointer ?

Dec.-07, Marks 2

Q.6 Explain the operations carried out when 8085 executes the instructions.
POP PSW Dec.-07, Marks 16

Q.7 Discuss the organizations of the 8085 stack and the various instructions that will
operate on the stack. Dec-09, June-11, Marks 10

Q.8 Describe with a suitable example the operation of stack. June-12, Marks 8

Q.9 How is PUSH B instruction executed ? Find the status after the execution.
May-11, Marks 2

Q.10 Explain the sequence of events in the execution of CALL and RET instructions.
June-07, Marks 8

Q.11 What is the use of branching instructions ? Give Example. June-12, Marks 2

Q.12 State the function of given 8085 instructions : JP, JPE, JPO, JNZ
May-11, Marks 2

Q.13 Give examples for machine control instructions. June-11, Marks 2

Section 2.3
Q.1 With example explain the different addressing modes of 8085 and the different types
of instruction. Dec.-04, Marks 16

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Q.2 Define and explain the addressing modes of 8085 with example.
June-06,07,11, May-08,10,11,12 Dec.-09,10, Marks 16

Q.3 Explain in detail about the indirect addressing mode in 8085.

June-09, Marks 4

Section 2.4
Q.1 Explain the instruction set of 8085 with examples. Dec.-08, Marks 16

Section 2.5
Q.1 What is program ?
Q.2 Give the steps involved in programming.
Q.3 What is flowchart ? Explain its use.
Q.4 Explain the process of writing assembly language program with the help of example.
Q.5 What do you mean by hand assembly ? Explain with the help of example.
Q.6 Explain the process of executing the program on the microprocessor training kit.

Section 2.6
Q.1 Write a program with a flowchart to multiply two 8-bit numbers.
Dec.-11, Marks 8

Q.2 Sixteen bytes are stored in memory locations at XX50h to XX5Fh.

Transfer the entire block of data to new memory locations starting at XX70h.
Dec.-11, Marks 8

Q.3 Write an assembly language program for arranging an array of 8-bit unsigned number
in ascending order. June-12, Marks 8

Section 2.7
Q.1 Compare the similarities and differences of CALL and RET instructions with PUSH
and POP instructions. Dec.-11, Marks 8

Q.2 Explain the operational difference between the following pairs of instructions.
i) SPHL and XTHL ii) CALL addr and JMP addr
iii) LHLD and SHLD addr iv) XRA A and MVI A, 00H
v) INR A and ADI 01 H vi) DAD RP and DAA.

Section 2.8
Q.1 Describe the instruction format of 8085 microprocessor. May-11, Marks 4

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Two Marks Questions with Answers

Q.1 What is an operand ?
Ans. : The data on which the operation is to be performed is called an operand.

Q.2 How many operations are there in the instruction set of 8085 microprocessor ?
Ans. : There are 74 operations in the 8085 microprocessor.

Q.3 What is an opcode ?

Ans. : The part of the instruction that specifies the operation to be performed is called
the operation code or opcode.

Q.4 List out the five categories of the 8085 instructions. Give examples of the
instructions for each group.
Ans. :
· Data transfer group - MOV, MVI, LXI.
· Arithmetic group - ADD, SUB, INR.
· Logical group -ANA, XRA, CMP.
· Branch group - JMP, JNZ, CALL.
· Stack I/O and Machine control group – PUSH, POP, HLT.

Q.5 Explain the purpose of the I/O instructions IN and OUT.

Ans. : The IN instruction is used to move data from an I/O port into the accumulator.
The OUT instruction is used to move data from the accumulator to an I/O port. The IN
and OUT instructions are used only on microprocessor, which use a separate address
space for I/O interfacing.

Q.6 What is the difference between the shift and rotate instructions?
Ans. : A rotate instruction is a closed loop instruction. That is, the data moved out at
one end is put back in at the other end. The shift instruction loses the data that is
moved out of the last bit locations.

Q.7 What are operations performed on data in 8085.

Ans. : The various operations performed are :
· Store 8-bit data
· Perform arithmetic and logical operations
· Test for conditions
· Sequence the execution of instructions
· Store data temporarily during execution in the defined R/W memory locations
called the stack
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Q.8 What is an instruction?

Ans. : An instruction is a binary pattern or code which is interpreted by the
microprocessor to perform that specific function

Q.9 Explain the different instruction formats with examples.

Ans. : The instruction set is grouped into the following formats.
· One byte instruction -MOV C,A
· Two byte instruction -MVI A,39H
· Three byte instruction -JMP 2345H
Q.10 What is the use of addressing modes, mention the different types.
Ans. : The various formats of specifying the operands are called addressing modes, it
is used to access the operands or data. The different types are as follows :
· Immediate addressing
· Register addressing
· Direct addressing
· Indirect addressing
· Implicit addressing
Q.11 What is the type of stack used in 8085? May-04

Ans. : Memory type stack is used in 8085

Q.12 What are the different addressing modes of 8085? Dec.-04,09

Ans. : The 8085 has 5 addressing modes. These are :

1. Immediate 2. Register
3. Direct 4. Indirect
5. Implied
Q.13 Define addressing modes.
Ans. : The different ways that a microprocessor can access data are referred to as
addressing modes

Q.14 What is the significance of 'XCHG' and 'SPHL' instructions ? June-07

Ans. : XCHG : This instruction exchanges the contents of the register H with that of
D and of L with that of E.
SPHL : This instruction copies the contents of HL register pair into the stack
pointer. The contents of H register are copied to higher order byte of stack pointer
and contents of L register are copied to the lower byte of stack pointer. This allows
indirect way of initializing stack pointer.

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Q.15 Differentiate cascade stack and memory stack.

June-07
Ans. : In a cascaded stack, CPU registers are used as a stack. In memory stack, the
part of memory is used for stack.

Q.16 What is the function of SIM instruction in 8085 ? Dec.-07

Ans. : The sim instruction masks the interrupts as desired. It also sends out serial
data through the SOD pin.

Q.17 Write the operation carried out when 8085 executes RST0 instruction.
Dec.-07
Ans. : When 8085 executes RST0 instruction, the program control is transferred to
memory address 0000H. Before transfer of program control RST0 instruction saves the
current program counter contents on the stack and decrements stack pointer by 2.
Q.18 Write the difference between opcode and operand. May-08

Ans. : Opcode indicates the operation to be performed and operand is a data on

which the operation is performed.

Q.19 Write the stack related instructions in 8085 microprocessor. May-08

Ans. : The stack related instructions in 8085 microprocessor are :

1. PUSH rp 2. PUSH PSW
3. POP rp 4. POP PSW
5. SPHL 6. XTHL
Q.20 Write the machine control instructions of 8085 microprocessor. Dec.-08
Ans. : Machine control instructions of 8085 microprocessor are :
1. EI 2. DI
3. NOP 4. HLT
5. SIM 6. RIM

Q.21 How the instruction sets are grouped ? June-09

Ans. : Refer section 2.2.

Q.22 What are the use of CALL and RET instructions of 8085? Dec-09
Ans. : Refer section 2.2.6.

Q.23 Mention the instructions used for data transfer with I/O ports. May-10

Ans. : The instructions used for data transfer with I/O ports are : 1. IN addr 2. OUT
adder

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Q.24 Differentiate CALL instruction from JUMP instruction. May-10

Ans. :

Sr. No. CALL JMP

1. A CALL instruction leaves A JMP instruction permanently changes the

information on the stack so that program counter.
the original program execution
sequence can be resumed.
2. It requires 5 machine cycles. It requires three machine cycles.
3. It requires 18 T-states time for It requires 10 T-states time for execution.
execution.
4. After execution of CALL sp is Stack pointer contents are unchanged after
sp - 2. execution of JMP instruction.

Q.25 What do you understand by the term 'program status word' and state how it
can be read ? Dec.-10

Ans. : Program status word is the flag register of microprocessor. In 8085

microprocessor the program status word can be read as follows :
PUSH PSW
POP rP
Now contents of PSW are available in lower byte of specified register pair

Q.26 What is the value of register A after each of the following instructions ?
MOV A, # 26H
RR A
RR A
RR A
RR A
SWAP A Dec.-10

Ans. : A = 26 H

qqq

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 Looping, Counting, Time Delays
3 and Code Conversion

Contents
3.1 Looping, Counting and Indexing
3.2 Timers
3.3 Code Conversion
3.4 BCD Arithmetic

(3 - 1)
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In the last chapter we have seen the instruction set of 8085 and some simple assembly
language programs using it. We know that, the program is an implementation of certain
logic by executing group of instructions. To implement program logic we need to take help
of some common programming techniques such as looping, counting, indexing and code
conversion.
In this chapter, we are going to study how to implement these programming
techniques using 8085 assembly language and some programming examples using them.
This chapter also introduces the BCD arithmetic and programming techniques to
implement BCD arithmetic using 8085 assembly language.

3.1 Looping, Counting and Indexing

Before going to implement these techniques, we get conversant with these techniques
and understand the use of them.
Looping : In this technique, the program is instructed to execute certain set of
instructions repeatedly to execute a particular task number of times. For example, to add
ten numbers stored in the consecutive memory locations we have to perform addition ten
times.
Counting : This technique allows programmer to count how many times the
instruction/set of instructions are executed.
Indexing : This technique allows programmer to point or refer the data stored in
sequential memory locations one by one. Let us see the program loop to understand
looping, counting and indexing.
The program loop is the basic structure which forces the processor to repeat a
sequence of instructions. Loops have four sections.
1. Initialization section. 2. Processing section.
3. Loop control section 4. Result section.

Flowchart : (See on next page)

1. The initialization section establishes the starting values of
· loop counters for counting how many times loop is executed,
· address registers for indexing which give pointers to memory locations and
· other variables.

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Start

Initialization section Start

Processing section Initialization section

Loop control section Loop control section

Is Is
No looping looping Yes
over over
? ?

Yes No

Result section Processing section Result section

End End

Flowchart 1 Flowchart 2
2. The actual data manipulation occurs in the processing section. This is the section
which does the work.
3. The loop control section updates counters, indices (pointers) for the next iteration.
4. The result section analyzes and stores the results.

Note : The processor executes initialization section and result section only once, while it
may execute processing section and loop control section many times. Thus, the execution
time of the loop will be mainly dependent on the execution time of the processing section
and loop control section. The flowchart 1 shows typical program loop. The processing
section in this flowchart is always executed at least once. If you interchange the position of
the processing and loop control section then it is possible that the processing section may
not be executed at all, if necessary. Refer flowchart 2.

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Program Examples
Lab Experiment 22 : Calculate the sum of series of numbers.
Statement : Calculate the sum of series of numbers. The length of the series is in memory
location 2200H and the series itself begins from memory location 2201H.
a. Assume the sum to be 8 bit number so you can ignore carries. Store the sum at
memory location 2300H.
b. Assume the sum to be 16 bit number. Store the sum at memory locations 2300H
and 2301H.

a. Sample problem :
2200H = 04H
2201H = 20H
2202H = 15H
2203H = 13H
2204H = 22H
Result = 20 + 15 + 13 + 22 = 6AH
\ 2300H = 6AH

Flowchart :

Start

Sum=0
Pointer = 2201H
Count = (2200H)

Sum = Sum + (Pointer)

Pointer = Pointer +1
Count = Count – 1

No Is
Count = 0
?

Yes

(2300H) = Sum

End

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Source program :
LDA 2200H
MOV C, A ; Initialize counter
SUB A ; sum = 0
LXI H, 2201H ; Initialize pointer
BACK : ADD M ; SUM = SUM + data
INX H ; Increment pointer
DCR C ; Decrement counter
JNZ BACK ; If counter ¹ 0 repeat
STA 2300H ; Store sum
HLT ; Terminate program execution

b. Sample problem :
2200H = 04H 2201H = 9AH
2202H = 52H 2203H = 89H 2204H = 3EH
Result = 9AH + 52H + 89H + 3EH = 1B3H
\ 2300H = B3H Lower byte 2301H = 01H Higher byte

Flowchart :
Start

Sum high = 0
Sum low = 0
Pointer = 2201H
Count = (2200H)

Sum low = Sum low + (Pointer)

No Is
Carry 1
?

Yes

Sum high = Sum high + 1

Pointer = Pointer + 1
Count = Count – 1

No Is
Count = 0
?

Yes
(2300H) = Sum low
(2301H) = Sum high

End

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Source program :
LDA 2200H
MOV C, A ; Initialize counter
LXI H, 2201H ; Initialize pointer
SUB A ; Sumlow = 0
MOV B, A ; Sumhigh = 0
BACK : ADD M ; Sum = sum + data
JNC SKIP
INR B ; Add carry to MSB of SUM
SKIP : INX H ; Increment pointer
DCR C ; Decrement counter
JNZ BACK ; Check if counter ¹ 0 repeat
STA 2300H ; Store lower byte
MOV A, B
STA 2301H ; Store higher byte
HLT ; Terminate program execution

Lab Experiment 23 : Data transfer from memory block B1 to memory block B2.
Statement : Transfer ten bytes of data from one memory to another memory block. Source
memory block starts from memory location 2200H where as destination memory block
starts from memory location 2300H.

Flowchart :
Start

Initialize counter = 10

Initialize source memory pointer

Initialize destination memory pointer

Get the byte from source memory block

Store byte in the destination memory block

Increment source memory pointer, increment

destination memory pointer and decrement counter

No Is
Count = 0
?

Yes

End

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Source program :
MVI C, 0AH ; Initialize counter
LXI H, 2200H ; Initialize source memory pointer
LXI D, 2300H ; Initialize destination memory pointer
BACK : MOV A, M ; Get byte from source memory block
STAX D ; Store byte in the destination memory block
INX H ; Increment source memory pointer
INX D ; Increment destination memory pointer
DCR C ; Decrement counter
JNZ BACK ; If counter ¹ 0 repeat
HLT ; Terminate program execution

Lab Experiment 24 : Multiply two 8-bit numbers.

Statement : Multiply two 8-bit numbers stored in memory locations 2200H and 2201H.
Store the result in memory locations 2300H and 2301H.

Sample problem :
(2200H) = 03H
(2201H) = B2H
Result = B2H + B2H + B2H
= 216H
(2300H) = 16H
(2301H) = 02H
Note : In 8085 multiplication can be done by repetitive addition.

Flowchart :
Start

Get the first number

Initialize second
number as a counter

Result = 0

Result = Result + First number

Decrement counter

No Is
count = 0
?

Yes

End

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Microprocessors and Microcontroller 3-8 Looping, Counting, Time Delays & Code Conversion

Source program :
LDA 2200H
MOV E, A
MVI D, 00 ; Get the first number in DE register pair
LDA 2201H
MOV C, A ; Initialize counter
LXI H, 0000H ; Result = 0
BACK : DAD D ; Result = result + first number
DCR C ; Decrement count
JNZ BACK ; If count ¹ 0 repeat
SHLD 2300H ; Store result
HLT ; Terminate program execution

Lab Experiment 25 : Divide 16-bit number by 8-bit number.

Statement : Divide 16 bit number stored in memory locations 2200H and 2201H by the 8
bit number stored at memory location 2202H. Store the quotient in memory locations
2300H and 2301H and remainder in memory locations 2302H and 2303H.

Flowchart :
Start

Get the dividend

Get the divisor

Quotient = 0

Division = Dividend – divisor

Quotient = quotient + 1

Is
No dividend <
divisor

Yes
Remainder = dividend

Store the quotient and remainder

End

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Microprocessors and Microcontroller 3-9 Looping, Counting, Time Delays & Code Conversion

Sample problem :
(2200H) = 60H
(2201H) = A0H
(2202H) = 12H
Result = A060H/12H = 8E8H Quotient
and 10H remainder
(2300H) = E8H
(2301H) = 08H
(2302H) = 10H
(2303H) = 00H

Source program :
LHLD 2200H ; Get the dividend
LDA 2202H
MOV C, A ; Get the divisor
LXI D, 0000H ; Quotient = 0
BACK : MOV A, L
SUB C ; Subtract divisor
MOV L, A ; Save partial result
JNC SKIP ; If CY ¹ 1 jump
DCR H ; Subtract borrow of previous subtraction
SKIP : INX D ; Increment quotient
MOV A, H
CPI, 00 ; Check if dividend < divisor
JNZ BACK ; If no repeat
MOV A, L
CMP C
JNC BACK
SHLD 2302H ; Store the remainder
XCHG
SHLD 2300H ; Store the quotient
HLT ; Terminate program execution

Lab Experiment 26 : Find the negative numbers in a block of data.

Statement : Find the number of negative elements (most significant bit 1) in a block of
data. The length of the block is in memory location 2200H and the block itself begins in
memory location 2201H. Store the number of negative elements in memory location 2300H.

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Flowchart :

Start

Neg number = 0
Pointer = 2201H
Count = (2200H)

No Is
MSB =1
?
Yes
Neg number =Neg number+ 1

Pointer = Pointer + 1
Count = Count – 1

No Is
Count = 0
?
Yes
(2300H) = Neg number

End

Sample problem :
(2200H) = 04H
(2201H) = 56H
(2202H) = A9H
(2203H) = 73H
(2204H) = 82H
Result = 02 since 2202H and 2204H contain numbers with a MSB of 1.

Source program :
LDA 2200H
MOV C, A ; Initialize count
MVI B, 00 ; Negative number = 0
LXI H, 2201H ; Initialize pointer
BACK : MOV A, M ; Get the number
ANI 80H ; Check for MSB
JZ SKIP ; If MSB = 1

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INR B ; Increment negative number count

SKIP : INX H ; Increment pointer
DCR C ; Decrement count
JNZ BACK ; If count ¹ 0 repeat
MOV A, B ;
STA 2300H ; Store the result
HLT ; Terminate program execution

Lab Experiment 27 : Find the largest of given numbers.

Statement :
Find the largest number in a block of data. The length of the block is in memory
location 2200H and the block itself start from memory location 2201H. Store the maximum
number in memory location 2300H. Assume that the number in the block are all 8 bit
unsigned binary numbers.

Flowchart :
Start

Count = 2200H
Pointer = (2201H)
Max = 0

No Is
Max < (Pointer)
?

Yes
Max = (Pointer)

Pointer = Pointer + 1
Count = Count – 1

No Is
Count = 0
?

Yes
(2300H) = Max

End

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Microprocessors and Microcontroller 3 - 12 Looping, Counting, Time Delays & Code Conversion

Sample problem :
(2200H) = 04
(2201H) = 34H
(2202H) = A9H
(2203H) = 78H
(2204H) = 56H
Result = (2202H) = A9H.

Source program :
LDA 2200H
MOV C, A ; Initialize counter
XRA A ; Maximum = Minimum possible value = 0
LXI H, 2201H ; Initialize pointer
BACK : CMP M ; Is number > maximum
JNC SKIP
MOV A, M ; Yes, replace maximum
SKIP : INX H
DCR C
JNZ BACK
STA 2300H ; Store maximum number
HLT ; Terminate program execution

Lab Experiment 28 : Count number of one's in a number.

Statement : Write a program to count number of 1’s in the contents of D register and store
the count in the B register.

Source program :
MVI B, 00H
MVI C, 08H
MOV A, D
BACK : RAR
JNC SKIP
INR B
SKIP : DCR C
JNZ BACK
HLT

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Microprocessors and Microcontroller 3 - 13 Looping, Counting, Time Delays & Code Conversion

Flowchart :

Start

Initialize count = 0
Initialize counter = 8

Get the contents of

D register in the
accumulator

Rotate contents of
accumulator so that
LSB will go in carry

No Is
carry = 1
?
Yes

Increment count

Decrement counter

No Is
counter = 0
?

Yes

Stop

Lab Experiment 29 : Arrange numbers in the ascending order.

Statement : Write a program to sort given 10 numbers from memory location 2200H in
the ascending order.

Source program :
MVI B, 09 ; Initialize counter 1
START : LXI H, 2200H ; Initialize memory pointer
MVI C, 09H ; Initialize counter 2
BACK : MOV A, M ; Get the number
INX H ; Increment memory pointer
CMP M ; Compare number with next number
JC SKIP ; If less, don’t interchange
JZ SKIP ; If equal, don’t interchange
MOV D, M
MOV M, A
DCX H
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MOV M, D
INX H ; Interchange two numbers
SKIP : DCR C ; Decrement counter 2
JNZ BACK ; If not zero, repeat
DCR B ; Decrement counter 1
JNZ START ; If not zero, repeat
HLT ; Terminate program execution

Flowchart :
Start

Initialize counter 1 = 09

Initialize memory pointer

Initialize counter = 09H

Get the number

Increment memory pointer

Is
No (Pointer – 1) >(Pointer)
?

Interchange contents

Decrement counter 2
Increment memory pointer

No Is
counter 2 = 0
?

Yes
Decrement counter 1

Is
counter 1 = 0
?

Stop

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Microprocessors and Microcontroller 3 - 15 Looping, Counting, Time Delays & Code Conversion

Lab Experiment 30 : Calculate the sum of series of even numbers.

Statement : Calculate the sum of series of even numbers from the list of numbers. The
length of the list is in memory location 2200H and the series itself begins from memory
location 2201H. Assume the sum to be 8 bit number so you can ignore carries and store
the sum at memory location 2210H.

Sample problem :
2200H = 4H
2201H = 20H
2202H = 15H
2203H = 13H
2204H = 22H
Result = 20 + 22 = 42H
\ 2210H = 42H

Flowchart :

Start

Sum = 0
Pointer = 2201H
Count = (2200H)

Is
(Pointer) = even No
number
?

Yes

Sum = Sum + (Pointer)

Pointer = Pointer +1
Count = Count – 1

No Is
carry = 0
?

Yes

(2300H) = Sum

End

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Microprocessors and Microcontroller 3 - 16 Looping, Counting, Time Delays & Code Conversion

Source program :
LDA 2200H
MOV C, A ; Initialize counter
MVI B, 00H ; sum = 0
LXI H, 2201H ; Initialize pointer
BACK : MOV A, M ; Get the number
ANI 01H ; Mask Bit1 to Bit7
JNZ SKIP ; Don’t add if number is ODD
MOV A, B ; Get the sum
ADD M ; SUM = SUM + data
MOV B, A ; Store result in B register
SKIP : INX H ; Increment pointer
DCR C ; Decrement counter
JNZ BACK ; If counter 0 repeat
STA 2210H ; Store sum
HLT ; Terminate program execution

Lab Experiment 31 : Calculate the sum of series of odd numbers.

Statement : Calculate the sum of series of odd numbers from the list of numbers. The
length of the list is in memory location 2200H and the series itself begins from memory
location 2201H. Assume the sum to be 16-bit. Store the sum at memory locations 2300H
and 2301H.

Sample program :
2200H = 4H
2201H = 9AH
2202H = 52H
2203H = 89H
2204H = 3FH
Result = 89H + 3FH = C8H
\ 2300H = 61H Lower byte
2301H = 01H Higher byte
Source program :
LDA 2200H
MOV C, A ; Initialize counter
LXI H, 2201H ; Initialize pointer
MVI E, 00 ; Sumlow = 0
MOV D, E ; Sumhigh = 0
BACK : MOV A, M ; Get the number

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Microprocessors and Microcontroller 3 - 17 Looping, Counting, Time Delays & Code Conversion

ANI 01H ; Mask Bit1 to Bit7

JZ SKIP ; Don’t add if number is even
MOV A, E ; Get the lower byte of sum
ADD M ; Sum = sum + data
MOV E, A ; Store result in E register
JNC SKIP
INR D ; Add carry to MSB of SUM
SKIP : INX H ; Increment pointer
DCR C ; Decrement counter
JNZ BACK ; Check if counter ¹ 0 repeat
MOV A, E
STA 2300H ; Store lower byte
MOV A, D
STA 2301H ; Store higher byte
HLT ; Terminate program execution

Flowchart :
Start

Sum = 0
Pointer = 2201H
Count = (2200H)

Is
(Pointer) = odd No
number
?

Yes

Sum = Sum + (Pointer)

Pointer = Pointer +1
Count = Count – 1

No Is
carry = 0
?

Yes

(2300H) = Sum

End

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Microprocessors and Microcontroller 3 - 18 Looping, Counting, Time Delays & Code Conversion

Lab Experiment 32 : Find the square of given number.

Statement : Find the square of the given numbers from memory location 6100H and store
the result from memory location 7000H.
Source program :
LXI H,6200H ; Initialize lookup table pointer
LXI D,6100H ; Initialize source memory pointer
LXI B,7000H ; Initialize destination memory pointer
BACK : LDAX D ; Get the number
MOV L, A ; A point to the square
MOV A, M ; Get the square
STAX B ; Store the result at destination memory location
INX D ; Increment source memory pointer
INX B ; Increment destination memory pointer
MOV A, C
CPI 05H ; Check for last number
JNZ BACK ; If not repeat
HLT ; End of program

Flowchart :

Start

Initialize lookup table pointer

Lookup Table
Initialize source memory pointer
Initialize destination memory pointer Address Digit Square

6100H 0 0H
Get the number
6101H 1 1H

Find the square 6102H 2 4H

6103H 3 9H
Store square in the
destination memory location 6104H 4 10H

6105H 5 19H
Increment source memory pointer
Increment destination memory pointer 6106H 6 24H

6107H 7 31H
Is 6108H 8 40H
No
last number
?
6109H 9 51H
Yes

Stop

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Microprocessors and Microcontroller 3 - 19 Looping, Counting, Time Delays & Code Conversion

Lab Experiment 33 : Search a byte in a given number.

Statement : Search the given byte in the list of 50 numbers stored in the consecutive
memory locations and store the address of memory location in the memory locations
2200H and 2201H. Assume byte is in the C register and starting address of the list is
2000H. If byte is not found store 00 at 2200H and 2201H.

Source program :
LXI H, 2000H ; Initialize memory pointer
MVI B, 52H ; Initialize counter
BACK : MOV A, M ; Get the number
CMP C ; Compare with the given byte
JZ LAST ; Go last if match occurs
INX H ; Increment memory pointer
DCR B ; Decrement counter
JNZ B ; If not zero, repeat
LXI H, 0000H
SHLD 2200H
JMP END ; Store 00 at 2200H and 2201H
LAST : SHLD 2200H ; Store memory address
END : HLT ; Stop

Flowchart :
Start

Initialize memory pointer

Initialize counter = 32H

Is
(Pointer) = Yes
Search byte
?

No

Increment memory pointer

Decrement counter

Store memory address

Is
No
Counter = 0
?

Yes

Store 00 as a result

Stop

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Microprocessors and Microcontroller 3 - 20 Looping, Counting, Time Delays & Code Conversion

Lab Experiment 34 : Add two decimal numbers.

Statement : Two decimal numbers six digits each, are stored in BCD packed form. Each
number occupies a sequence of byte in the memory. The starting address of first number is
6000H and second number is 6100H. Write an assembly language program that adds these
two numbers and stores the sum in the same format starting from memory location 6200H.

Flowchart :

Start

Initialize memory pointer

1 to point the first number

Initialize memory pointer

2 to point the second number
Initialize result pointer

Set carry = 0

Add two number pointed by

two memory pointers
with carry

Adjust result for decimal values

Store the result at memory

location pointed by
result pointer

Increment memory pointer 1

Increment memory pointer 2
Increment result pointer

Check
No for last
digit

Yes

Stop

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Microprocessors and Microcontroller 3 - 21 Looping, Counting, Time Delays & Code Conversion

Source program :
LXI H,6000H ; Initialize pointer1 to first number
LXI D,6100H ; Initialize pointer2 to second number
LXI B,6200H ; Initialize pointer3 to result
STC
CMC ; Carry = 0
BACK : LDAX D ; Get the digit
ADD M ; Add two digits
DAA ; Adjust for decimal
STAX B ; Store the result
INX H ; Increment pointer1
INX D ; Increment pointer2
INX B ; Increment result pointer
MOV A, L
CPI 06H ; Check for last digit
JNZ BACK ; If not last digit repeat
HLT ; Terminate program execution

Lab Experiment 35 : Add each element of array with the elements of another array.
Statement : Add 2 arrays having ten 8-bit numbers each and generate a third array of
result. It is necessary to add the first element of array1 with the first element of array-2
and so on. The starting addresses of array1, array2 and array3 are 2200H, 2300H and
2400H, respectively.

Flowchart : (See on next page)

Source program :
LXI H, 2200H ; Initialize memory pointer 1
LXI B, 2300H ; Initialize memory pointer 2
LXI D, 2400H ; Initialize result pointer
BACK : LDAX B ; Get the number from array 2
ADD M ; Add it with number in array 1
STAX D ; Store the addition in array 3
INX H ; Increment pointer1
INX B ; Increment pointer2
INX D ; Increment result pointer
MOV A, L ;
CPI 0AH ; Check pointer1 for last number
JNZ BACK ; If not, repeat
HLT ; Stop

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Flowchart :

Start

Initialize memory pointer 1

for array 1

Initialize memory pointer 2

for array 2

Initialize memory pointer 3

for array 3

(Pointer 3) = (Pointer 1) + (Pointer 2)

Pointer 1 = Pointer 1 + 1
Pointer 2 = Pointer 2 + 1
Pointer 3 = Pointer 3 + 1

Yes Is
Pointer 1 <10
?

No

Stop

Lab Experiment 36 : Separate even numbers from given numbers.

Statement : Write an assembly language program to seperate even numbers from the
given list of 50 numbers and store them in the another list starting from 2300H. Assume
starting address of 50 number list is 2200H.

Flowchart : (See on next page)

Source program :
LXI H, 2200H ; Initialize memory pointer1
LXI D, 2300H ; Initialize memory pointer2
MVI C, 32H ; Initialize counter
BACK : MOV A, M ; Get the number
ANI 01H ; Check for even number
JNZ SKIP ; If ODD, don’t store
MOV A, M ; Get the number
STAX D ; Store the number in result list
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Microprocessors and Microcontroller 3 - 23 Looping, Counting, Time Delays & Code Conversion

INX D ; Increment pointer 2

SKIP : INX H ; Increment pointer1
DCR C ; Decrement counter
JNZ BACK ; If not zero, repeat
HLT ; Stop

Flowchart : (For Lab Experiment 36)

Start

Initialize memory pointer 1 to

point list of 50 numbers

Initialize memory pointer 2 to

point the result list

Initialize counter = 32H

Get the number

Is No
number = even
?

Yes

(Pointer 2) number

Pointer 2 = pointer 2 + 1

Pointer 1 = pointer 1 + 1

Counter = counter – 1

No Is
counter = 0
?

Yes

End

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Microprocessors and Microcontroller 3 - 24 Looping, Counting, Time Delays & Code Conversion

Lab Experiment 37 : Transfer contents to overlapping memory blocks.

Statement : Write assembly language program to with proper comments for the
following : A block of data consisting of 256 bytes is stored in memory starting at 3000H.
This block is to be shifted (relocated) in memory from 3050H onwards. Do not shift the
block or part of the block anywhere else in the memory.

Source program :
Two blocks (3000 – 30FF and 3050 – 314F) are overlapping. Therefore it is necessary to
transfer last byte first and first byte last.
MVI C, FFH ; Initialize counter
LXI H, 30FFH ; Initialize source memory pointer
LXI D, 314FH ; Initialize destination memory pointer
BACK : MOV A, M ; Get byte from source memory block
STAX D ; Store byte in the destination memory
; block
DCX H ; Decrement source memory pointer
DCX ; Decrement destination memory pointer
DCR C ; Decrement counter
JNZ BACK ; If counter ¹ 0 repeat
HLT ; Stop execution

Lab Experiment 38 : Inserting string in a given array of characters.

Statement : Write an 8085 assembly language program to insert a string of four characters
from the tenth location in the given array of 50 characters.

Solution :

Step 1 : Move bytes from location 10 till the end of array by four bytes downwards.

Step 2 : Insert four bytes at locations 10, 11, 12 and 13.

LXI H, 2131H ; Initialize pointer at the last location
; of array.
LXI D, 2135H ; Initialize another pointer to point the
; last location of array after insertion.

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AGAIN : MOV A, M ; Get the character

STAX D ; Store at the new location
DCX D ; Decrement destination pointer
DCX H ; Decrement source pointer
MOV A, L ; [ check whether desired bytes are
CPI 08H shifted or not]
JNZ AGAIN ; If not repeat the process
INX H ; Adjust the memory pointer
LXI D, 2200H ; Initialize the memory pointer to point
; the string to be inserted
REPE : LDAX D ; Get the character
MOV M, A ; Store it in the array
INX D ; Increment source pointer
INX H ; Increment destination pointer
MOV A, E ; [ check whether the 4 bytes
CPI 04 ; are inserted]
JNZ REPE ; If not repeat the process
HLT ; Stop

Lab Experiment 39 : Deleting string in a given array of characters.

Statement : Write an 8085 assembly language program to delete a string of 4 characters
from the tenth location in the given array of 50 characters.

Solution : Shift bytes from location 14 till the end of array upwards by 4 characters i.e.
from location 10 on words.
LXI H, 210DH ; Initialize source memory pointer at the 14th
; location of the array.
LXI D, 2109H ; Initialize destination memory pointer at the
; 10th location of the array.
MOV A, M ; Get the character
STAX D ; Store character at new location
INX D ; Increment destination pointer
INX H ; Increment source pointer
MOV A, L ; [ check whether desired
CPI 32H ; bytes are shifted or not]
JNZ REPE ; If not repeat the process.
HLT ; Stop

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Lab Experiment 40 : Add parity bit to 7-bit ASCII characters.

Statement : Add even parity to a string of 7-bit ASCII characters. The length of the string
is in memory location 2040H and the string itself begins in memory location 2041H. Place
even parity in the most significant bit of each character. Draw a flowchart and write an
8085 assembly language program with comment for each instruction.

Flowchart :
Start

Initialize memory pointer

and character counter

Get ASCII character

from memory location

No Is
Parity odd
?

Yes

Add even parity bit

in MSB

Store ASCII character

in memory location

Increment memory
Pointer

Decrement character
counter

Is
character No
counter 0?

Yes

End

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Source program :
LXI H, 2040H
MOV C, M ; Counter for character
REPEAT : INX H ; Memory pointer to character
MOV A, M ; Character in accumulator
ORA A ; ORing with itself to check parity.
JPO PEREVEN
ORI 80H ; If odd parity place even parity in
; D7(80).
PEREVEN : MOV M, A ; Store converted even parity character.
DCR C ; Decrement counter.
JNZ REPEAT ; If not zero go for next character.
HLT ; Terminate program execution

Lab Experiment 41 : Find the number of negative, zero and positive numbers.
Statement : A list of 50 numbers is stored in memory, starting at 6000H. Find number of
negative, zero and positive numbers from this list and store these results in memory
locations 7000H, 7001H, and 7002H respectively.

Source program :
LXI H, 6000H ; Initialize memory pointer
MVI C, 00H ; Initialize number counter
MVI B, 00H ; Initialize negative number counter
MVI E, 00H ; Initialize zero number counter
BEGIN : MOV A, M ; Get the number
CPI 00H ; If number = 0
JZ ZERONUM ; Goto zeronum
ANI 80H ; If MSB of number = 1 i.e. if
JNZ NEGNUM ; Number is negative goto NEGNUM
INR D ; Otherwise increment positive number Counter
JMP LAST ;
ZERONUM : INR E ; Increment zero number counter
JMP LAST
NEGNUM : INR B ; Increment negative number counter
LAST : INX H ; Increment memory pointer
INR C ; Increment number counter
MOV A, C
CPI 32H ; If number counter = 5010 then
JNZ BEGIN ; Store otherwise check next number
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Microprocessors and Microcontroller 3 - 28 Looping, Counting, Time Delays & Code Conversion

LXI H, 7000 ; Initialize memory pointer.

MOV M, B ; Store negative number.
INX H
MOV M, E ; Store zero number.
INX H
MOV M, D ; Store positive number.
HLT

Flowchart :

Start

Initialize memory pointer initialize

counter to count total numbers

Initialize counters for negative,

positive and zero numbers

Get the number

Yes Is
number = 0
?

No

Is
number <0? Yes
Increment zero
number counter MSB=1

No Increment negative
number counter
Increment positive number
counter

Increment memory pointer

Numbers = Numbers + 1

No Is
number =50
?

Yes

Stop

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Microprocessors and Microcontroller 3 - 29 Looping, Counting, Time Delays & Code Conversion

Lab Experiment 42 : Multiply two eight bit numbers with shift and add method.
Statement : Multiply the 8-bit unsigned number in memory location 2200H by the 8-bit
unsigned number in memory location 2201H. Store the 8 least significant bits of the result
in memory location 2300H and the 8 most significant bits in memory location 2301H.

Sample problems :
(2200) = 1100 (0CH)
(2201) = 0101 (05H)
Multiplicand Multiplier Result
1100 (1210) 0101 (510) 12 ´ 5 = 6010
For simplicity, Multiplicand and Multiplier are taken 4-bit each.

Steps Product Multiplier Comments

B 7 B 6 B5 B4 B3 B2 B1 B 0 CY B 3 B 2 B1 B 0

0 0 0 0 0 0 0 0 0 0 1 0 1 Initial stage

Step 1 0 0 0 0 0 0 0 0 0 1 0 1 0 Shift left by 1

0 0 0 0 0 0 0 0 0 1 0 1 0 Don’t Add since CY = 0

Step 2 0 0 0 0 0 0 0 0 1 0 1 0 0 Shift

0 0 0 0 1 1 0 0 1 0 1 0 0 Add multiplicand Since CY = 1

Step 3 0 0 0 1 1 0 0 0 0 1 0 0 0 Shift left by 1

0 0 0 1 1 0 0 0 0 1 0 0 0 Don’t Add since CY=0

Step 4 0 0 1 1 0 0 0 0 1 0 0 0 0 Shift left by 1

0 0 1 1 1 1 0 0 1 0 0 0 0 Add multiplicand Since CY = 1

Source program :
LXI H, 2200H ; Initialize the memory pointer
MOV E, M ; Get multiplicand
MVI D, 00H ; Extend to 16-bits
INX H ; Increment memory pointer
MOV A, M ; Get multiplier
LXI H, 0000H ; Product = 0
MVI B, 08H ; Initialize counter with count 8
MULT : DAD H ; Product = product ´ 2
RAL
JNC SKIP ; Is carry from multiplier 1 ?
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Microprocessors and Microcontroller 3 - 30 Looping, Counting, Time Delays & Code Conversion

DAD D ; Yes, Product =Product + Multiplicand

SKIP : DCR B ; Is counter = zero
JNZ MULT ; no, repeat
SHLD 2300H ; Store the result
HLT ; End of program

Flowchart :

Start

Product = 0
Count = 8
Multiplicand = (2200H)
Multiplier = (2201H)

Product = 2 X product
( Shift left 1 bit )
Multiplier = 2 X multiplier
(Shift left 1 bit )

Is
No carry from
Multiplier 1
?

Yes

Product = product + Multiplicand

Count = count – 1
Yes

No Is
count = 0
?

Yes

(2300H) and (2301H) = product

End

Lab Experiment 43 : Divide 16-bit number with 8-bit number using shifting technique.
Statement : Divide the 16-bit unsigned number in memory locations 2200H and 2201H
(most significant bits in 2201H) by the 8-bit unsigned number in memory location 2300H
store the quotient in memory location 2400H and remainder in 2401H.
Assumption : The most significant bits of both the divisor and dividend are zero.
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Sample problem :
For simplicity, Dividend and divisor are taken 8-bit and 4-bit respectively
Dividend = 0110 0001 (61H) Divisor = 0111 (07H)

Steps Dividend Quotient Comment

B7 B 6 B5 B4 B3 B2 B 1 B0 B3 B 2 B1 B 0

0 1 1 0 0 0 0 1 0 0 0 0 Initial stage

Step 1 1 1 0 0 0 0 1 0 0 0 0 0 Shift left

0 1 0 1 0 0 1 0 0 0 0 1 MSB of dividend = MSB dividend – divisor

and Quotient = Quotient + 1 since
MSB of dividend > divisor

Step 2 1 0 1 0 0 1 0 0 0 0 1 0 Shift left

0 0 1 1 0 1 0 0 0 0 1 1 MSB of dividend = MSB dividend – divisor

and Quotient = Quotient + 1 since
MSB of dividend > divisor

Step 3 0 1 1 0 1 0 0 0 0 1 1 0 Shift left

0 1 1 0 1 0 0 0 0 1 1 0 No change since MSB of dividend < divisor

Step 4 1 1 0 1 0 0 0 0 1 1 0 0 Shift left

0 1 1 0 0 0 0 0 1 1 0 1 MSB of dividend = MSB dividend – divisor

and Quotient = Quotient + 1 since
MSB of dividend > divisor

Source program :
MVI E, 00 ; Quotient = 0
LHLD 2200H ; Get dividend
LDA 2300 ; Get divisor
MOV B, A ; Store divisor
MVI C, 08 ; Count = 8
NEXT : DAD H ; Dividend = Dividend ´ 2
MOV A, E
RLC
MOV E, A ; Quotient = ´ 2
MOV A, H ;
SUB B ; Is most significant byte of Dividend
; > divisor
JC SKIP ; No, go to Next step
MOV H, A ; Yes, subtract divisor
INR E ; and Quotient = Quotient + 1
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Microprocessors and Microcontroller 3 - 32 Looping, Counting, Time Delays & Code Conversion

SKIP : DCR C ; Count = Count – 1

JNZ NEXT ; Is count = 0 repeat
MOV A, E
STA 2401H ; Store Quotient
MOV A, H
STA 2401H ; Store remainder
HLT ; End of program.

Flowchart :
Start

Dividend (2200H) and (2201H)

Divisor (2300H)
Count = 8
Quotient = 0

Dividend = Dividend X 2
Quotient = Quotient X 2

Is
Divisor < = Yes
8 MSBS of
Dividend
?
8 MSBS of dividend = 8 MSBS of
No dividend – divisor
Quotient = Quotient + 1

Count = count –1

No Is
count = 0
?

Yes

(2400H) = Quotient
(2401 H) = Remainder

End

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Microprocessors and Microcontroller 3 - 33 Looping, Counting, Time Delays & Code Conversion

Lab Experiment 44 : Simulate DAA instruction.

Statement : Assume the DAA instruction is absent. Write a subroutine which will perform
the same task as DAA instruction

Flowchart :

Start

Mask upper nibble

Is
number > 9 No
or AC = 1
?

Yes

Add 6 in the number

Get the number

Mask lower nibble

Rotate number right 4 bits

Is
number > 9 No
or CY = 1
?

Yes

Add 60H in the number

End

Sample Problem :
Let us see the execution of DAA instruction.
1. If the value of the low order four bits (D 3 -D 0 ) in the accumulator is greater than 9
or if auxiliary carry flag is set, the instruction adds 6 (06) to the low-order four
bits.

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Microprocessors and Microcontroller 3 - 34 Looping, Counting, Time Delays & Code Conversion

2. If the value of the high-order four bits (D7-D4) in the accumulator is greater than 9
or if carry flag is set, the instruction adds 6(06) to the high-order four bits.

Note : To check auxiliary carry flag it is necessary to get the flag register contents in
one of the registers and then we can check the auxiliary carry flag by checking bit 4 of
that register. To get the flag register contents in any general purpose register we require
stack operation and therefore stack pointer is initialized at the beginning of the source
program.

Source program :
LXI SP, 27FFH ; Initialize stack pointer
MOV E, A ; Store the contents of accumulator
ANI 0FH ; Mask upper nibble
CPI 0AH ; Check if number is greater than 9
JC SKIP ; If no go to skip
MOV A, E ; Get the number
ADI 06H ; Add 6 in the number
JMP SECOND ; Go for second check
SKIP : PUSH PSW ; Store accumulator and flag contents
; in stack
POP B ; Get the contents of accumulator in B
; register and
; flag register contents in C register
MOV A, C ; Get flag register contents in
; accumulator
ANI 10H ; Check for bit 4
JZ SECOND ; If zero, go for second check
MOV A, E ; Get the number
ADI 06 ; Add 6 in the number
SECOND : MOV E, A ; Store the contents of accumulator
ANI F0H ; Mask lower nibble
RRC
RRC
RRC
RRC ; Rotate number 4 bit right
CPI 0AH ; Check if number is greater than 9
JC SKIP1 ; If no go to skip 1
MOV A, E ; Get the number
ADI 60H ; Add 60 H in the number

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Microprocessors and Microcontroller 3 - 35 Looping, Counting, Time Delays & Code Conversion

JMP LAST ; Go to last

SKIP1 : JNC LAST ; If carry flag = 0 go to last
MOV A, E ; Get the number
ADI 60 H ; Add 60 H in the number
LAST : HLT

Lab Experiment 45 : Program to test RAM.

Statement : Write an assembly language program with proper comments to perform
following operations :
To test RAM by writing ‘1’ and reading it back and later writing ‘0’ (zero) and reading
it back. RAM addresses to be checked are 4000H to 40FFH. In case of any error, it is
indicated by writing 01H at port 10H.

Source Program :
LXI H, 4000H ; Initialize memory pointer
BACK : MVI M, FFH ; Writing ‘1’ into RAM
MOV A, M ; Reading data from RAM
CPI FFH ; Check for ERROR
JNZ ERROR ; If yes go to ERROR
INX H ; Increment memory pointer
MOV A, H
CPI 50H ; Check for last check
JNZ BACK ; If not last repeat
LXI H, 4000H ; Initialize memory pointer
BACK1 : MVI M, 00H ; Writing ‘0’ into RAM
MOV A, M ; Reading data from RAM
CPI 00H ; Check for ERROR
INX H ; Increment memory pointer
MOV A, H
CPI 50H ; Check for last check
JNZ BACK1 ; If not last, repeat
HLT ; Stop execution

Lab Experiment 46 : Write an assembly language program to generate fibonacci number.

MVI D, COUNT ; Initialize counter
MVI B, 00 ; Initialize variable to store previous
; number
MVI C, 01 ; Initialize variable to store current
; number

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BACK : MOV A, B ; [Add two

ADD C ; numbers ]
MOV B, C ; Current number is now previous number
MOV C, A ; Save result as a new current number
DCR D ; Decrement count
JNZ BACK ; If count ¹ 0 go to BACK
HLT ; Stop.

Lab Experiment 47 : Program to evaluate a 2 + b 2

2 2
Statement :Write 8085 assembly language program to perform the following, a + b ,
where a and b are 8 - bit binary numbers. Explain with algorithm and flowchart.
Dec.-08, Marks 10

Algorithm
1. Read number a.
2. Find a2 by performing a ´ a and store result 1.
3. Read number b.
4. Find b2 by performing b ´ b and store result 2.
5. Result = Result 1 + Result 2

Flowchart
See flowchart on next page.

Refer Lab experiment 42 for the flowchart of multiplication routine.

Program
MVI E, Number a ; Get the number a
CALL MULTIPLY ; Call multiply subroutine
SHLD 2200H ; Store result 1
MVI E, Number b ; Get the number b
CALL MULTIPLY ; Call multiply subroutine
XCHG ; Store result 2 in DE
LHLD 2200H ; Get the result 1 in HL
DAD D ; HL ¬ HL + DE
HLT ; Stop
MULTIPLY : MVI D, 00 ; Extend to 16-bit
MOV A, E ; Multiplier = multiplicand
LXI H, 0000H ; Product = 0
MVI B, 08H ; Initialize counter with count 8
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Microprocessors and Microcontroller 3 - 37 Looping, Counting, Time Delays & Code Conversion

Start

Read a

Multiplicand = a
Multiplier = a

Call Multiply

Store result 1

Read b

Multiplicand = b
Multiplier = b

Call multiply

Store result 2

Result = Result 1 + Result 2

Stop

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Microprocessors and Microcontroller 3 - 38 Looping, Counting, Time Delays & Code Conversion

MULT: DAD H ; Product = product ´ 2

RAL
JNC SKIP ; Is carry from multiplier 1 ?
DAD D ; Yes, Product =Product + Multiplicand
SKIP: DCR B ; Is counter = zero
JNZ MULT ; no, repeat
RET ; Return to main program

Lab Experiment 48 : Program to count given data in a set of numbers Dec.-08, Marks 6

Statement : Write a program to count the number of times the data 02 is present in a set of
20 numbers.
It is assumed that set of 20 numbers are stored from memory location 2000H.

LXI, 2000H ; Initialize memory pointer

MVI B, 14H ; Initialize counter
MVI C, 00H ; Count = 0
BACK : MOV A, M ; Get the number
CPI 02H ; Compare with 02
JNZ NEXT ; If not zero skip next instruction
INR C ; Increment count
NEXT : INX H ; Increment memory pointer
DCR B ; Decrement counter
JNZ BACK ; If not zero, repeat
HLT ; Stop

Lab Experiment 49 : Program to multiply two 16-bit numbers June-09, Marks 12

Statement : Write an assembly language program in 8085 to multiply two 16-bit numbers.
LXI SP, 27FFH ; Initialize stack pointer
LXI H, 0000H ; Result = 0 (Lower word)
SHLD 2000H ; Result = 0 (Higher word)
LXI D, number 1 ; Multiplicand
LXI B, number 2 ; Multiplier as a counter
BACK : DAD D ; Result (HL) = HL + DE
JNC NEXT ; If no carry goto NEXT
PUSH H ; Save HL register
LHLD 2000H ; Get the higher word
INX H ; Increment word by 1
SHLD 2000H ; Save higher word
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Microprocessors and Microcontroller 3 - 39 Looping, Counting, Time Delays & Code Conversion

POP H ; Get the lower word in HL

DCX B ; Decrement counter
MOV A, B ; Check whether
ORA C ; BC is zero
JNZ BACK ; if not zero, repeat
XCHG ; Exchange DE and HL
LHLD 2000H ; Get the higher word in HL
HLT ; Stop
The 32-bit answer of multiplication is in HL and DE register. The lower word is in DE
register and higher word is in HL register.

3.2 Timers
In the real time applications, such as traffic light control, digital clock, process control,
serial communication, it is important to keep a track with time. For example in traffic light
control application, it is necessary to give time delays between two transitions. These time
delays are in few seconds and can be generated with the help of executing group of
instructions number of times. This software timers are also called time delays or software
delays. Let us see how to implement these time delays or software delays.
As you know microprocessor system consists of two basic components, Hardware and
software. The software component controls and operates the hardware to get the desired
output with the help of instructions. To execute these instructions, microprocessor takes fix
time as per the instruction, since it is driven by constant frequency clock. This makes it
possible to introduce delay for specific time between two events. In the following section
we will see different delay implementation techniques.

3.2.1 Timer Delay using NOP Instruction

NOP instruction does nothing but takes 4T states of processor time to execute. So by
executing NOP instruction in between two instructions we can get delay of 4 T-state
1
1 T state =
Operating frequency of 8085

3.2.2 Timer Delay using Counters

Counting can create time delays. Since the execution times of the instructions used in a
counting routine are known, the initial value of the counter, required to get specific time
delay can be determined.

Using 8-bit counter :

Number of T-states
MVI C, count ; Load count 7 T-states
BACK : DCR C ; Decrement count 4 T-states
JNZ BACK ; If count ¹ 0, repeat 10/7 T-states
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Microprocessors and Microcontroller 3 - 40 Looping, Counting, Time Delays & Code Conversion

In this program, the instructions DCR C and JNZ BACK execute number of times
equal to count stored in the C register. The time taken by this program for execution can
be calculated with the help of T-states. The column to the right of the comments indicates
the number of T-states in the instruction cycle of each instruction. Two values are specified
for the number of T-states for the JNZ instruction. The smaller value is applied when the
condition is not met, and the larger value applied when it is met. The first instruction
MVI C, count executed only once and it requires 7 T-states. There are count – 1 passes
through the loop where the condition is met and control is transferred back to the first
instruction in the loop (DCR C). The number of T-states that elapse while C is not zero are
(count - 1) ´ (4+10). On the last pass through the loop, the condition is not met and the
loop is terminated. The number of T states that elapse in this pass are 4 + 7.
\ Total T-states required to execute the given program
= 7 + (count–1) ´ (4 + 10 ) + (4 + 7)
MVI C Loops Last loop
For count = 5
Number of T-state = 7 + (5 –1) ´ (14) + (11)
= 7 + 56 + 11
= 74
Assuming operating frequency of 8085A is 2 MHz,
1
Time required for 1 T-state =
2 MHz
= 0.5 msec
Total time required to execute the given program = 74 ´ 0.5 msec.
= 37 msec.
Maximum delay possible with 8-bit count.
The maximum count that can be loaded in the 8 bit register is FFH (255) so the
maximum delay possible with 8 bit count, assuming operating frequency 2 MHz
= (7 + (255 – 1) ´ (14) + (11)) ´ 0.5 msec.
= 1787 msec.
With these calculations, it can be noticed that delay with 8 bit count suitable for small
delays and not for large delays.

Using 16-bit counter :

Number of T-states
LXI B, count ; load 16 bit count 10 T-states
BACK : DCX B ; Decrement count 6 T-states
MOV A, C ; 4 T-states
ORA B ; logically OR B and C 4 T-states
JNZ BACK ; If result is not 0, repeat 10 T-states

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Microprocessors and Microcontroller 3 - 41 Looping, Counting, Time Delays & Code Conversion

In this program, the instructions DCX B, MOV A, C, ORA B and JNZ BACK execute
number of times equal to count stored in BC register pair. The instruction LXI B, count is
executed only once. It requires 10 T-states. The number of T-states required for
one loop = 6 + 4 + 4 + 10 = 24 T-states. The number of T-states required for
last loop = 6 + 4 + 4 + 7 = 21 T-states. So total T-states required for execution of given
program are
= 10 + (count–1) ´ 24 + 21
LXI B Loops Last loop
for count = 03FFH (102310 )
Number of T-states = 10 + (1022) ´ 24 + 21
= 24559
Assuming operating frequency of 8085A as 2 MHz, the time required for,
T state = 0.5 msec.
\ Total time required to execute the given program
= 24559 ´ 0.5 msec
= 12279.5 msec
= 12.2795 msec

Maximum delay possible with 16-bit count

The maximum count that can be loaded in the 16 bit register pair is FFFFH (65535 H).
So the maximum delay possible with 8 bit count, assuming operating frequency 2 MHz.
= 10(10 + (65535 – 1) ´ (24) + (21)) ´ 0.5 msec
= 0.786425 sec
If the application requires the delays more than this, then the nested loop technique is
used to implement the delays.

3.2.3 Timer Delay using Nested Loops

In this, there are more than one loops. The innermost loop is same as explained above.
The outer loop sets the multiplying count to the delays provided by the innermost loop.
Number of T states
MVI B, Multiplier count ; Initialize multiplier 7 T-states
START : MVI C, Delay count ; Initialize delay count 7 T-states
BACK : DCR C ; Decrement delay count 4 T-states
JNZ BACK ; If not 0, repeat 10/7 T-states
DCR B ; Decrement multiplier count 4 T-states
JNZ START ; If not 0, repeat 10/7 T-states
T-states required for execution of inner loop
Tinner = 7 + (Delay count – 1 ) ´ 14 + 11
T-states required for execution of the given program
= (Multiplier count – 1) ´ (Tinner +14) +11
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Microprocessors and Microcontroller 3 - 42 Looping, Counting, Time Delays & Code Conversion

For delay count = 65H (101) and multiplier count

= 51H (81)
Tinner = 7+(101–1) ´ 14 + 11
= 1418
Total time required to execute the given program is
(Operating frequency is 2 MHz) = [(81–1) ´ (1418 + 14) +11] ´ 0.5 msec.
= 57.2855 msec.

Lab Experiment 50 : Generate a delay of 0.4 seconds.

Statement : Write a program to generate a delay of 0.4 sec if the crystal frequency is
5 MHz.
Solution : In 8085, the operating frequency is half of the crystal frequency,
\ Operating frequency = 5/2 = 2.5 MHz
1
\ Time for one T-state = = 0.4 msec
2.5 MHz
Required Time 0.4 sec
Number of T-states required = =
Time for 1 T - state 0.4 msec

= 1 ´ 10 6

Delay Program :
LXI B, count ; 16-bit count
BACK : DCX B ; Decrement count
MOV A, C
ORA B ; Logically OR B and C
JNZ BACK ; If result is not zero repeat
1 ´ 10 6 = 10 + (count – 1) ´ 24 + 21
æ 1 ´ 10 6 – 31 ö
count = ç ÷ + 1 » 41666
ç 24 ÷ 10
è ø
count = 41666 10
= A2C2H

Lab Experiment 51 : Generate and display binary up counter.

Statement : Write a program for displaying binary up counter. Counter should count
numbers from 00 to FFH and it should increment after every 0.5 sec.
Assume operating frequency of 8085 equal to 2 MHz. Display routine is available.
Solution :
LXI SP, 27FFH ; Initialize stack pointer
MVI C, 00H ; Initialize counter
BACK : CALL Display ; Call display subroutine
CALL Delay ; Call delay subroutine
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INR C ; Increment counter

MOV A, C ;
CPI 00H ; Check counter is > FFH
JNZ BACK ; If not, repeat
HLT ; Stop

Delay Subroutine :
Delay : LXI D, count ; Initialize count
BACK : DCX D ; Decrement count
MOV A, E ;
ORA D ; Logically OR D and E
JNZ BACK ; If result is not 0 repeat
RET ; Return to main program

Flowchart :

Start

Initialize counter = 00
Delay

Call display
Initialize counter

Call delay
Decrement counter

Increment counter

No Is
counter = 0
?
No Is
count > FFH Yes
?
RET
Yes

Stop

Operating frequency = 2 MHz

1
\ Time for one T-state = = 0.5 msec
2 MHz

Required Time 0.5 sec

Number of T-states required = = = 1 ´ 10 6
Time for 1 T - state 0.5 msec

1 ´ 10 6 = 10 + (count – 1) ´ 24 + 21
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Microprocessors and Microcontroller 3 - 44 Looping, Counting, Time Delays & Code Conversion

æ 1 ´ 10 6 – 31 ö
count = ç ÷+1 » 4166610
ç 24 ÷
è ø
count = 4166610 = A2C2H

Lab Experiment 52 : Generate and display BCD up counter with frequency 1 Hz.
Statement : Write a program for displaying BCD up counter. Counter should count
numbers from 00 to 99H and it should increment after every 1 sec. Assume operating
frequency of 8085 equal to 3 MHz. Display routine is available.
Solution :
LXI SP, 27FFH ; Initialize stack pointer
MVI C, 00H ; Initialize counter
BACK : CALL Display ; Call display subroutine
CALL Delay ; Call delay subroutine
MOV A, C ;
ADI , 01 ; Increment counter
DAA ; Adjust it for decimal
MOV C, A ; Store count
CPI ,00 ; Check count is > 99
JNZ BACK ; If not, repeat
HLT ; Stop

Delay Subroutine :
Delay : MVI B, Multiplier-count ; Initialize multiplier count
BACK1: LXI D, Initialize Count
BACK : DCX D ; Decrement count
MOV A, E ;
ORA D ; Locally OR D and E
JNZ BACK ; If result is not 0, repeat
DCR B ; Decrement multiplier count
JNZ BACK1 ; If not zero, repeat
RET ; Return to main program.
Operating frequency : 3 MHz
1
\ Time for one T-state = = 0.333 msec
3 MHz

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Microprocessors and Microcontroller 3 - 45 Looping, Counting, Time Delays & Code Conversion

Flowchart :

Start

Initialize counter = 0

Call display
Delay

Call delay
Initialize counter

Increment counter
Decrement counter

Adjust it for decimal

No Is
counter = 0
?
No Is
count > 99 Yes
?
RET
Yes

Stop

Required Time
\ Number of T-states required = = 3 ´ 10 6
Time for 1- T state
1 sec
=
0.333 msec
Let us take multiplier count = 3.
3 ´ 10 6
\ Number of T-states required by inner loop = = 1 ´ 10 6
3
\ 1 ´ 10 6 = 10 + (count – 1) ´ 24 + 21
» 4166610
count = 4166610 = A2C2H

Lab Experiment 53 : Generate and display BCD down counter with frequency 1 Hz
Statement : Write a program for displaying BCD down counter. Counter should count
numbers from 99 to 00 and it should decrement after every 1 sec. Assume display and
delay routines are available.

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Solution : Flowchart :

Start

Initialize counter = 99

Call display

Call delay

Decrement and adjust counter

for its decimal value

No Is
count < 0
?

Yes

End

Source program with logic 1 :

LXI SP, 27FFH ; Initialize stack pointer
MVI A, 99H ; Initialize counter
BACK : CALL Display ; Call display subroutine
CALL Delay ; Call Delay subroutine
ADI 99H ; * (Explained later)
DAA ; Adjust for decimal
CPI 99H ; Compare with last count
JNZ BACK ; If no, repeat
HLT
* Addition :
1001 1001 99H
+ 1001 1001 99H
10011 0010

DAA + 0110 0110

1001 1000 98H

Program with logic 2 :

LXI SP, 27FFH ; Initialize stack pointer
MVI C, 99H ; Initialize counter = 99
BACK : Call Display ; Call display subroutine
Call Delay ; Call delay subroutine
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MOV A, C ; Get the count

ANI 0FH ; Check for lower nibble
JNZ SKIP ; If it is not 0FH go to skip
MOV A, C ; Else get the count
SBI 06 ; and subtract 6
MOV C, A ; Store the count
SKIP : DCR C ; Decrement count
MOV A, C ; Get the count
CPI 99H ; Check it for last count
JNZ BACK ; If not, repeat
HLT ; Stop

Lab Experiment 54 : Generate and display the contents of decimal counter.

Statement : Write assembly language program to with proper comments for the following :
To display decimal decrementing counter (99 to 00) at port 05 H with delay of half
seconds between each count. Write as well the delay routine giving delay of half seconds.
Operating frequency of microprocessor is 3.072 MHz. Neglect delay of the main program.

Source program :
MVI C, 99H ; Initialize counter
BACK : MOV A, C ;
ANI 0F ; Mask higher nibble
CPI 0F
JNZ SKIP
MOV A, C
SUI 06 ; Subtract 6 to adjust decimal count
MOV D, A
SKIP : MOV A, C
OUT 05 ; send count on output port
CALL Delay ; Wait for 0.5 seconds
DCR C ; decrement count
MOV A, C
CPI FF
JNZ BACK ; If not zero, repeat
HLT ; Stop execution
Delay subroutine :
Delay : LXI D, Count
Back : DCX D ; 6 T-states
MOV A, D ; 4 T-states
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ORA E ; 4 T-states
JNZ Back ; 10 T-states
RET
1 1
1 T-state = =
Operating frequency 3.072 ´ 10 6

= 3.2552 ´ 10 –7

0.5 sec
Number of T-states required = = 1.536 ´ 10 6
3.2552 ´ 10 –7

1.536 ´ 10 6 = 10 + (count – 1) ´ 24 + 21

1.536 ´ 10 6 – 31
Count = + 1 = 63999.708
24

= 64000

= FA00H

Lab Experiment 55 : Identify the error and correct the given delay routine.
Statement : The delay routine given below is in infinite loop, identify the error. Correct
the program, give the machine cycles and T states of each instruction and also find the
maximum delay generated. Assume 1 "T" state = 320 ns.
DELAY : LXI H, N
L1 : DCX H
JNZ L1
Solution : 1) The fault in the above program is at instruction JNZ L1. This condition
always evaluates to be true hence loops keeps on executing and hence infinite loop.
2) Reason for infinite looping : - The instruction DCX H decrease the HL pair count
one by one but it does not affect the zero flag. So when count reaches to 0000H in HL pair
zero flag is not affected and JNZ L1 evaluates to be true and loop continues. Now HL
again decrements below 0000H and HL becomes FFFFH and thus execution continues.
3) The modification in the program is as follows :
No. of T states
DELAY : LXI H, N ; Load 16 bit count ® 10 T-states
L1 : DCX H ; Decrement count ® 6 T-states
MOV A, L ; ® 4 T-states
ORA H ; logically OR H and L ® 4 T-states
JNZ L1 ; If result is not 0 repeat ® 10 T-states
\ Total number of T states required for program execution are
= 10 + (count – 1) ´ 24 + 21
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LXI H + Loops Last Loop

T-states for maximum delay = ?
Now maximum count that can be loaded in 16 bit register pair is FFFFH (65535H) so
[T-states for max. delay = 10 + (65535 – 1) ´ 24 + 21]
= 1.57247 ´ 106
Time for 1 T state = 320 ns
\ Max. delay = 1.575247 ´ 10 6 ´ 320 ns

= 0.50407904 seconds

3.3 Code Conversion

This technique allows programmer to translate a number represented using one coding
system to another. For example, when we accept any number from the keyboard it is in
ASCII code. But for processing, we have to convert this number in its hex equivalent. The
code conversion involves some basic conversions such as
· BCD to binary conversion
· Binary to BCD conversion
· BCD to seven segment code conversion
· Binary to ASCII conversion and
· ASCII to binary conversion.

3.3.1 BCD to Binary Conversion

We are more familiar with the decimal number system. But the microprocessor
understands the binary/hex number system. To convert BCD number into its binary
equivalent we have to use the principle of positional weighting in a given number.

For example : 67 = 6 ´ 0AH + 7

= 3CH + 7 = 43H

To perform above operation it is necessary to separate an 8-bit packed BCD number

into two 4-bit unpacked BCD digits : BCD1 and BCD2 and then convert each digit into its
binary value according to its positions. Finally, add both binary numbers to obtain the
binary equivalent of the BCD number. Let us see the program for 2-digit BCD to binary
conversion.

Lab Experiment 56 : 2-Digit BCD to binary conversion.

Statement : Convert a 2-digit BCD number stored at memory address 2200H into its
binary equivalent number and store the result in a memory location 2300H.

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Sample Problem :
(2200H) = 67H
(2300H) = 6 ´ 0AH + 7 = 3CH + 7 = 43H

Source Program :
LDA 2200H ; Get the BCD number
MOV B, A ; Save it
ANI 0FH ; Mask most significant four bits
MOV C, A ; Save unpacked BCD1 in C register
MOV A, B ; Get BCD again
ANI F0H ; Mask least significant four bits
RRC ; Convert most significant four
RRC ; bits into unpacked BCD2
RRC ;
RRC ;

Flowchart :

Start

Get the number

Mask upper Nibble

and
store number as BCD1

Get number again

Mask lower Nibble

exchange nibble
positions of result and
store it as BCD2

Multiply BCD2
number by 10

Add BCD1

Store result

Stop

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MOV B, A ; Save unpacked BCD2 in B register

XRA A ; Clear accumulator (sum = 0)
MVI D, 0AH ; Set D as a multiplier of 10
SUM : ADD D ; Add 10 until (B) = 0
DCR B ; Decrement BCD2 by one
JNZ SUM ; Is multiplication complete ?
; if not, go back and add again
ADD C ; Add BCD1
STA 2300H ; Store the result
HLT ; Terminate program execution

3.3.2 Binary to BCD Conversion

We know that microprocessor processes data in the binary form. But when it is
displayed, it is in the BCD form. In this case we need binary to BCD conversion of data.
The conversion of binary to BCD is performed by dividing the number by the power of
ten.
For example, assume the binary number as
0111 1011 (7BH) = 12310

To represent the number in BCD requires twelve bits or three BCD digits as shown
below
12310 = 0001 0010 0011
Digit2 digit1 digit0

The conversion can be performed as follows

Step 1 : If the number is equal to or greater than 100, divide number by 100 (i.e.
subtract 100 repeatedly until the remainder is less than 100). The quotient
gives the most significant digit, digit 2 of the BCD number. If number is less
than 100 go to step 2.

Step 2 : If the number i.e. remainder of first division is equal to or greater than 10
divide number by 10 repeatedly until the remainder is less than 10. The
quotient gives the digit 1. If number is less than 10, go to step 3.

Step 3 : The remainder from step 2 gives the digit 3.

Let us see the program for binary to BCD conversion.

Lab Experiment 57 : Binary to BCD conversion.

Statement : Write a main program and a conversion subroutine to convert the binary
number stored at 6000H into its equivalent BCD number. Store the result from memory
location 6100H.
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Sample Problem : (6000)H = 8AH

1. 8AH ³ 64H (Decimal 100) \ Divide by 64H (Decimal 100)
8AH/64H ® Quotient = 1 Remainder = 26H
26H < 64H (Decimal 100) \ goto step 2 and Digit 2 = 1
2. 26H ³ 0AH (Decimal 10) \ Divide by 0AH (Decimal 10)
26H/0AH ® Quotient = 3 Remainder = 08H
08H < 0AH (Decimal 10) \ goto step 3 and Digit 1 = 3
3. Digit 0 = 08H

Source Program :
LXI SP, 27FFH ; Initialize stack pointer
LDA 6000H ; Get the binary number in accumulator
CALL BIN TO BCD ; Call subroutine BIN TO BCD
HLT ; Terminate program execution

Flowchart :
Start

Get the binary

number

Check if Yes
number
is > 100
Divide number by 100

No

Digit 2 = 0 Digit 2 = Quotient

Check if Yes
reminder
is > 10
Divide number by 10

No

Digit 1 = 0 Digit 1 = Quotient

Digit 0 = reminder

Stop

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Subroutine to convert binary number into its equivalent

BCD number
BIN TO BCD :
PUSH B ; Save BC register pair contents
PUSH D ; Save DE register pair contents
MVI B, 64H ; Load divisor decimal 100 in B register
MVI C, 0AH ; Load divisor decimal 10 in C register
MVI D, 00H ; Initialize Digit 1
MVI E, 00H ; Initialize Digit 2
STEP1 : CMP B ; Check if number < Decimal 100
JC STEP 2 ; If yes go to step 2
SUB B ; Subtract decimal 100
INR E ; Update quotient
JMP STEP1 ; Go to step 1
STEP2 : CMP C ; Check if number < Decimal 10
JC STEP 3 ; If yes go to step 3
SUB C ; Subtract decimal 10
INR D ; Update quotient
JMP STEP 2 ; Continue division by 10

STEP3 : STA 6100H ; Store Digit 0

MOV A, D ; Get Digit 1
STA 6101H ; Store Digit 1
MOV A, E ; Get Digit 2
STA 6102H ; Store Digit 2
POP D ; Restore DE register pair contents
POP B ; Restore BC register pair contents
RET ; Return to main program

3.3.3 BCD to Seven Segment Conversion

Many times 7-segment LED display is used to display the results or parameters in the
microprocessor system. In such cases we have to convert the result or parameter in
7-segment code. This conversion can be done using look-up technique. In the look-up table
the codes of the digits (0-9) to be displayed are stored sequentially in the memory. The
conversion program locates the code of a digit based on its BCD digit. Let us see the
program for BCD to common cathode 7-segment code conversion.

Lab Experiment 58 : Find the 7-segment codes for given numbers.

Statement : Find the 7-segment codes for given 5 numbers from memory location 6000H
and store the result from memory location 7000H.

Source Program :
LXI H, 6200H ; Initialize lookup table pointer
LXI D, 6000H ; Initialize source memory pointer
LXI B, 7000H ; Initialize destination memory pointer
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BACK : LDAX D ; Get the number

MOV L, A ; A point to the 7-segment code
MOV A, M ; Get the 7-segment code
STAX B ; Store the result at destination memory
; location
INX D ; Increment source memory pointer
INX B ; Increment destination memory pointer
MOV A, C
CPI 05H ; Check for last number
JNZ BACK ; If not repeat
HLT ; End of program

Flowchart :

Start

Initialize lookup table pointer

Lookup Table

Initialize source memory pointer Digit Code

Initialize destination memory pointer
0 3F

1 06
Get the number
2 5B

3 4F
Find the 7-segment code
4 66

Store 7 segment code in the 5 6D

destination memory location
6 7D

7 07
Increment source memory pointer
Increment destination memory pointer 8 7F

9 6F

Is
No last
number
?
Yes

Stop

3.3.4 Binary to ASCII Code Conversion

The ASCII Code (American Standard Code for Information Interchange) is commonly
used for communication. In such cases we need to convert binary number to its ASCII
equivalent. It is a seven bit code. In this code number 0 through 9 are represented as 30
through 39 respectively and letters A through Z are represented as 41H through 5AH.

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Therefore, by adding 30H we can convert number into its ASCII equivalent and by adding
37H we can convert letter to its ASCII equivalent. Let us see the program for binary to
ASCII code conversion.

Lab Experiment 59 : Find the ASCII character.

Statement : Write an assembly language program to convert the contents of the five
memory locations starting from 2000H into an ASCII character. Place the result in another
five memory locations starting from 2200H.

Flowchart :

Start

Initialize source memory

pointer

Initialize destination memory

pointer Start

Initialize count = 5
Is Yes
number > A
Get the number ?

No
CALL ASCII Number = number + 30 Number = number + 37

Store the number

RET

Decrement source memory pointer

Decrement destination memory pointer

Decrement counter

No Is
count = 0
?

Yes

End

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Sample Problem :
(2000H) = 1
(2001H) = 2
(2002H) = 9
(2003H) = A
(2004H) = B Result (2200H) = 31
(2201H) = 32
(2202H) = 39
(2203H) = 41
(2204H) = 42

Subroutine Documentation :
Subroutine ‘ASCII’ converts a hexadecimal digit to ASCII.
Passing parameter : The digit is passed using accumulator.
Return value : In the accumulator.
Register used : Accumulator.
Stack used : From 27FEH to 27FDH

Source Program :
LXI SP, 27FFH ; Initialize stack pointer
LXI H, 2000H ; Source memory pointer
LXI D, 2200H ; Destination memory pointer
MVI C, 05H ; Initialize the counter
BACK : MOV A, M ; Get the number
CALL ASCII ; Call subroutine ASCII
STAX D ; Store result
INX H ; Increment source memory pointer
INX D ; Increment destination memory pointer
DCR C ; Decrement count by 1
JNZ BACK ; if not zero, repeat
HLT ; Stop program execution subroutine ASCII
ASCII : CPI, 0AH ; Check if number is 0AH
JNC NEXT ; If yes goto next otherwise continue
ADI 30H ;
JMP LAST
NEXT : ADI 37H
LAST : RET ; Return to main program

3.3.5 ASCII Code to Binary Conversion

It is exactly reverse process to binary to ASCII conversion. Here, if ASCII code is less
than 3AH then 30H is subtracted to get the binary equivalent and if it is in between 41H
and 5AH then 37H is subtracted to get the binary equivalent of letter (A-F).

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3.4 BCD Arithmetic

3.4.1 BCD Addition

The addition of two BCD numbers can be best understood by considering the three
cases that occur when two BCD digits are added.

Sum equals 9 or less with carry 0

Let us consider additions of 3 and 6 in BCD.
6 0110 ¬ BCD for 6
+ 3 0011 ¬ BCD for 3
------- ---------
9 1001 ¬ BCD for 9

The addition is carried out as in normal binary addition and the sum is 1 0 0 1, which
is BCD code for 9.

Sum greater than 9 with carry 0

Let us consider addition of 6 and 8 in BCD.
6 0110 ¬ BCD for 6
+ 8 1000 ¬ BCD for 8
-------- ----------
14 1110 ¬ Invalid BCD number (1110) > 9

The sum 1 1 1 0 is an invalid BCD number. This has occurred because the sum of the
two digits exceeds 9. Whenever this occurs the sum has to be corrected by the addition of
six (0110) in the invalid BCD number, as shown below
6 0110 ¬ BCD for 6
+ 8 1000 ¬ BCD for 8
-------- ----------
14 1110 ¬ Invalid BCD number
+ 0110 ¬ Add 6 for correction
-----------------------------
0001 0100 ¬ BCD for 14
1424 3 12
4 4 3
1 4
After addition of 6 carry is produced into the second decimal position.

Sum equals 9 or less with carry 1

Let us consider addition of 8 and 9 in BCD
8 1000 ¬ BCD for 8
+ 9 1001 ¬ BCD for 9
------- --------------------
17 0 0 0 1 0 0 0 1 ¬ Incorrect BCD result

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In this, case, result (0001 0001) is valid BCD number, but it is incorrect. To get the
correct BCD result correction factor of 6 has to be added to the least significant digit sum,
as shown.
8 1000 ¬ BCD for 8
+ 9 1001 ¬ BCD for 9
------- -------------------
17 00010001 ¬ Incorrect BCD result
+ 00000110 ¬ Add 6 for correction
--------------------------------------
00010111 ¬ BCD for 17
Going through these three cases of BCD addition we can summarize the BCD addition
procedure as follows :
1. Add two BCD numbers using ordinary binary addition.
2. If four-bit sum is equal to or less than 9, no correction is needed. The sum is in
proper BCD form.
3. If the four-bit sum is greater than 9 or if a carry is generated from the four-bit
sum, the sum is invalid.
4. To correct the invalid sum, add 01102 to the four-bit sum. If a carry results from
this addition, add it to the next higher-order BCD digit.
The 8085 supports DAA (Decimal Adjust Accumulator) instruction for adjusting the
result of addition to the BCD number. (See chapter 2 for DAA instruction).

Lab Experiment 60 : Add two 2-digit BCD numbers.

Statement : Add two 2 digit BCD numbers in memory location 2200H and 2201H and
store the result in memory location 2300H. Flowchart
Start

Sample problem :
Get the first BCD number
(2200H) = 39
(2201H) = 45
Get the second BCD number
Result = (2300H) = 39 + 45
= 7E + 6 = 84
(lower nibble is greater than 9 so add 6) Add two BCD numbers

Source program :
LXI H, 2200H ; Initialize pointer Adjust result to valid BCD number

MOV A, M ; Get the first number

INX H ; Increment the pointer Store the result
ADD M ; Add two numbers
DAA ; Convert HEX to valid BCD End

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STA 2300H ; Store the result

HLT ; Terminate program execution

Lab Experiment 61 : Add two 4-digit BCD numbers.

Statement : Add two 4 digit BCD numbers in HL and DE register pairs and store result in
memory locations, 2300H and 2301H. Ignore carry after 16 bit.

Sample problem :
(HL) = 3629
(DE) = 4738

Flowchart :
Start

Get the two lower digits of first BCD number

Get the two lower digits of second BCD number

Add two lower digits

Adjust result to valid BCD number

Store the result

Get the two most significant

digits of the first number

Get the two most significant

digits of the second number

Add the two most significant

digits and carry of
previous addition

Adjust result to valid BCD number

Store the result

End

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Step 1 : 29 + 38 = 61 and auxiliary carry flag = 1

\ add 06
61 + 06 = 67
Step 2 : 36 + 47 + 0 (carry of LSB) = 7D
Lower nibble of addition is greater than 9
so add 6.
7D + 06 = 83
\ Result = 8367

Source program :
MOV A, L ; Get lower 2 digits of no. 1
ADD E ; Add two lower digits
DAA ; Adjust result to valid BCD
STA 2300H ; Store partial result
MOV A, H ; Get most significant 2 digits of no. 2
ADC D ; Add two most significant digits
DAA ; Adjust result to valid BCD
STA 2301H ; Store partial result
HLT ; Terminate program execution.

3.4.2 BCD Subtraction

When two BCD numbers are subtracted we can use DAA instruction for adjusting
result to the BCD. Therefore, the subtraction of BCD number is carried out using 10's
complement or 100's complement method.
The 10's complement of a decimal number is equal to the 9's complement plus 1 and
the 100's complement of a decimal number is equal to the 99's complement plus 1. The 99's
complement of a number can be found by subtracting the number from 99. The steps for
100's complement BCD subtraction are as follows :
· Find the 100's complement of subtrahend.
· Add two numbers using BCD addition.
Let us see the program for subtraction of two BCD numbers.

Lab Experiment 62 : Subtraction of two BCD numbers.

Statement : Subtract the BCD number stored in E register from the number stored in the
D register.

Source Program :
MVI A,99H
SUB E ; Find the 99's complement of subtrahend
INR A ; Find 100's complement of subtrahend
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ADD D ; Add minuend to 100's complement of subtrahend

DAA ; Adjust for BCD
HLT ; Terminate program execution

Lab Experiment 63 : Multiply two 2-digit BCD numbers

Statement : Write an assembly language program to multiply 2 BCD numbers

Source Program :
MVI C, Multiplier ; Load BCD multiplier
MVI B, 00 ; Initialize counter
LXI H, 0000H ; Result = 0000
MVI E, multiplicand ; Load multiplicand
MVI D, 00H ; Extend to 16-bits
BACK : DAD D ; Result ¬ Result + Multiplicand
M