APEX INSTITUTE OF TECHNOLOGY

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 16 & 17
CPU Control Unit Design: Hardwired Design & DISCOVER . LEARN . EMPOWER
Micro-programmed Design Approach 1
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 What is CPU Control unit design?

 Control unit is the part of the computer’s Central Processing Unit (CPU), which directs the operation of the
processor. It was included as part of the Von Neumann Architecture by John von Neumann. It is the
responsibility of the Control Unit to tell the computer’s memory, arithmetic/logic unit and input and output
devices how to respond to the instructions that have been sent to the processor. It fetches internal
instructions of the programs from the main memory to the processor instruction register, and based on this
register contents, the control unit generates a control signal that supervises the execution of these
instructions.
 A control unit works by receiving input information to which it converts into control signals, which are then
sent to the central processor. The computer’s processor then tells the attached hardware what operations to
perform. The functions that a control unit performs are dependent on the type of CPU because the
architecture of CPU varies from manufacturer to manufacturer. Examples of devices that require a CU are:
• Control Processing Units(CPUs)
• Graphics Processing Units(GPUs)
4
5
Functions of the Control Unit
 It coordinates the sequence of data movements into, out of, and between a processor’s many sub-units.
 It interprets instructions.
 It controls data flow inside the processor.
 It receives external instructions or commands to which it converts to sequence of control signals.
 It controls many execution units(i.e. ALU, data buffers and registers) contained within a CPU.
 It also handles multiple tasks, such as fetching, decoding, execution handling and storing results.
Types of Control Unit
 There are two types of control units:
• Hardwired control unit and
• Micro-programmable control unit.
6
 Hardwired Control Unit

 In the Hardwired control unit, the control signals that are important for instruction execution control are
generated by specially designed hardware logical circuits, in which we can not modify the signal generation
method without physical change of the circuit structure.
 The operation code of an instruction contains the basic data for control signal generation. In the instruction
decoder, the operation code is decoded. The instruction decoder constitutes a set of many decoders that
decode different fields of the instruction opcode.
 As a result, few output lines going out from the instruction decoder obtains active signal values. These
output lines are connected to the inputs of the matrix that generates control signals for executive units of the
computer.
 This matrix implements logical combinations of the decoded signals from the instruction opcode with the
outputs from the matrix that generates signals representing consecutive control unit states and with signals
coming from the outside of the processor, e.g. interrupt signals. The matrices are built in a similar way as a
programmable logic arrays.
7
8
 Control signals for an instruction execution have to be generated not in a single time point but during the
entire time interval that corresponds to the instruction execution cycle.
 Following the structure of this cycle, the suitable sequence of internal states is organized in the control unit.
 A number of signals generated by the control signal generator matrix are sent back to inputs of the next
control state generator matrix.
 This matrix combines these signals with the timing signals, which are generated by the timing unit based on
the rectangular patterns usually supplied by the quartz generator.
 When a new instruction arrives at the control unit, the control units is in the initial state of new instruction
fetching. Instruction decoding allows the control unit enters the first state relating execution of the new
instruction, which lasts as long as the timing signals and other input signals as flags and state information of
the computer remain unaltered.
 A change of any of the earlier mentioned signals stimulates the change of the control unit state.
9
 This causes that a new respective input is generated for the control signal generator matrix.
 When an external signal appears, (e.g. an interrupt) the control unit takes entry into a next control state that
is the state concerned with the reaction to this external signal (e.g. interrupt processing).
 The values of flags and state variables of the computer are used to select suitable states for the instruction
execution cycle.
 The last states in the cycle are control states that commence fetching the next instruction of the program:
sending the program counter content to the main memory address buffer register and next, reading the
instruction word to the instruction register of computer.
 When the ongoing instruction is the stop instruction that ends program execution, the control unit enters an
operating system state, in which it waits for a next user directive.

10
11
 A Hard-wired Control consists of two decoders, a sequence counter, and a number of logic gates.

 An instruction fetched from the memory unit is placed in the instruction register (IR).

 The component of an instruction register includes; I bit, the operation code, and bits 0 through 11.

 The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.

 The outputs of the decoder are designated by the symbols D0 through D7.

 The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.

 The operation codes from Bits 0 through 11 are applied to the control logic gates.

 The Sequence counter (SC) can count in binary from 0 through 15.

12
 Micro-programmable Control Unit

 The fundamental difference between these unit structures and the structure of the hardwired control unit is
the existence of the control store that is used for storing words containing encoded control signals
mandatory for instruction execution.
 In microprogrammed control units, subsequent instruction words are fetched into the instruction register in
a normal way. However, the operation code of each instruction is not directly decoded to enable immediate
control signal generation but it comprises the initial address of a microprogram contained in the control
store.
With a single-level control store
 In this, the instruction opcode from the instruction register is sent to the control store address register. Based
on this address, the first microinstruction of a microprogram that interprets execution of this instruction is
read to the microinstruction register. This microinstruction contains in its operation part encoded control
signals, normally as few bit fields. In a set microinstruction field decoders, the fields are decoded. The
microinstruction also contains the address of the next microinstruction of the given instruction
microprogram and a control field used to control activities of the microinstruction address generator. 13
14
 The last mentioned field decides the addressing mode (addressing operation) to be applied to the address
embedded in the ongoing microinstruction. In microinstructions along with conditional addressing mode,
this address is refined by using the processor condition flags that represent the status of computations in the
current program. The last microinstruction in the instruction of the given microprogram is the
microinstruction that fetches the next instruction from the main memory to the instruction register.

With a two-level control store:

 In this, in a control unit with a two-level control store, besides the control memory for microinstructions, a
nano-instruction memory is included. In such a control unit, microinstructions do not contain encoded
control signals. The operation part of microinstructions contains the address of the word in the nano-
instruction memory, which contains encoded control signals. The nano-instruction memory contains all
combinations of control signals that appear in microprograms that interpret the complete instruction set of a
given computer, written once in the form of nano-instructions. 15
16
 In this way, unnecessary storing of the same operation parts of microinstructions is avoided. In this case,
microinstruction word can be much shorter than with the single level control store. It gives a much smaller
size in bits of the microinstruction memory and, as a result, a much smaller size of the entire control
memory.

 The microinstruction memory contains the control for selection of consecutive microinstructions, while
those control signals are generated at the basis of nano-instructions. In nano-instructions, control signals are
frequently encoded using 1 bit/ 1 signal method that eliminates decoding.

 The Microprogrammed Control organization is implemented by using the programming approach.

 In Microprogrammed Control, the micro-operations are performed by executing a program consisting of

micro-instructions.

 The following image shows the block diagram of a Microprogrammed Control organization.
17
 The Control memory address register specifies the address of the micro-instruction.
 The Control memory is assumed to be a ROM, within which all control information is permanently stored.
 The control register holds the microinstruction fetched from the memory.
 The micro-instruction contains a control word that specifies one or more micro-operations for the data
processor.
 While the micro-operations are being executed, the next address is computed in the next address generator
circuit and then transferred into the control address register to read the next microinstruction.
 The next address generator is often referred to as a micro-program sequencer, as it determines the address
sequence that is read from control memory.
18
Summary
 Discussed about Design of Control Unit.
 Discussed about Types of Design of Control Unit.
 Discussed about Hardwired Control Unit.
 Discussed about Microprogrammed Control.

Assessment Questions
Q1. What are Types of Design of Control Unit?
Q2. What is Microprogrammed Control?

19
THANK YOU

20
 APEX INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 18 & 19
CPU Control Unit Design: Design of a simple DISCOVER . LEARN . EMPOWER
Hypothetical CPU 1
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 Design of a simple hypothetical CPU

 Recall that the primary function of a CPU is to execute programs expressed in the processor's own machine
language. During their execution programs and their accompanying data are stored wholly or in part in a
main memory M which lies outside the CPU. To actually execute the program the CPU must perform the
following actions:
1. Determine the address in M of the first (or next as is appropriate) machine language instruction I.
2. Fetch I from M by performing one or more memory read operations.
3. Decode I to determine the operation(s) to be performed.
4. If necessary fetch any operands required by I that are stored in M; again this will require one or more
memory read operations.
5. Perform the operations specified by I.
6. If required by I, store any results in M. This will require one or more memory write operations.

4
 These steps comprise what is known as the instruction cycle or fetch-execute cycle. Steps 4, 5, and 6
together constitute the execute phase of the instruction cycle.
 During normal execution of a program the CPU repeatedly goes through the instruction cycle.
 The circuitry within the CPU to implement this process consists of:
1. An appropriate sized ALU.
2. A variety of registers for the temporary storage of addresses, instructions and data.
3. Control circuitry to properly sequence the transfers of data among the CPU's ALU and internal registers
that are needed to implement the steps of the instruction cycle for each machine language instruction.
 The organization used to connect the registers and CPU is often referred to as the data path of the CPU. We
shall describe the data path for our own hypothetical CPU (which we shall call the Relatively Simple CPU,
or simply RSCPU) and use this CPU as a vehicle for introducing processor organization principles.

5
 Data Path for a Hypothetical CPU

 We note that similar to some of the organizations on the previous page, the data path for RSCPU uses a
single 16-bit data bus organization bus which we show represented as two 8-bit data lines.
 The low order bits of the bus are shown on the right and the high order bits are shown on the left. The data
path also includes the following components:
 1. A 16-bit address register (AR) to address words in main memory. The outputs of the address register
connect it to the address lines of the system bus connecting the CPU and memory. We also assume that AR
has a control line that, when activated (high) increments its current value by 1. We denote this operation by
AR++.
 2. A 16-bit program counter (PC) that contains the address of the next instruction to be executed (not the
current instruction), or the address of the next required operand of the current instruction. We also assume
that PC has a control line that, when activated (high) increments the current value of the PC by 1. We
denote this operation by PC++.

6
7
 3. An 8-bit data register (DR) that serves as a data interface between the CPU and memory. It has separate
data lines to connect it to those of memory and separate control lines for interacting with memory. Note, in
our data path the output of DR is connected to the low order lines of the bus and is also connected directly
to the input lines of the IR and TR registers described below. Finally, we include circuitry (not shown, but
essentially tristate buffers) to allow the output of DR to also be placed on the high-order lines of the bus.

 4. An 8-bit ALU capable of performing various operations as shown in the table below. Here we assume
that X and Y are the operand inputs to the ALU and W represents the output. The operation of the ALU will
be governed the following seven control signals (ALU1,…,ALU7) according to the following table (here D
-= “don’t care”)

8
9
 5. 8-bit accumulator register (AC) that receives the results of any arithmetic or logical operation and
provides the X operand for appropriate binary arithmetic or logical operations of the ALU. It is also the
source (destination) of any programmer-initiated data transfers to (from) memory. Note that while the
output of AC is routed to the data bus and the X input of the alu, it only receives its input from the alu.
 6. 8-bit general-purpose register (R) that supplies the Y operand for appropriate binary arithmetic or logical
operations that the ALU performs. It can also be used by a programmer to store data. It is capable of
bidirectional data transfers with the (low order lines of the) data bus
 7. 8-bit instruction register (IR) which contains a copy of the op-code of the current instruction. Note, IR is
not connected to the data bus. It receives its input from the output lines of DR, and as we shall see later, its
output is directed elsewhere.
 8. 8-bit temporary register (TR) which temporarily stores data during instruction execution. Note, the output
lines of TR go to the data path’s bus, but TR receives its input from the output lines of DR.
 9. 1-bit flag register Z that is set to 1 if the last arithmetic or logical operation produced a result equal to 0.

10
Data Path Timing and Register Transfers for RSCPU
We assume that these data transfers will be coordinated by a clock pulse being transmitted throughout the data
path. It is important to know, however, just how much can be done in our data path in a single clock pulse.
This is shown below. What is most significant for us at this time about this clock cycle is that it is significantly
long to allow us to transfer data between registers via the data bus in one clock cycle. We also assume the
clock pulse is sufficiently long to allow a memory operation to complete.

11
Examples of registers transfers implementing the fetch phase and some instruction for RSCPU:
We now give examples of the register transfers needed to implement the instruction cycle for our CPU. In
doing so note the following:

• If a memory read is indicated (by control signal read) the read operation starts at the end of the data path
cycle using the value in AR. Our discussion of the data path timing cycle showed that it is possible for AR
to attain a new value before the end of the cycle, however, meaning it is possible to change the value of AR
and initiate a read operation with this new value at the beginning of the next cycle.

• Continuing memory reads, we shall assume that memory completes its operation within one cycle. This
means that following the initiation of a memory read, we can assume the data being read is available in the
DR at the end of the current timing cycle, but not at the beginning of this cycle. Consequently we must wait
until the next cycle before it can be used.

12
Summary
 Discussed about Design of a simple hypothetical CPU.

Assessment Questions
Q1. Presents a case study to design a simple hypothetical CPU.

13
THANK YOU

14
 APEX INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 20
Memory System Design: Semiconductor DISCOVER . LEARN . EMPOWER
Memory Technologies 1
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 Classification of Memory

 In computers, memory is the most essential component of the normal functioning of any system. The
computer system categorizes the memory for different purposes and uses. In this slide, we have discussed
the classification of memory in detail. Also, we will discuss types of memory, features of memory, RAM,
ROM, SRAM, DRAM, and its advantages and disadvantages.
What is computer memory?
 Computer memory is any physical device, used to store data, information or instruction temporarily or
permanently.
 It is the collection of storage units that stores binary information in the form of bits. The memory block is
split into a small number of components, called cells.
 Each cell has a unique address to store the data in memory, ranging from zero to memory size minus one.
 For example, if the size of computer memory is 64k words, the memory units have 64 * 1024 = 65536
locations or cells. The address of the memory's cells varies from 0 to 65535.
4
Why do we need a computer memory?
 In the computer system, we need computer memory to store various types of data like text, images, video,
audio, documents, etc. We can retrieve it when the data is required. For example, when we write and
execute any computer program, it is initially stored in primary memory. If the processor does not need
particular items for a longer time, the program or data is automatically saved into the permanent or
secondary memory. Then the data is called from secondary memory to main memory and performs the
execution of codes.
Features of Memory
 Following are the different features of the memory system that includes:
 Location: It represents the internal or external location of the memory in a computer. The internal memory
is inbuilt in computer memory. It is also known as primary memory. the example of primary memory are
registers, cache and main memory. Whereas, external memory is the separate storage device from the
computer, such as disk, tape, USB pen drive.
5
 Capacity: It is the most important feature of computer memory. Storage capacity can vary in external and
internal memory. External devices' storage capacity is measured in terms of bytes, whereas the internal
memory is measured with bytes or words. The storage word length can vary in bits, such as 8, 16 or 32 bits.
 Access Methods: Memory can be accessed through four modes of memory.
• DMA: As the name specifies, Direct Memory Address (DMA) is a method that allows input/output (I/O)
devices to access or retrieve data directly or from the main memory.
• Sequential Access Method: The sequential access method is used in a data storage device to read stored
data sequentially from the computer memory. Whereas, the data received from random access memory
(RAM) can be in any order.
• Random Access Method: It is a method used to randomly access data from memory. This method is the
opposite of SAM. For example, to go from A to Z in random access, we can directly jump to any
specified location. In the Sequential method, we have to follow all intervening from A to Z to reach at the
particular memory location.
• Associative Access Method: It is a special type of memory that optimizes search performance through
6
defined data to directly access the stored information based on a memory address.
 Unit of transfer: As the name suggests, a unit of transfer measures the transfer rate of bits that can be read
or write in or out of the memory devices. The transfer rate of data can be different in external and internal
memory.
• Internal memory: The transfer rate of bits is mostly equal to the word size.
• External memory: The transfer rate of bit or unit is not equal to the word length. It is always greater than
a word or may be referred to as blocks.
 Performance: The performance of memory is majorly divided into three parts.
• Access Time: In random access memory, it represents the total time taken by memory devices to perform
a read or write operation that an address is sent to memory.
• Memory Cycle Time: Total time required to access memory block and additional required time before
starting second access.
• Transfer rate: It describes the transfer rate of data used to transmit memory to or from an external or
internal memory device. Bit transfer can be different for different external and internal devices. 7
 Physical types: It defines the physical type of memory used
in a computer such as magnetic, semiconductor, magneto-
optical and optical.
 Organization: It defines the physical structure of the bits
used in memory.
 Physical characteristics: It specifies the physical behavior
of the memory like volatile, non-volatile or non-erasable
memory. Volatile memory is known as RAM, which
requires power to retain stored information, and if any
power loss has occurred, stored data will be lost. Non-
volatile memory is a permanent storage memory that is used
to obtain any stored information, even when the power is
off. Non-erasable memory is a type of memory that cannot
be erased after the manufactured like ROM because at the
8
time of manufactured ROM are programmed.
 Primary or Main Memory: Primary memory is also known as the computer system's main memory that
communicates directly within the CPU, Auxiliary memory and the Cache memory.
 Main memory is used to kept programs or data when the processor is active to use them. When a program
or data is activated to execute, the processor first loads instructions or programs from secondary memory
into main memory, and then the processor starts execution.
 Accessing or executing of data from primary memory is faster because it has a cache or register memory
that provides faster response, and it is located closer to the CPU.
 The primary memory is volatile, which means the data in memory can be lost if it is not saved when a
power failure occurs. It is costlier than secondary memory, and the main memory capacity is limited as
compared to secondary memory.
 The primary memory is further divided into two parts:
• RAM (Random Access Memory)
• ROM (Read Only Memory) 9
 Random Access Memory (RAM): It is one of the faster types of main memory accessed directly by the
CPU. It is the hardware in a computer device to temporarily store data, programs or program results. It is
used to read/write data in memory until the machine is working. It is volatile, which means if a power
failure occurs or the computer is turned off, the information stored in RAM will be lost. All data stored in
computer memory can be read or accessed randomly at any time.
 There are two types of RAM:
• DRAM (Dynamic Random-Access Memory)
• SRAM (Static Random-Access Memory)

10
 DRAM: DRAM (Dynamic Random-Access Memory) is a type of RAM that is used for the dynamic
storage of data in RAM. In DRAM, each cell carries one-bit information. The cell is made up of two parts: a
capacitor and a transistor. The size of the capacitor and the transistor is so small, requiring millions of them
to store on a single chip. Hence, a DRAM chip can hold more data than an SRAM chip of the same size.
However, the capacitor needs to be continuously refreshed to retain information because DRAM is volatile.
If the power is switched off, the data store in memory is lost.
 Characteristics of DRAM
• It requires continuously refreshed to retain the data.
• It is slower than SRAM
• It holds a large amount of data
• It is the combination of capacitor and transistor
• It is less expensive as compared to SRAM
• Less power consumption
11
 SRAM: SRMA (Static Random-Access Memory) is a type of RAM used to store static data in the memory.
It means to store data in SRAM remains active as long as the computer system has a power supply.
However, data is lost in SRAM when power failures have occurred.
 Characteristics of Static Ram
• It does not require to refresh.
• It is faster than DRAM
• It is expensive.
• High power consumption
• Longer life
• Large size
• Uses as a cache memory
12
 SRAM Vs DRAM:
SRAM DRAM
Advantages of RAM
It is a Static Random-Access Memory. It is a Dynamic Random Access Memory.
 It is a faster type of memory in a computer.
The access time of SRAM is slow. The access time of DRAM is high.
 It requires less power to operate.
It uses flip-flops to store each bit of It uses a capacitor to store each bit of
 Program loads much faster information. information.

 More RAM increases the performance of a

It does not require periodic refreshing to It requires periodically refreshing to preserve
system and can multitask. preserve the information. the information.

 Perform read and write operations. It uses in cache memory. It is used in the main memory.

 The processor can read information faster than The cost of SRAM is expensive. The cost of DRAM is less expensive.

a hard disc, floppy, USB, etc. It has a complex structure. Its structure is simple.

Disadvantages of RAM It requires low power consumption. It requires more power consumption.

 Less RAM reduces the speed and performance of a computer. Due to volatile, it requires electricity to
preserve the data.
 It is expensive than ROM and unreliable as compared to ROM and the Size of RAM is limited. 13
 Read-Only Memory (ROM): ROM is a memory device or storage medium that is used to permanently
store information inside a chip. It is a read-only memory that can only read stored information, data or
programs, but we cannot write or modify anything.
 A ROM contains some important instructions or program data that are required to start or boot a computer.
It is a non-volatile memory; it means that the stored information cannot be lost even when the power is
turned off or the system is shut down.
 Types of ROM: There are five types of Read Only Memory:
• MROM (Masked Read Only Memory): MROM is the
oldest type of read-only memory whose program or
data is pre-configured by the integrated circuit
manufacture at the time of manufacturing. Therefore, a
program or instruction stored within the MROM chip
cannot be changed by the user. 14
• EPROM (Erasable and Programmable Read Only Memory): It is the type of read only memory in which
stored data can be erased and re-programmed only once in the EPROM memory. It is a non-volatile
memory chip that holds data when there is no power supply and can also store data for a minimum of 10
to 20 years. In EPROM, if we want to erase any stored data and re-programmed it, first, we need to pass
the ultraviolet light for 40 minutes to erase the data; after that, the data is re-created in EPROM.
• EEPROM (Electrically Erasable and Programmable Read Only Memory): The EEROM is an electrically
erasable and programmable read only memory used to erase stored data using a high voltage electrical
charge and re-programmed it. It is also a non-volatile memory whose data cannot be erased or lost; even
the power is turned off. In EEPROM, the stored data can be erased and reprogrammed up to 10 thousand
times, and the data erase one byte at a time.
• Flash ROM: Flash memory is a non-volatile storage memory chip that can be written or programmed in
small units called Block or Sector. Flash Memory is an EEPROM form of computer memory, and the
contents or data cannot be lost when the power source is turned off. It is also used to transfer data
between the computer and digital devices.
15
 RAM Vs ROM:
RAM ROM
Advantages of ROM
It is a Random-Access Memory. It is a Read Only Memory.
 It is a non-volatile memory in which stored Read and write operations can be Only Read operation can be
performed. performed.
information can be lost even power is turned off. Data can be lost in volatile memory Data cannot be lost in non-
when the power supply is turned volatile memory when the power
 It is static, so it does not require refreshing the off. supply is turned off.
It is a faster and expensive memory. It is a slower and less expensive
content every time. Data can be stored permanently. memory.
 It is easy to test and store large data as compared to RAM. Storage data requires to be Storage data does not need to be
refreshed in RAM. refreshed in ROM.
 These cannot be changed accidently The size of the chip is bigger than The size of the chip is smaller
the ROM chip to store the data. than the RAM chip to store the
 It is cheaper, simple and reliable than RAM. same amount of data.
Types of RAM: DRAM and SRAM Types of ROM: MROM, PROM,
 It helps to start the computer and loads the OS. EPROM, EEPROM

Disadvantages of ROM
 Store data cannot be updated or modify except to read the existing data. It is a slower memory than RAM to
access the stored data.
 It takes around 40 minutes to destroy the existing data using the high charge of ultraviolet light. 16
 Secondary Memory: Secondary memory is a permanent storage space to hold a large amount of data.
Secondary memory is also known as external memory that representing the various storage media (hard
drives, USB, CDs, flash drives and DVDs) on which the computer data and program can be saved on a long
term basis. However, it is cheaper and slower than the main memory. Unlike primary memory, secondary
memory cannot be accessed directly by the CPU. Instead of that, secondary memory data is first loaded into
the RAM (Random Access Memory) and then sent to the processor to read and update the data. Secondary
memory devices also include magnetic disks like hard disk and floppy disks, an optical disk such as CDs
and CDROMs, and magnetic tapes.
• Features of Secondary Memory
• Its speed is slower than the primary/ main memory.
• Store data cannot be lost due to non-volatile nature.
• It can store large collections of different types, such as audio, video, pictures, text, software, etc.
• All the stored data in a secondary memory cannot be lost because it is a permanent storage area; even the
power is turned off.
• It has various optical and magnetic memories to store data.
17
Types of Secondary Memory
 The following are the types of secondary memory devices:
 Hard Disk: A hard disk is a computer's permanent storage device. It is a non-volatile disk that permanently
stores data, programs, and files, and cannot lose store data when the computer's power source is switched
off. Typically, it is located internally on computer's motherboard that stores and retrieves data using one or
more rigid fast rotating disk platters inside an air-sealed casing. It is a large storage device, found on every
computer or laptop for permanently storing installed software, music, text documentation, videos, operating
system, and data until the user did not delete.

18
 Floppy Disk: A floppy disk is a secondary storage system that consisting of thin, flexible magnetic coating
disks for holding electronic data such as computer files. It is also known as Floppy Diskette that comes in
three sizes like 8 inches, 5.5 inches and 3.5 inches. The stored data of a floppy disk can be accessed through
the floppy disk drive. Furthermore, it is the only way through a new program installed on a computer or
backup of the information. However, it is the oldest type of portable storage device, which can store data up
to 1.44 MB. Since most programs were larger, that required multiple floppy diskettes to store large amounts
of data. Therefore, it is not used due to very low memory storage.

19
 CD (Compact Disc): A CD is an optical disk storage device, stands for Compact Disc. It is a storage
device used to store various data types like audio, videos, files, OS, Back-Up file, and any other
information useful to a computer. The CD has a width of 1.2 mm and 12 cm in height, which can store
approximately 783 MB of data size. It uses laser light to read and write data from the CDs.
 Types of CDs
• CD-ROM (Compact Disc Read Only Memory): It is mainly used for bulk size mass like audio CDs,
software and computer games at the time of manufacture. Users can only read data, text, music, videos
from the disc, but they cannot modify or burnt it.
• CD-R (Compact Disc Recordable): The type of Compact Disc used to write once by the user; after that,
it cannot be modified or erased.
• CD-RW (Compact Disc Rewritable): It is a rewritable CD disc, often used to write or delete the stored
data.

20
 DVD Drive/Disc: DVD is an optical disc storage device, stands for Digital Video
Display or Digital Versatile Disc. It has the same size as a CD but can store a larger
amount of data than a compact disc. It was developed in 1995 by Sony, Panasonic,
Toshiba and Philips four electronics companies. DVD drives are divided into three
types, such as DVD ROM (Read Only Memory), DVD R (Recordable) and DVD
RW (Rewritable or Erasable). It can store multiple data formats like audio, videos,
images, software, operating system, etc. The storing capacity of data in DVD is 4.7
GB to 17 GB.

 Pen Drive: A pen drive is a portable device used to permanently store data and is
also known as a USB flash drive. It is commonly used to store and transfer the data
connected to a computer using a USB port. It does not have any moveable part to
store the data; it uses an integrated circuit chip that stores the data. It allows the
users to store and transfer data like audio, videos, images, etc. from one computer
to any USB pen drive. The storing capacity of pen drives from 64 MB to 128 GB or
more.
21
 Blu Ray Disc (BD): Blu Ray is an Optical disc storage device used to store a large amount of data or high
definition of video recording and playing other media files. It uses laser technology to read the stored data
of the Blu-ray Disk. It can store more data at a greater density as compared to CD/ DVD. For example,
compact discs allow us to store 700 MB of data, and in DVDs, it provides up to 8 GB of storage capacity,
while Blu-ray Discs provide 28 GB of space to store data.
 Cache Memory: It is a small-sized chip-based computer memory that lies between the CPU and the main
memory. It is a faster, high performance and temporary memory to enhance the performance of the CPU. It
stores all the data and instructions that are often used by computer CPUs. It also reduces the access time of
data from the main memory. It is faster than the main memory, and sometimes, it is also called CPU
memory because it is very close to the CPU chip. The following are the levels of cache memory.
 L1 Cache: Its speed is very high, and the size of the L1 cache varies from
8 KB to 128 KB.
 L2 Cache: It is built into a separate chip in a motherboard, not built into
the CPU like the L1 level. The size of the L2 may be 128 KB to 1 MB.
 L3 Cache: Its speed is very slow, and the maximum size up to 8 MB.
22
Advantages of Cache Memory
 Cache memory is the faster memory as compared to the main memory.
 It stores all data and instructions that are repeatedly used by the CPU for improving the performance of a
computer.
 The access time of data is less than the main memory.
Disadvantage of Cache Memory
 It is very costly as compared to the Main memory and the Secondary memory.
 It has limited storage capacity.

 Register Memory: The register memory is a temporary storage area for storing and transferring the data
and the instructions to a computer. It is the smallest and fastest memory of a computer. It is a part of
computer memory located in the CPU as the form of registers. The register memory is 16, 32 and 64 bits in
size. It temporarily stores data instructions and the address of the memory that is repeatedly used to provide
faster response to the CPU.
23
 Primary Vs. Secondary Memory
Primary Memory Secondary Memory
It is also known as temporary memory. It is also known as a permanent memory.

Data can be access directly by the processor or CPU. Data cannot be accessed directly by the I/O processor or
CPU.
Stored data can be a volatile or non-volatile memory. The nature of secondary memory is always non-volatile.

It is more costly than secondary memory. It is less costly than primary memory.

It is a faster memory. It is a slower memory.

It has limited storage capacity. It has a large storage capacity.

It required the power to retain the data in primary memory. It does not require power to retain the data in secondary
memory.
Examples of primary memory are RAM, ROM, Registers, Examples of secondary memory are CD, DVD, HDD,
EPROM, PROM and cache memory. magnetic tapes, flash disks, pen drive, etc.

24
Summary
 Discussed about Classification of Memory.
 Why do we need a computer memory?
 Discussed about the Features of Memory.
 Learn about Primary or Main Memory, Random Access Memory (RAM), Read-Only Memory (ROM),
Secondary Memory, and Register Memory

Assessment Questions
Q1. What is computer memory?
Q2. Discussed the Classification of Memory.
25
THANK YOU

26
 APEX INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 21
Memory System Design: Memory Organization DISCOVER . LEARN . EMPOWER
1
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 Classification of Memory

 In computers, memory is the most essential component of the normal functioning of any system. The
computer system categorizes the memory for different purposes and uses. In this slide, we have discussed
the classification of memory in detail. Also, we will discuss types of memory, features of memory, RAM,
ROM, SRAM, DRAM, and its advantages and disadvantages.
What is computer memory?
 Computer memory is any physical device, used to store data, information or instruction temporarily or
permanently.
 It is the collection of storage units that stores binary information in the form of bits. The memory block is
split into a small number of components, called cells.
 Each cell has a unique address to store the data in memory, ranging from zero to memory size minus one.
 For example, if the size of computer memory is 64k words, the memory units have 64 * 1024 = 65536
locations or cells. The address of the memory's cells varies from 0 to 65535.
4
 Memory Hierarchy
 Memory is used for storing programs and data that are required to perform a
specific task.
 For CPU to operate at its maximum speed, it required an uninterrupted and high speed
access to these memories that contain programs and data. Some of the criteria need to
be taken into consideration while deciding which memory is to be used:
• Cost
• Speed
• Memory access time
• Data transfer rate
• Reliability
How Memories attached to CPU

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 A computer system contains various types of memories like auxiliary memory,
cache memory, and main memory.
• Auxiliary Memory
The auxiliary memory is at the bottom and is not connected with the CPU directly.
However, being slow, it is present in large volume in the system due to its low
pricing. This memory is basically used for storing the programs that are not needed
in the main memory. This helps in freeing the main memory which can be utilized
by other programs that needs main memory. The main function of this memory is
to provide parallel searching that can be used for performing a search on an entire
word.
• Main Memory
The main memory is at the second level of the hierarchy. Due to its direct
connection with the CPU, it is also known as central memory. The main memory
holds the data and the programs that are needed by the CPU. The main memory
mainly consists of RAM, which is available in static and dynamic mode.
• Cache Memory
Cache memory is at the top level of the memory hierarchy. This is a high speed
memory used to increase the speed of processing by making current programs
and data available to the CPU at a rapid rate. Cache memory is usually placed
between the CPU and the main memory.
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 Main Memory

• Central storage unit in a computer system

• Large memory
• Made up of Integrated chips
• Types:
RAM (Random access memory)
ROM (Read only memory)
 RAM (Random Access Memory)

Random access memory (RAM) is the best

known form of computer memory. RAM is
considered "random access" because you can
access any memory cell directly if you know
the row and column that intersect at that cell.
Types of RAM:-
• Static RAM (SRAM)
• Dynamic RAM (DRAM)
• Static RAM (SRAM)
– a bit of data is stored using the state of a flip-flop.
– Retains value indefinitely, as long as it is kept powered.
– Mostly uses to create cache memory of CPU.
– Faster and more expensive than DRAM.

• Dynamic RAM (DRAM)

– Each cell stores bit with a capacitor and transistor.
– Large storage capacity
– Needs to be refreshed frequently.
– Used to create main memory.
– Slower and cheaper than SRAM.
 ROM
ROM is used for storing programs that are Permanently resident in
the computer and for tables of constants that do not change in
value once the production of the computer is completed

The ROM portion of main memory is needed for storing an initial

program called bootstrap loader, witch is to start the computer
software operating when power is turned on.

There are five basic ROM types:

• ROM - Read Only Memory
• PROM - Programmable Read Only Memory
• EPROM - Erasable Programmable Read Only Memory
• EEPROM - Electrically Erasable Programmable Read Only Memory
• Flash EEPROM memory
 RAM and ROM Chips

• A RAM chip is better suited for

communication with the CPU if it has one or
more control inputs that select the chip when
needed

• The Block diagram of a RAM chip is shown

next slide, the capacity of the memory is 128
words of 8 bits (one byte) per word
RAM

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ROM

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 Memory Address Map

• Memory Address Map is a pictorial representation of

assigned address space for each chip in the system

• To demonstrate an example, assume that a computer

system needs 512 bytes of RAM and 512 bytes of
ROM

• The RAM have 128 byte and need seven address

lines, where the ROM have 512 bytes and need 9
address lines
• The hexadecimal address assigns a range of
hexadecimal equivalent address for each chip

• Line 8 and 9 represent four distinct binary

combination to specify which RAM we chose

• When line 10 is 0, CPU selects a RAM. And

when it’s 1, it selects the ROM
Memory connection to the CPU
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 Cache memory

• If the active portions of the program and data

are placed in a fast small memory, the average
memory access time can be reduced
• Thus reducing the total execution time of the
program
• Such a fast small memory is referred to as
cache memory
• The cache is the fastest component in the
memory hierarchy and approaches the speed
of CPU component
• When CPU needs to access memory, the cache
is examined
• If the word is found in the cache, it is read
from the fast memory
• If the word addressed by the CPU is not found
in the cache, the main memory is accessed to
read the word
• When the CPU refers to memory and finds the
word in cache, it is said to produce a hit

• Otherwise, it is a miss

• The performance of cache memory is

frequently measured in terms of a quantity
called hit ratio
Hit ratio = hit / (hit+miss)
• The basic characteristic of cache memory is its fast
access time
• Therefore, very little or no time must be wasted
when searching the words in the cache
• The transformation of data from main memory to
cache memory is referred to as a mapping process,
there are three types of mapping:
– Associative mapping
– Direct mapping
– Set-associative mapping
• To help understand the mapping procedure,
we have the following example:

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 Associative mapping
• The fastest and most flexible cache
organization uses an associative memory
• The associative memory stores both the
address and data of the memory word
• This permits any location in cache to store ant
word from main memory
• The address value of 15 bits is shown as a five-
digit octal number and its corresponding 12-
bit word is shown as a four-digit octal number
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• A CPU address of 15 bits is places in the
argument register and the associative memory
us searched for a matching address
• If the address is found, the corresponding 12-
bits data is read and sent to the CPU
• If not, the main memory is accessed for the
word
• If the cache is full, an address-data pair must
be displaced to make room for a pair that is
needed and not presently in the cache
 Direct Mapping
• Associative memory is expensive compared to
RAM
• In general case, there are 2^k words in cache
memory and 2^n words in main memory (in
our case, k=9, n=15)
• The n bit memory address is divided into two
fields: k-bits for the index and n-k bits for the
tag field
Addressing relationships between main and cache memories

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Source: http://cms.gcg11.ac.in/attachments/article/93/Memory%20Organization.pdf
 Set-Associative Mapping

• The disadvantage of direct mapping is that

two words with the same index in their
address but with different tag values cannot
reside in cache memory at the same time

• Set-Associative Mapping is an improvement

over the direct-mapping in that each word of
cache can store two or more word of memory
under the same index address
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• Each index address refers to two data words
and their associated tags
• Each tag requires six bits and each data word
has 12 bits, so the word length is 2*(6+12) =
36 bits
Key Points
• Memory organization
• Memory Hierarchy
• RAM
• ROM
• Cache memory
• Types of mapping

34
Summary
 Discussed about Memory organization.
 Discussed about Memory Hierarchy.
 Discussed about RAM and ROM.
 Discussed about the Cache memory

Assessment Questions
Q1. What is computer memory?
Q2. Discussed the Classification of Memory.

35
THANK YOU

36
 APEX INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 23 & 24
Memory Organization: Memory Interleaving & DISCOVER . LEARN . EMPOWER
1
Concept of Hierarchical Memory Organization
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 Memory Interleaving

 Interleaved memory is designed to compensate for the relatively slow speed of dynamic random-access
memory (DRAM) or core memory by spreading memory addresses evenly across memory banks. In this
way, contiguous memory reads and writes use each memory bank, resulting in higher memory throughput
due to reduced waiting for memory banks to become ready for the operations. It is different from multi-
channel memory architectures, primarily as interleaved memory does not add more channels between the
main memory and the memory controller.
 However, channel interleaving is also possible,
for example, in Freescale i.MX6 processors,
which allow interleaving to be done between two
channels. With interleaved memory, memory addresses
are allocated to each memory bank.

4
Example of Interleaved Memory
 It is an abstraction technique that divides memory into many modules such that successive words in the
address space are placed in different modules.
 Suppose we have 4 memory banks, each containing 256 bytes, and then the Block Oriented scheme (no
interleaving) will assign virtual addresses 0 to 255 to the first bank and 256 to 511 to the second bank. But
in Interleaved memory, virtual address 0 will be with the first bank, 1 with the second memory bank, 2 with
the third bank and 3 with the fourth, and then 4 with the first memory bank again.
 Hence, the CPU can access alternate sections immediately without waiting for memory to be cached. There
are multiple memory banks that take turns for the supply of data.
 In the above example of 4 memory banks, data with virtual addresses 0, 1, 2 and 3 can be accessed
simultaneously as they reside in separate memory banks. Hence we do not have to wait to complete a data
fetch to begin the next operation.
5
 An interleaved memory with n banks is said to be n-way interleaved. There are still two banks of DRAM in
an interleaved memory system, but logically, the system seems one bank of memory that is twice as large.
 In the interleaved bank representation below with 2 memory banks, the first long word of bank 0 is flowed
by that of bank 1, followed by the second long word of bank 0, followed by the second long word of bank 1
and so on.
 The following image shows the organization of two physical banks
of n long words. All even long words of the logical bank are located
in physical bank 0, and all odd long words are located in physical
bank 1.

6
Why do we use Memory Interleaving?
 When the processor requests data from the main memory, a block (chunk) of data is transferred to the cache
and then to processor. So whenever a cache miss occurs, the data is to be fetched from the main memory.
But main memory is relatively slower than the cache. So to improve the access time of the main memory,
interleaving is used.
 For example, we can access all four modules at the same time, thus achieving parallelism. The data can be
acquired from the module using the higher bits. This method uses memory effectively.
Types of Interleaved Memory
 In an operating system, there are two types of interleaved memory, such as:
 1. High order interleaving: In high order memory interleaving, the most significant bits of the memory
address decides memory banks where a particular location resides. But, in low order interleaving the least
significant bits of the memory address decides the memory banks.
7
 The least significant bits are sent as addresses to each chip. One problem is that consecutive addresses tend
to be in the same chip. The maximum rate of data transfer is limited by the memory cycle time. It is also
known as Memory Banking.

8
9
2. Low order interleaving: The least significant bits select the memory bank (module) in low-
order interleaving. In this, consecutive memory addresses are in different memory modules,
allowing memory access faster than the cycle time.

10
11
Benefits of Interleaved Memory

An instruction pipeline may require instruction and operands both at the same time from
main memory, which is not possible in the traditional method of memory access.

Similarly, an arithmetic pipeline requires two operands to be fetched simultaneously from

the main memory.

12
 So, to overcome this problem, memory interleaving comes to resolve this.
• It allows simultaneous access to different modules of memory. The modular memory technique allows
the CPU to initiate memory access with one module while others are busy with the CPU in reading or
write operations. So, we can say interleave memory honors every memory request independent of the
state of the other modules.
• So, for this obvious reason, interleave memory makes a system more responsive and fast than non-
interleaving. Additionally, with simultaneous memory access, the CPU processing time also decreases
and increasing throughput. Interleave memory is useful in the system with pipelining and vector
processing.
• In an interleaved memory, consecutive memory addresses are spread across different memory modules.
Say, in a byte-addressable 4 way interleave memory, if byte 0 is in the first module, then byte 1 will be in
the 2nd module, byte 2 will be in the 3rd module, byte 3 will be in the 4th module, and again byte 4 will
fall in the first module, and this goes on.
13
 • An n-way interleaved memory where main memory is divided into n-banks and system can access n
operands/instruction simultaneously from n different memory banks.
• This kind of memory access can reduce the memory access time by a factor close to the number of
memory banks. In this memory interleaving memory location, i can be found in bank i mod n.
Interleaving DRAM
 Main memory is usually composed of a collection of DRAM memory chips, where many chips can be
grouped together to form a memory bank. With a memory controller that supports interleaving, it is then
possible to layout these memory banks so that the memory banks will be interleaved.
 Data in DRAM is stored in units of pages. Each DRAM bank has a row buffer that serves as a cache for
accessing any page in the bank. Before a page in the DRAM bank is read, it is first loaded into the row-
buffer.
 If the page is immediately read from the row-buffer, it has the shortest memory access latency in one
memory cycle. Suppose it is a row buffer miss, which is also called a row-buffer conflict. 14
 It is slower because the new page has to be loaded into the row-buffer before it is read.
 Row-buffer misses happening as access requests on different memory pages in the same bank are serviced.
 A row-buffer conflict incurs a substantial delay for memory access.
 In contrast, memory accesses to different banks can proceed in parallel with high throughput.
 In traditional layouts, memory banks can be allocated a contiguous block of memory addresses, which is
very simple for the memory controller and gives an equal performance in completely random access
scenarios compared to performance levels achieved through interleaving.
 However, memory reads are rarely random due to the locality of reference, and optimizing for close
together access gives far better performance in interleaved layouts.
 The way memory is addressed does not affect the access time for memory locations that are already cached,
impacting only on memory locations that need to be retrieved from DRAM.

15
 Concept of Hierarchical Memory Organization

 In our computer system, a processor and many memory devices have been used. However, the main
problem is these devices are expensive. So the memory organization of the system is done with the help of
the memory hierarchy.
 It has various levels of memory with different access times and performance rates. But all these can give us
an exact purpose, such that the access time can be reduced. Therefore the memory hierarchy was developed
based on the program.
 We will discuss the Memory organization or Hierarchy of computer architecture in detail.
What is Memory Hierarchy?

16
 The memory hierarchy is the arrangement of various types of storage on a computing system based on
access speed. It organizes computer storage according to response time.
 Since response time, complexity, and capacity are all connected, the levels can also be distinguished by
their performance and controlling technologies.
 As shown in the above picture, the computer memory has a pyramid-like structure. It is used to describe the
different levels of memory.
 It separates the computer storage based on hierarchy.
 As you can see, capacity is increasing with time. This Memory Hierarchy Design is divided into 2 types:
•Primary or internal memory: It consists of CPU registers, Cache Memory, Main Memory, and these are
directly accessible by the processor.
•Secondary or external memory: It consists of a Magnetic Disk, Optical Disk, Magnetic Tape, which are
accessible by processor via I/O Module.
17
 Let's focus on each memory level in detail to better understand the topic.
Memory Hierarchy Design
 The Memory hierarchy is further classified into two types:
 Internal memory: It is also called primary memory. Internal memory is a part of your computer that, when
running, can store small amounts of data that need to be accessed quickly. This type of memory is directly
reachable by the process through the I/O module. It consists of RAM, ROM, and cache memory.
• RAM: It is a volatile memory that is used to store whatever is in use by the computer, and it acts as a
middle man between the CPU and the storage device, which helps speed up the computer. It has many
forms, but the most common type is DDR3.
• ROM: ROM, unlike other internal memory, is non-volatile. ROM stands for read-only memory, meaning
the user cannot write data to the ROM without special access. It was designed so that the computer could
access the bios without other parts of hardware.
• Cache: It is a really small, super-fast memory found in various computer components. The CPU cache
stores small bits of frequently accessed data from the RAM so that the processor doesn't have to wait for
the RAM to respond every time it wants the same piece of information.
18
 External memory: It is also known as secondary memory. Since it has a huge capacity, it stores massive
data. Presently, it can measure the data in hundreds of megabytes or even in gigabytes. The critical property
of external memory is that stored information will not be lost whenever the computer switches off. It
consists of magnetic tape, a magnetic disk, and an optical disk.
• Magnetic tape: It is a medium for magnetic storage, a thin, magnetizable coating on a long, narrow strip
of plastic film. It is used for many purposes like hanging signs and displays for business recording audio in
a recording tape to store the data on a hard disk. Alternatively, we can use it for keeping things in a house
or a garage.
• Magnetic disk: Magnetic disks are flat circular plates of metal or plastic coated on both sides with iron
oxide. Input signals, which may be audio, video, or data, are recorded on the surface of a disk as magnetic
patterns or spots in spiral tracks by a recording head while a drive unit rotates the disk. It is relatively cheap
per storage unit, with Fast access and retrieval times compared to other storage devices.
• Optical disk: It is an electronic data storage medium that can be written to and read using a low-powered
laser beam. Optical disks are often stored in exceptional cases, sometimes called jewel cases, and are most
commonly used for digital preservation, music, video, or data and programs for personal computers.
Optical media provides many advantages for storing data over conventional magnetic disks, such as mass
19
storage capacity, mountable/unmountable storage units, and low cost per bit of storage.
Characteristics of Memory Hierarchy

 The memory characteristics mainly include:

1. Access Time: The access time in the memory hierarchy of a computer system is the interval of the time
among the data availability and request to read or write.
2. Capacity: It is the amount of information that can be stored. The capacity increases as we move from
top to bottom in the hierarchy.
3. Performance: In old times, designing a computer system was done without memory hierarchy. The gap
of speed between the main memory and the CPU registers is enhanced because of the huge inconsistency in
access time, which will cause the lower performance of the system. So, the enhancement in the memory
was mandatory. This enhancement was designed in the memory hierarchy model due to the system's
performance increase.
4. Cost per bit: As we will move from bottom to top in the system's hierarchy, the cost per bit increases,
i.e., Internal Memory is costlier than External Memory.

20
Advantages
 Removes external destruction.
 Swapping will be more proficient.
 Data can be spread all over.
 Memory distribution is simple and economical

21
Summary
 Why do we need a computer memory?
 Discussed about the Memory interleaving.
 Discussed about memory hierarchy?

Assessment Questions
Q1. Why is memory hierarchy?
Q2. What are the types of memory hierarchy?

22
THANK YOU

23
 APEX INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 25 & 26
Memory Organization: Cache Memory & DISCOVER . LEARN . EMPOWER
Cache Size Vs. Block Size 1
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 Cache Memory

 The data or contents of the main memory that are used frequently by CPU are stored in the cache memory
so that the processor can easily access that data in a shorter time. Whenever the CPU needs to access
memory, it first checks the cache memory. If the data is not found in cache memory, then the CPU moves
into the main memory. Cache memory is placed between the CPU and the main memory. The block
diagram for a cache memory can be represented as:

4
 The cache is the fastest component in the memory hierarchy and approaches the speed of CPU components.
Cache memory is organized as distinct set of blocks where each set contains a small fixed number of
blocks.

5
 As shown in the above sets are represented by the rows. The example contains N sets and each set contains
four blocks. Whenever an access is made to cache, the cache controller does not search the entire cache in
order to look for a match. Rather, the controller maps the address to a particular set of the cache and
therefore searches only the set for a match.
 If a required block is not found in that set, the block is not present in the cache and cache controller does not
search it further. This kind of cache organization is called set associative because the cache is divided into
distinct sets of blocks. As each set contains four blocks the cache is said to be four way set associative.
 The basic operation of a cache memory is as follows:
• When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it is
read from the fast memory.
• If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the
word.
6
 The basic operation of a cache memory is as follows:
• A block of words one just accessed is then transferred from main memory to cache memory. The block
size may vary from one word (the one just accessed) to about 16 words adjacent to the one just accessed.
• The performance of the cache memory is frequently measured in terms of a quantity called hit ratio.
• When the CPU refers to memory and finds the word in cache, it is said to produce a hit.
• If the word is not found in the cache, it is in main memory and it counts as a miss.
• The ratio of the number of hits divided by the total CPU references to memory (hits plus misses) is the hit
ratio.
Levels of memory:
 Level 1 or Registers : It is a type of memory in which data is stored and accepted that are immediately
stored in CPU. Most commonly used register is accumulator, Program counter, address register etc.
7
 Level 2 or cache memory: It is the fastest memory which has faster access time where data is temporarily
stored for faster access.
 Level 3 or main memory: It is memory on which computer works currently. It is small in size and once
power is off data no longer stays in this memory.
 Level 4 or secondary memory: It is external memory which is not as fast as main memory but data stays
permanently in this memory.
Cache Organization: Block Size, Writes
 Remember that the memory in a modern system has many levels of cache. Typically, the more data that the
memory can store, the slower it is. It turns out that a third of the core of a processor is a cache. For each
cache line, you have:
• 1-bit valid bit
• 4-bit tag bits
• 8-bit data bits
8
 This has 5 bits of overhead for every 8 bits of data! This is a problem. How do we reduce this? What if
instead of storing one byte per tag, we stored multiple bytes per tag?
Advantages:
• Increase the data
• Reduce the bits needed per tag
• Can get a higher hit rate by bringing sequential values to higher cache level (loops!)
 Let's say you have 16 memory addresses, and originally a block size of 1. If you double the block size, the
tag space is halved and hence you can actually save a bit off of the tag field!

9
 Block Offset Size vs. Tag Size

 You have to store the tag and the block offset together. Let's say that you have 32 bits to do so. Let's look at
a couple scenarios to determine how big the tag needs to be, and how big the block offset needs to be.
 If your blocks have a size of one byte, then you do not need to store a block offset whatsoever. The tag size
is 32 bits, and block offset size is 0 bits.
 If your blocks have a size of two bytes, then you have to store a single bit for the block offset, and you have
to use the remaining bits for the tag. The tag size is then 31 bits, and block offset size is 1 bit.
 In general, the block offset size is always going to be log2(b), where b is your block size in bytes. The tag
size will always be the number of bits for the address (tag + offset), minus the block offset size.
 Where does the best equilibrium lie? How big should the block size be to maximize locality?
Deciding on Block Size
 Let's say that you have a super huge block size. If the block size is on the scale of your cache, then you only
have one cache line. This is really inefficient. On the other hand, if your block size is one byte, you have to
do a lot of repeated loads. How do we decide the best block size? 10
 It turns out, computer engineers just take a bunch of applications that they believe are representative of
what their processor will run in real life, and they simulate the performance of different cache sizes.
 Most systems use a block size between 32 bytes and 128 bytes. These longer sizes reduce the overhead by:
• Reducing the number of CAM entries
• Reducing the size of each CAM entry
Keeping Track of LRU
 When you load something from the memory into the cache, you have to replace the least recently used
block. To keep track of this, hardware keeps a list. To store this ordering, you need some bits to store the
ordering of the cache lines in the LRU list.
Bits needed
 Since you need to store a number for each cache line entry, this amounts to: log2(l), Where l is the number
of cache lines you have.
11
Summary
 Discussed about the Cache memory.
 Discussed about the Cache size vs. block size.

Assessment Questions
Q1. What are the differences between Cache size &. block size?
Q2. What are the types of Cache memory and usages?

12
THANK YOU

13
 APEX INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 27 & 28
Memory Organization: Mapping Functions DISCOVER . LEARN . EMPOWER
1
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 Mapping Functions

 There are three different types of mapping used for the purpose of cache memory which are as follows:
• Direct mapping,
• Associative mapping
• Set-Associative mapping

 Direct Mapping: In direct mapping, the cache consists of normal high-speed random-access memory. Each
location in the cache holds the data, at a specific address in the cache. This address is given by the lower
significant bits of the main memory address. This enables the block to be selected directly from the lower
significant bit of the memory address. The remaining higher significant bits of the address are stored in the
cache with the data to complete the identification of the cached data. 4
 As shown in the above figure, the address from processor is divided into two field a tag and an index. 5
 The tag consists of the higher significant bits of the address and these bits are stored with the data in cache.
The index consists of the lower significant b of the address.
 Whenever the memory is referenced, the following sequence of events occurs
• The index is first used to access a word in the cache.
• The tag stored in the accessed word is read.
• This tag is then compared with the tag in the address.
• If two tags are same this indicates cache hit and required data is read from the cache word.
• If the two tags are not same, this indicates a cache miss. Then the reference is made to the main memory
to find it.
 For a memory read operation, the word is then transferred into the cache. It is possible to pass the
information to the cache and the process simultaneously.
6
 In direct mapped cache, there can also be a line consisting of more than one word as shown in the following
figure

7
 In such a case, the main memory address consists of a tag, an index and a word within a line. All the words
within a line in the cache have the same stored tag
 The index part in the address is used to access the cache and the stored tag is compared with required tag
address.
 For a read operation, if the tags are same, the word within the block is selected for transfer to the processor.
If tags are not same, the block containing the required word is first transferred to the cache.
 In direct mapping, the corresponding blocks with the same index in the main memory will map into the
same block in the cache, and hence only blocks with different indices can be in the cache at the same time.
 It is important that all words in the cache must have different indices.
 The tags may be the same or different.
 Set Associative Mapping: In set associative mapping a cache is divided into a set of blocks. The number of
blocks in a set is known as associativity or set size. Each block in each set has a stored tag. This tag together
with index completely identify the block. 8
 Thus, set associative mapping allows a limited number of blocks, with the same index and different tags. An
example of four way set associative cache having four blocks in each set is shown in the following figure

9
 In this type of cache, the following steps are used to access the data from a cache:
1.The index of the address from the processor is used to access the set.
2.Then the comparators are used to compare all tags of the selected set with the incoming tag.
3.If a match is found, the corresponding location is accessed.
4.If no match is found, an access is made to the main memory.
 The tag address bits are always chosen to be the most significant bits of the full address, the block address
bits are the next significant bits and the word/byte address bits are the least significant bits.
 The number of comparators required in the set associative cache is given by the number of blocks in a set.
 The set can be selected quickly and all the blocks of the set can be read out simultaneously with the tags
before waiting for the tag comparisons to be made.
 After a tag has been identified, the corresponding block can be selected.
10
 Fully associative mapping: In fully associative type of cache memory, each location in cache stores both
memory address as well as data.

11
 Whenever a data is requested, the incoming memory address a simultaneously compared with all stored
addresses using the internal logic the associative memory. If a match is found, the corresponding is read out.
Otherwise, the main memory is accessed if address is not found in cache.
 This method is known as fully associative mapping approach because cached data is related to the main
memory by storing both memory address and data in the cache. In all organizations, data can be more than
one word as shown in the following figure.

12
 A line constitutes four words, each word being 4 bytes. In such case, the least significant part of the address
selects the particular byte, the next part selects the word, and the remaining bits form the address. These
address bits are compared to the address in the cache.
 The whole line can be transferred to and from the cache in one transaction if there are sufficient data paths
between the main memory and the cache. With only one data word path, the words of the line have to be
transferred in separate transactions.
 The main advantage of fully associative mapped cache is that it provides greatest flexibility of holding
combinations of blocks in the cache and conflict for a given cache.
It suffers from certain disadvantages:
1. It is expensive method because of the high cost of associative memory.
2. It requires a replacement algorithm in order to select a block to be removed whenever cache miss occurs.
3. Such an algorithm must be implemented in hardware to maintain a high speed of operation.
13
4. The fully associative mechanism is usually employed by microprocessors with small internal cache.
Summary
 Discussed about the Cache memory mapping.

Assessment Questions
Q1. What are the types of Cache memory mapping ?

14
THANK YOU

15
 APEX INSTITUTE OF TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Computer Organization & Architecture (21CSH-281)

Lecture – 29 & 30
Memory Organization: Replacement DISCOVER . LEARN . EMPOWER
Algorithms & Write Policies 1
Computer Organization & Architecture: Course Objectives
COURSE OBJECTIVES
The course aims to:
1) The purpose of the course is to introduce principles of computer organization and the basic
architectural concepts.
2) It begins with basic organization, design, and programming of a simple digital computer and
introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,
pipelining and vector processing, memory organization and I/O systems, and
multiprocessors.
4) To familiarize Students with the detailed Architectures of a Central Processing Unit.
5) Learn the different types of serial communication techniques.
2
 COURSE OUTCOMES
On completion of this course, the students shall be able to:-
Identify and interpret the basics of instruction sets and their impact on the design, organization,
CO1 and functionality of various functional units of a computer comparable to the CPU, memory
organization, I/O organization, and parallel processors.
Analysis of the design of arithmetic & logic unit and understanding of the fixed point and
CO2
floating-point arithmetic operations.
Relate cost performance and design trade-offs in designing and constructing a computer
CO3
processor which includes memory.
Understanding the different ways of communicating with I/O devices and standard I/O
CO4
interfaces.

CO5 Implementation of control unit techniques and the concept of Pipelining. 3

 Cache Replacement Algorithms

 Cache replacement algorithms specifies different ways to evict an item from the cache with it is full. There
are bunch of algorithms available used in different scenarios. The goal is to understand different cache
replacement policies by implementing simpler version of these algorithms.
 Optimal Replacement: The best algorithm is called Bélády’s algorithm because it’ll always discard an
item from the cache if it is no longer needed in future. Of course this is theoretical and can’t be
implemented in real-life since it is generally impossible to predict how far in the future information will be
needed.
 FIFO/LIFO: In FIFO the item that enter the cache first is evicted first without any regard of how often or
how many times it was accessed before. LIFO behaves in exact opposite way - evicts the most recent item
from the cache.
 Least Recently Used (LRU): Here we replace the item that has been unused for the longest time.
Implementation is almost same as FIFO cache - used a map and doubly linked list. Only difference is that
any time there is a cache hit, we move it to the front of the queue. Items at the front are most recently used
4
items and items at the tail are the least recently used items.
 Least Frequently Used (LFU): In LFU, we count how many times an item was accessed and evict the item
that has least access count. I used a map and a minimum priority queue to implement it. Priority queue sorts
the items in a binary tree based on their hit counts. Item at the root of the heap has the least hit count.
Instead of removing the root, we update it’s values and reset hit count and Fix the tree. calling heap.Fix() is
equivalent to, but less expensive than, calling heap.Remove() followed by a heap.Push()of the new value.
 LRU and LFU combined: Finally let’s combine LFU and LRU together so that when multiple items in the
cache have the same hit counts, we’ll only evict the oldest one. We can modify the LFU implementation a
bit and add a global sequential id to each item. When accessing/adding an item we increment the id and
store it in the item. So the items that are recently accessed will have a higher sequential ids than the older
ones.
 Cache Write Policy: A cache’s write policy is the behavior of a cache while performing a write operation.
A cache’s write policy plays a central part in all the variety of different characteristics exposed by the cache.

5
 Let’s now take a look at three policies:
• Write-through
• Write-around
• Write-back
 1. Write-through: Suppose we design our
cache to ensure consistency first. That is,
we’d want to update our backing store
synchronously before sending the response
back to the client. In case the requested
entry is not found in the cache, we create an
entry in cache storage first: 6
 2. Write-around: Now, write-through provides the best outcome in
case we expect written data to be accessed soon. Depending on our
cache usage pattern, this might be not true.
 If we do not expect a read operation shortly after, the cache would
become polluted with the entries we’re not using. To avoid cache
pollution, we may bypass cache entry allocation in case of a cache
miss:
 We refer to this policy as “write-through with no-write allocation”
or write-around.
 Yet another variation on write-through cache is write-invalidate
policy. In this mode, along with the write operations going directly
to the backing store, cache data entry undergoes invalidation in case
of a cache hit.
7
 3. Write-back: While write-through provides us the best
consistency, it does not help us with write operation latency – the
cache returns a response to the client only after the backing store is
updated.
 We may take advantage of our fast cache storage to streamline this
as well. To do this, we would have to return the response before
updating the backing store. In this case, the backing store update
happens asynchronously in a separate sequence.
 We can kick off such a sequence in several ways – right before the
response return, periodically, or integrated into cache eviction
based on cache entry dirty state. For CPU caches, we use a dirty
bit as a state indicator. In software caches, asynchronous kick-off
before response return is generally preferable.
 We call this type of policy write-back or write-behind: 8
 The asynchronous update brings us better responsiveness as well as the chance to improve throughput, for
example, using source storage update batching.
 Besides write-back having more difficult implementation, it’s possible to encounter consistency issues.
Having cache in volatile memory, power outage before write-back is complete would result in data loss.
 More subtle issues also emerge in write-back implementations. Consider when we access source storage not
only via our cache instance but using some other means as well – either by another cache instance(s) or a
direct write operation. The data which is not written to the backing store yet may reach the store only after
the direct write operation is completed.
 To ensure this does not happen, we must preserve operation order at some level. We call this technique
transaction serialization.
 Considering both the set of techniques to address this kind of problem and the concept itself we use the term
cache coherence

9
Summary
 Discussed about the replacement algorithms.
 Discussed about the Write policies.

Assessment Questions
Q1. What are the types of replacement algorithms?

10
THANK YOU

11