PHY 421:ELECTRONIC CIRCUITS

AND MICROPROCESSORS

INTERFACING
 Introduction
Interface is the path for communication between two components.
 Interfacing is of two types,
 Memory interfacing and
 I/O interfacing.
 Memory Interfacing
When we are executing any instruction, we need the microprocessor to access the
memory for reading instruction codes and the data stored in the memory. For this,
both the memory and the microprocessor requires some signals to read from and
write to registers.
The interfacing process includes some key factors to match with the memory
requirements and microprocessor signals.
The interfacing circuit therefore should be designed in such a way that it matches
the memory signal requirements with the signals of the microprocessor.
 IO Interfacing
There are various communication devices like the keyboard, mouse, printer,
etc. So, we need to interface the keyboard and other devices with the
microprocessor by using latches and buffers.
This type of interfacing is known as I/O interfacing.
• Block Diagram of Memory and
I/O Interfacing
Ways of Communication − Microprocessor with the Outside World

• There are two ways of communication in which the microprocessor can

connect with the outside world.

 Serial Communication Interface

 Parallel Communication interface
 Serial Communication Interface − In this type of communication, the
interface gets a single byte of data from the microprocessor and sends it bit
by bit to the other system serially and vice-a-versa.
 Parallel Communication Interface − In this type of communication, the
interface gets a byte of data from the microprocessor and sends it bit by bit
to the other systems in simultaneous (or) parallel fashion and vice-a-versa.
 8279 - Programmable Keyboard

• 8279 programmable keyboard/display controller is designed by Intel that

interfaces a keyboard with the CPU.
• The keyboard first scans the keyboard and identifies if any key has been
pressed.
• It then sends their relative response of the pressed key to the CPU and
vice-a-versa.
 Methods of interfacing keyboard
• The Keyboard can be interfaced either in the interrupt or the polled mode.
• In the Interrupt mode, the processor is requested service only if any key
is pressed, otherwise the CPU will continue with its main task.
• In the Polled mode, the CPU periodically reads an internal flag of 8279 to
check whether any key is pressed or not with key pressure.
 How 8279 Keyboard Work
• The keyboard consists of maximum 64 keys, which are interfaced with the
CPU by using the key-codes.
• These key-codes are de-bounced and stored in an 8-byte FIFORAM,
which can be accessed by the CPU.
• If more than 8 characters are entered in the FIFO, then it means more than
eight keys are pressed at a time. This is when the overrun status is set.
• If a FIFO contains a valid key entry, then the CPU is interrupted in an
interrupt mode else the CPU checks the status in polling to read the entry.
• Once the CPU reads a key entry, then FIFO is updated, and the key entry
is pushed out of the FIFO to generate space for new entries.
 8257 DMA Controller
• DMA stands for Direct Memory Access. It is designed by Intel to transfer data at
the fastest rate.
• It allows the device to transfer the data directly to/from memory without any
interference of the CPU.
• Using a DMA controller, the device requests the CPU to hold its data, address and
control bus, so the device is free to transfer data directly to/from the memory.
• The DMA data transfer is initiated only after receiving HLDA signal from the CPU.
 DMA Operations
 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU
to assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus.
The CPU leaves the control over bus and acknowledges the HOLD request through
HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the
operations over buses between the CPU, memory, and I/O devices.
 Features of 8257
 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer
operations.
 It generates MARK signal to the peripheral device that 128 bytes have been
transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.
 8257 Architecture
Block diagram Pin configuration
• DRQ0−DRQ3 - These are the four-individual • Do − D7 - These are bidirectional, data lines
channel DMA request inputs, which are used by which are used to interface the system bus with
the peripheral devices for using DMA services. the internal data bus of DMA controller. In the
When the fixed priority mode is selected, then Slave mode, it carries command words to 8257
DRQ0 has the highest priority and DRQ3 has the and status word from 8257. In the master mode,
lowest priority among them. these lines are used to send higher byte of the
generated address to the latch. This address is
• DACKo − DACK3 - These are the active-low further latched using ADSTB signal.
DMA acknowledge lines, which updates the
requesting peripheral about the status of their • IOR - It is an active-low bidirectional tri-state
request by the CPU. These lines can also act as input line, which is used by the CPU to read
strobe lines for the requesting devices. internal registers of 8257 in the Slave mode. In the
master mode, it is used to read data from the
peripheral devices during a memory write cycle.
• IOW - It is an active low bi-direction tri-state line, • Ao - A3 - These are the four least significant
which is used to load the contents of the data bus address lines. In the slave mode, they act as an
to the 8-bit mode register or upper/lower byte of input, which selects one of the registers to be read
a 16-bit DMA address register or terminal count or written. In the master mode, they are the four
register. In the master mode, it is used to load the least significant memory address output lines
data to the peripheral devices during DMA generated by 8257.
memory read cycle.
• CS - It is an active-low chip select line. In the
• CLK - It is a clock frequency signal which is Slave mode, it enables the read/write operations
required for the internal operation of 8257. to/from 8257. In the master mode, it disables the
read/write operations to/from 8257.
• RESET - This signal is used to RESET the DMA
controller by disabling all the DMA channels. • A4 - A7 - These are the higher nibble of the lower
byte address generated by DMA in the master
mode.
• READY - It is an active-high asynchronous input • MEMR - It is the low memory read signal, which
signal, which makes DMA ready by inserting wait is used to read the data from the addressed
states. memory locations during DMA read cycles.
• HRQ - This signal is used to receive the hold • MEMW - It is the active-low three state signal
request signal from the output device. In the slave which is used to write the data to the addressed
mode, it is connected with a DRQ input line 8257. memory location during DMA write operation.
In Master mode, it is connected with HOLD input
of the CPU. • ADST - This signal is used to convert the higher
byte of the memory address generated by the
• HLDA - It is the hold acknowledgement signal DMA controller into the latches
which indicates the DMA controller that the bus
has been granted to the requesting peripheral by
the CPU when it is set to 1.
• AEN - This signal is used to disable the address bus/data bus. TC - It stands
for „Terminal Count‟, which indicates the present DMA cycle to the present
peripheral devices.
• MARK - The mark will be activated after each 128 cycles or integral
multiples of it from the beginning. It indicates the current DMA cycle is the
128th cycle since the previous MARK output to the selected peripheral
device.
• Vcc - It is the power signal which is required for the operation of the circuit.
Control word format
THANK
YOU