DIFFERENCE BETWEEN FUNCTION AND TASK
////DIFFERENCES BETWEEN FUNCTION AND TASK IN VERILOG
DIFFERENCE#1
Execution Time:
Function :
Function executes in a single simulation time step (That is in zero time delay)
and cannot contain any timing controls like #, @, or wait statements.
Task :
Task can execute across multiple simulation time steps because it is allowed to
include timing controls, such as # for delays, @ for event controls, or wait.
DIFFERENCE#2
Return Value:
Function :
Function must return a single value and return data type is defined when
declaring the function and the return value should be assigned to the function
name itself inside the function(i.e>must not use return keyword).
Task :
A task does not return a value directly and instead of that it can have multiple
outputs, inputs and inouts which can added as arguments while declaring the
task.
DIFFERENCE#3
Input and Output Arguments:
Function :
A function can only take input arguments but it must not have output or inout
arguments and it should have atleast one argument. All inputs must be provided
when the function is called(i.e> as arguments inside the brackets).
Task :
A task can take input, output, and inout arguments. All arguments must be
provided when the task is called i.e>inside the brackets.
DIFFERENCE#4
Usage Scope:
Function :
Functions are generally used for combinational logic, mathematical calculations,
or simple transformations where no delays are involved.
Task :
Tasks are used when sequential logic or operations that require timing control,
delays, or multiple outputs are needed.
DIFFERECE#5
Nature:
Function :
Functions are always blocking due to its zero-time execution and the absence of
timing controls.
Task :
Tasks can be blocking or non-blocking, depending on whether they included with
timing controls or blocking/non-blocking assignments in Verilog
DIFFERENCE#6
Calling inside another Function/Task:
Function :
Function can be called inside both Task and Function but task can not be called
inside the another function because task may contains the delay statements which
shouldnot be included inside the function
Task :
Task can be called inside another Task and Function can be called inside the
another Task but not viceversa as mentioned in the above point.
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////DIFFERENCE BETWEEN VERILOG AND SV => TASK, FUNCTION
DIFFERENCE#1
Verilog :
Statements/Logic should be written inside begin-end block in both function and
task.
SV :
No need of any begin and end to write logic/statements inside task or
function
DIFFERNCE#2
Verilog :
Functions can have only inputs , atleast one input.
SV :
Functions can have both inputs and outputs in arguments, we have multiple inputs
and outputs
DIFFERENCE#3
Verilog :
Functions should return the values using functions name itself with return type
SV :
Functions can return the values either through arguments or return types
DIFFERENCE#4
Verilog :
Function/task values must be passed when those methods are called
SV :
Function/task can have default values, if we wont pass any values it takes
default values
DIFFERENC#5
Verilog :
Function without return types is not possible
SV :
Function without return is possible, there we can use void as return keyword
DIFFERENCE#6
Verilog :
Function/task doesn't support return keyword
SV :
Function/task can support return keyword
DIFFERENCE#7
Verilog :
In task/function call we can only pass values
SV :
In task/function call we can pass either values or handles
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