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Microprocessor

The 80286 microprocessor, introduced by Intel in 1982, is a 16-bit processor with a 24-bit address bus and enhanced performance over its predecessor, the 8086. It operates in two modes: real address mode and protected virtual-address mode, allowing for multitasking and virtual memory utilization. The document also discusses the architecture, functional units, and interrupt handling of the 80286, as well as the advancements made in the subsequent 80386 microprocessor, which supports 32-bit operations and improved multitasking capabilities.
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0% found this document useful (0 votes)
23 views7 pages

Microprocessor

The 80286 microprocessor, introduced by Intel in 1982, is a 16-bit processor with a 24-bit address bus and enhanced performance over its predecessor, the 8086. It operates in two modes: real address mode and protected virtual-address mode, allowing for multitasking and virtual memory utilization. The document also discusses the architecture, functional units, and interrupt handling of the 80286, as well as the advancements made in the subsequent 80386 microprocessor, which supports 32-bit operations and improved multitasking capabilities.
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80286 Microprocessor

80286 Microprocessor is a 16-bit microprocessor that has the ability to execute 16-bit
instruction at a time. It has non-multiplexed data and address bus. The size of data bus is 16-
bit whereas the size of address bus is 24-bit.
It was invented in February 1982 by Intel. 80286 microprocessor was basically an
advancement of 8086 microprocessor. Further in 1985, Intel produced upgraded version of
80286 which was a 32-bit microprocessor.

The factors that make 80286 more advantageous than 8086 microprocessor?

 It has non-multiplexed address and data bus that reduces operational speed.
 The addressable memory in case of 80286 is 16 MB.
 It offers an additional adder for address calculation.
 80286 has faster multipliers that lead to quick operation.
 The performance per clock cycle of 80286 is almost twice when compared with
8086 or 8088.
 Operating modes of 80286 microprocessor

80286 operates in two modes:

In real address mode:


 This microprocessor acts as a version of 8086 which is quite faster.
 Also without any special modification, the instruction programmed for 8086 can be
executed in 80286.
 It offers memory addressability of 1 MB of physical memory.

Protected virtual-address mode:


 Protected virtual-address mode of 80286 supports multitasking because
multiple programs can be executed using virtual memory.
 This mode of 80286 offers memory addressability of 16 MB of physical
memory along with 1 GB of virtual memory.

As using virtual memory, space for other programs can be saved. Sometimes bulky programs
also do exist that cannot be stored in physical memory, so virtual memory is utilized in order
to execute large programs.

What is virtual memory?

Virtual memory is that part of hard disk which can be utilized for storing large instructions
inside the system. This extra memory can be addressed by the computer other than the
physical memory.

When there exists an instruction that is to be loaded in the memory but whose size is greater
than the provided physical memory. Then some part of hard disk is used in order to store that
instruction, which is known as virtual memory.

Architecture of 80286 Microprocessor

The figure below shows the architectural representation of 80286 microprocessor:

It is a 16-bit microprocessor thus holds a 16-bit data bus and 24-bit address bus.

80286 is composed of nearly around 125K transistors and the pin configuration has a total of
68 pins. (Pin diagram is in Difference btw 80286,80386 & 80486 pdf)
The CPU, central processing unit of 80286 microprocessor, consists of 4 functional block:

 Address Unit
 Bus Unit
 Instruction Unit
 Execution Unit

Firstly, the physical address from where the data or instruction is to be fetched is calculated,
by the address unit. Once the physical address is calculated then the calculated address is
handed over to the bus unit. More specifically we can say, that the calculated address is
loaded on the address bus of the bus unit.
This address specifies the memory location from where the data or instruction is to be
fetched. The fetching of data through the memory is done through the data bus. For faster
execution of instruction, the BU fetches the instructions in advanced from the memory and
stores them in the queue.

This is done through the bus control module. As we have discussed that the prefetched
instructions are stored in a 6-byte instruction queue. This instruction queue then further
sends the instruction to the instruction unit.

The instruction unit on receiving the instructions now starts decoding the instruction. As
instructions are stored in prefetched queue thus the decoder continuously decodes the fetched
instructions and stores them into decoded instruction queue.

Now after the instructions gets decoded then further these are needed to be executed. So, the
instructions from decoded instruction queue are fed to the execution unit. The main
component of EU is ALU i.e., arithmetic and logic unit that performs the arithmetic and logic
operations over the operand according to the decoded instruction.
Once the execution of the instruction is performed then the result of the operation i.e., the
desired data is send to the register bank through the data bus.

As we have already discussed that 80286 is just a modified version of 8086. The register set
in 80286 is same as that of 8086 microprocessor.

 It holds 8 general purpose registers of 16 bit each.


 It contains 4 segment register each of 16-bit.
 Also has status and control register and instruction pointer.

Interrupt of 80286 Microprocessor

We know that whenever an interrupt gets generated in a system, then the execution of the
current program is stopped and the execution gets transferred to the new program location
where the interrupt is generated.

But once the interrupt gets executed then then in order to get back to the original program, its
address as well as machine state must be stored in the stack. Basically there exist 3 categories
of interrupt in 80286 microprocessor:

 External interrupt (Hardware interrupt)


 INT instruction interrupt (Software interrupt)
 Internally generated interrupt due to some exceptions
External or hardware initiate interrupt are those interrupts that gets generated due to an
external input. And are basically of two types:
1. Maskable interrupt
2. Non-maskable interrupt
Sometimes when multiple programs are allowed to be executed in a system, then this leads to
generation of INT instruction, and such an interrupt is known as software interrupt.
Another interrupt in 80286 exist due to some unusual conditions or situations generated in the
system that leads to prevention of further execution of the current instruction.

So, this is all about the modes of operation, architecture and interrupts of 80286
microprocessor.

80386 Microprocessor
80386 Microprocessor is a 32-bit processor that holds the ability to carry out 32-bit
operations in one cycle. It has a data and address bus of 32-bit each. Thus has the ability to
address 4 GB (or 232) of physical memory.
Multitasking and protection capability are the two key characteristics of the 80386
microprocessor. 80386 has internal dedicated hardware that permits multitasking.
We know 8086 is a 16-bit microprocessor and 80286 was an advancement of 8086 with some
additional characteristics. But with the advent of technology intel introduced a 32-bit
microprocessor whose processing speed was twice that of the 80286 microprocessor. This
was an 80386 microprocessor that was designed by Intel in October 1985 and was an
upgraded version of the 80286 microprocessor.

Features of 80386

 As it is a 32-bit microprocessor. Thus has a 32-bit ALU.


 80386 has a data bus of 32-bit.
 It holds an address bus of 32 bit.
 It supports physical memory addressability of 4 GB and virtual memory
addressability of 64 TB.
 80386 supports a variety of operating clock frequencies, which are 16 MHz, 20
MHz, 25 MHz, and 33 MHz.
 It offers 3 stage pipeline: fetch, decode and execute. As it supports simultaneous
fetching, decoding, and execution inside the system.

Operating modes of 80386

We have already discussed in our previous article that 80286 supports two operating modes.
The first is real address mode while the second is the protected virtual address mode.
However, 80386 supports 3 operating modes: real, protected, and virtual real mode.

Of the two modes of 80286 microprocessor, initially, the 80286 was booted in real mode.
However, to have better operating performance, separate software command is used to switch
from the real mode to the protected mode. But it requires the resetting of the microprocessor
in order to switch to real mode from protected mode. This drawback was eliminated in 80386
that allows the switching between the modes using software commands.

In the protected mode, 80386 microprocessor operates in a similar way like 80286 but offers
higher memory addressing ability.
In virtual mode, the overall memory of 80386 can be divided into various virtual machines.
And all of them acts as a separate computer with 8086 microprocessor. This mode is also
called virtual 8086 mode or V86 mode.
The other one is the virtual real mode, this mode allows the system to execute multiple
programs in the protected memory. And in case a program at a particular memory gets
crashed then it will not cause any adverse effect on the other part of the memory.
Architecture of 80386 Microprocessor

The figure below shows the architectural representation of 80386 microprocessor:

Basically, it has 6 functional units which are as follows:

1. Bus Interface Unit


2. Code Fetch Unit
3. Instruction Decode Unit
4. Execution Unit
5. Memory Management Unit
As we have already discussed that the 80386 possesses the ability of 3 stages pipelining thus
performs fetching, decoding, and execution simultaneously along with memory management
and bus accessing. Thus all these units operate parallelly. This pipelining technique leads to a
reduction in overall processing time thereby increasing the performance of the overall
system.

Let us now move further and understand the operation of each unit in detail.
1. Bus Interface Unit

The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as a 32-bit address
bus. Whenever a need for instruction or a data fetch is generated by the system then the BIU
generates signals (according to the priority) for activating the data and address bus in order to
fetch the data from the desired address.

The BIU connects the peripheral devices through the memory unit and also controls the
interfacing of external buses with the coprocessors.

2. Code Prefetch Unit

This unit fetches the instructions stored in the memory by making use of system buses.
Whenever the system generates a need for instruction then the code prefetch unit fetches that
instruction from the memory and stores it in a 16-byte prefetch queue. So to speed up the
operation this unit fetches the instructions in advance and the queue stores these instructions.
The sequence in which the instructions are fetched and gets stored in the queue depends on
the order they exist in the memory.
As this unit fetches one double word in a single access. So, in such a case, it is not necessary
that each time only a single instruction will be fetched, as the fetched instruction can be parts
of two different instructions.

It is to be noted here that, code prefetching holds lower priority than data transferring. As
whenever a need for data transfer is generated by the system then immediately the code
prefetcher leaves control over the buses. So that the BIU can transfer the required data. But
prefetching of instruction and storing it in the queue reduces the wait for the upcoming
instruction to almost zero.

3. Instruction Decode Unit

We know that instructions in the memory are stored in the form of bits. So, this unit decodes
the instructions stored in the prefetch queue. Basically the decoder changes the machine
language code into assembly language and transfers it to the processor for further execution.

4. Execution Unit

The decoded instructions are stored in the decoded instruction queue. So, these instructions
are provided to the execution unit in order to execute the instructions. The execution unit
controls the execution of the decoded instructions. This unit has a 32-bit ALU, that performs
the operation over 32-bit data in one cycle. Also, it consists of 8 general purpose as well as 8
special purpose registers. These are used for data handling and calculation of offset address.

5. Memory Management Unit

This unit has two separate units within it. These are

1. Segmentation Unit and


2. Paging Unit
Segmentation unit: The segmentation unit plays a vital role in the 80836 microprocessor. It
offers a protection mechanism in order to protect the code or data present in the memory from
application programs. It gives 4 level protection to the data or code present in the memory.
Every information in the memory is assigned a privilege level from PL0 to PL3. Here, PL0
holds the highest priority and PL3 holds the lowest priority.
Suppose a file (either data or code) is needed to be accessed is stored in the memory at PL0.
Then only those programs which are working at PL0 would be able to access that file. While
other programs will not be able to access the same. Also, if a file is present at PL1, then
programs of PL0 and PL1 both can access it. As PL0 has a higher priority than PL1. So, for
protection purposes, the main part of the OS is stored in PL0 while PL3 holds the user
programs. Providing protection to the data or code inside the system is the most advantageous
factor that was first given by the 80386 microprocessor.

Paging Unit: The paging unit operates only in protected mode and it changes the linear
address into a physical address. As the programmer only provides the virtual address and not
the physical address. The segmentation unit controls the action of the paging unit, as the
segmentation unit has the ability to convert the logical address into the linear address at the
time of executing an instruction. Basically, it changes the overall task map into pages and
each page has a size of 4K. This allows the handling of tasks in the form of pages rather than
segments.
The paging unit supports multitasking. This is so because the physical memory is not
required to hold the whole segment of any task. Despite this, only that part of the segment
which is needed to be currently executed must be stored in that memory whose physical
address is calculated by the paging unit. This resultantly reduces the memory requirement and
hence this frees the memory for other tasks. Thus by this we get an effective way for
managing the memory to support multitasking

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