be active. A RAM contains one or two control inputs. They are R / W or RD and WR .
If there is only one
input R/ W then it performs read operation when R/ W pin is at logic 1. If it is at logic 0 it performs write
operation. Note that this is possible only when CS is also active.
4.4 Memory Interface using RAMS, EPROMS and EEPROMS
(Ref: Advanced Microprocessors and Peripherals by A.K. Ray & K.M. Bhurchandi, McGraw-Hill, 2nd Edition.P.158-
164)
Semiconductor Memory Interfacing:
Semiconductor memories are of two types, viz. RAM (Random Access Memory) and ROM (Read Only
Memory).
Static RAM Interfacing:
The semiconductor RAMs are of broadly two types-static RAM and dynamic RAM. The
semiconductor memories are organized as two dimensional arrays of memory locations. For example, 4K x 8
or 4K byte memory contains 4096 locations, where each location contains 8-bit data and only one of the 4096
locations can be selected at a time. Obviously, for addressing 4K bytes of memory, twelve address lines are
required. In general, to address a memory location out of N memory locations , we will require at least n bits
of address, i.e. n address lines where n = Log2 N. Thus if the microprocessor has n address lines, then it is
able to address at the most N locations of memory, where 2n = N. However, if out of N locations only P
memory locations are to be interfaced, then the least significant p address lines out of the available n lines can
be directly connected from the microprocessor to the memory chip while the remaining (n-p) higher order
address lines may be used for address decoding (as inputs to the chip selection logic). The memory address
depends upon the hardware circuit used for decoding the chip select ( CS ). The output of the decoding circuit
is connected with the CS pin of the memory chip. The general procedure of static memory interfacing with
8086 is briefly described as follows:
1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit bank is
called ‘odd address memory bank’ and the lower 8-bit bank is called ‘even address memory bank’.
2. Connect available memory address lines of memory chips with those of the microprocessor and
also connect the memory RD and WR inputs to the corresponding processor control signals. Connect the
16-bit data bus of the memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and A0 are used for decoding the
required chip select signals for the odd and even memory banks. CS of memory is derived from the O/P of
the decoding circuit.
As a good and efficient interfacing practice, the address map of the system should be continuous as
far as possible, i.e. there should be no windows in the map. A memory location should have a single address
corresponding to it, i.e. absolute decoding should be preferred, and minimum hardware should be used for
decoding. In a number of cases, linear decoding may be used to minimise the required hardware. Let us now
consider a few example problems on memory interfacing with 8086.
SERIAL COMMUNICATION STANDARDS
(Ref: Interfacing through Microprocessors by K. Subba Rao, Hi-tech publishers, P. 250-260)
Most of devices are parallel in nature. These devices transfer data simultaneously on data lines. But
parallel data transfer process is very complicated and expensive. Hence in some situations the serial I/O mode
is used where one bit is transferred over a single line at a time. In this type of transmission parallel word is
converted into a stream of serial bits which is known as parallel to serial conversion. The rate of transmission
in serial mode is BAUD, i.e., bits per second. The serial data transmission involves starting, end of
transmission, error verification bits along with the data. Any serial I/O involves the following concepts.
