MODULE 2 EC 15-1503 EMBEDDED

SYSTEMS

19-08-2020 INTERFACNG KEYBOARD WITH 8051 1

CONTENTS
❑ General Description of KEYPAD.
❑ How to detect a key press?
❑ The interfacing diagram of keypad with 8051.
❑ The program
❑ Main Problem

19-08-2020 INTERFACNG KEYBOARD WITH 8051 2

KEYPAD
• Keypad is used as an input device to read the key
pressed by user and to process it.
• 4x4 keypad consists of 4 rows and 4 columns.
Switches are placed between the rows and columns. A
key press establishes a connection between
corresponding row and column between which the
switch is placed.
• To read the key press, we need to configure the rows
as outputs and columns as inputs.
• Columns are read after applying signals to the rows in
order to determine whether or not a key is pressed and
if pressed, which key is pressed.

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TO DETECT A KEY
• Two approaches are there called column scanning ,row scanning.
• Consider column scanning , make each row 1 and others 0 and then scan
each column.
• If any switch is pressed corresponding column’s sense value is zero.
• The pressed switch make corresponding column and row shorted.
• Row scanning is just the opposite of column scanning technique.

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THE INTERFACING DIAGRAM

19-08-2020 INTERFACNG KEYBOARD WITH 8051 5

PROGRAM
ORG 00H
MOV DPTR, #LUT //moves starting address of LUT to DPTR
MOV A, #11111111B
MOV P0, #00000000B //initializes P0 as output port
BACK: MOV P1, #11111111B
CLR P1.0 //makes row 1 low
JB P1.4, NEXT1 //checks whether column 1 is low and jumps
to next1 if not low.

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PROGRAM
MOV A, #0D //loads A with 0D if column is low( means a key is
pressed)
ACALL DISPLAY // calls DISPLAY subroutine
NEXT1: JB P1.5, NEXT2 // checks whether column 2 is low and so on….
MOV A, #1D
ACALL DISPLAY
NEXT2: JB P1.6, NEXT3
MOV A, #2D
ACALL DISPLAY
NEXT3: JB P1.7, NEXT4

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PROGRAM
MOV A, #3D
ACALL DISPLAY
NEXT4: SETB P1.0
CLR P1.1
JB P1.4, NEXT5
MOV A, #4D
ACALL DISPLAY
NEXT5: JB P1.5, NEXT6
MOV A, #5D
ACALL DISPLAY

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PROGRAM
NEXT6: JB P1.6, NEXT7
MOV A, #6D
ACALL DISPLAY
NEXT7: JB P1.7, NEXT8
MOV A, #7D
ACALL DISPLAY
NEXT8: SETB P1.1
CLR P1.2
JB P1.4, NEXT9
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PROGRAM
MOV A, #8D
ACALL DISPLAY
NEXT9: JB P1.5, NEXT10
MOV A, #9D
ACALL DISPLAY
NEXT10: JB P1.6, NEXT11
MOV A, #10D
ACALL DISPLAY
NEXT11: JB P1.7, NEXT12
MOV A, #11D
ACALL DISPLAY

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PROGRAM
NEXT12: SETB P1.2
CLR P1.3
JB P1.4, NEXT13
MOV A, #12D
ACALL DISPLAY
NEXT13: JB P1.5, NEXT14
MOV A, #13D
ACALL DISPLAY
NEXT14: JB P1.6, NEXT15
MOV A, #14D
ACALL DISPLAY

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PROGRAM
NEXT15: JB P1.7, BACK
MOV A, #15D
ACALL DISPLAY
LJMP BACK
DISPLAY: MOVC A, @A+DPTR //gets digit drive pattern for the current key
from LUT
MOV P0,A //puts corresponding digit drive pattern into
P0
RET

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PROGRAM
LUT: DB 01100000B // Lookup table starts here
DB 11011010B
DB 11110010B
DB 11101110B
DB 01100110B
DB 10110110B
DB 10111110B
DB 00111110B
DB 11100000B
DB 11111110B
DB 11110110B
DB 10011100B
DB 10011110B
DB 11111100B
DB 10001110B
DB 01111010B
END
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MAIN PROBLEM
• Switch contacts do not come to rest immediately after pressing.
• microcontroller sense multiple key press due to multiple pulse generation.
• A human cannot press and release a key in less than 20 ms.
• Debouncing problem solution
• hardware solution
• software solution

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 MODULE 2
EC 15-1503 EMBEDDED SYSTEMS

20-08-2020 Interfacing stepper motor with 8051 1

CONTENTS

■ STEPPER MOTOR
■ INTERFACING DIAGRAM
■ 4 STEP SEQUENCE
■ CODE
■ ANOTHER CODE
■ PROTEUS CONNECTION DIAGRAM

20-08-2020 Interfacing stepper motor with 8051 2

STEPPER
MOTOR
▪ A stepper motor is a type of DC
motor that rotates in steps. When
electrical signal is applied to it,
the motor rotates in steps and the
speed of rotation depends on the
rate at which the electrical
signals are applied and the
direction of rotation is
dependent on the pattern of
pulses that is followed.

Interfacing stepper motor with

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8051
STEPPER MOTOR

■ Stepper motor divides the full rotation angle of 360° into number of equal steps.
■ Total no. of steps = Total rotational angle / step angle.
■ Take step angle =1.8 so, 360/1.8 = 200 steps are required to complete one
rotation.
■ Total no. of repeated steps = Total no. of steps / Step sequence
■ 200 / 4 = 50 = 32H
■ There are 4 stepper motor coils.

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INTERFACING
DIAGRAM
▪ The stepper motors coil A,B,C,D is
connected to the port 1 i.e. to P1.0,
P1.2, P1.2 and P1.3.

▪ The Microcontroller does not

provide sufficient current to drive
motor and to safeguard 8051 from
loading effect and burn out
condition, a motor driver IC ULN
2003 is used between 8051 and
stepper motor. ULN 2003 is a
stepper motor driver.

Interfacing stepper motor with

20-08-2020 5
8051
4 STEP SEQUENCE

A B C D Hex Code Comments

1 0 0 1 09
1 1 0 0 0C Sequence for
0 1 1 0 06 Clockwise rotation
0 0 1 1 03

0 0 1 1 03
0 1 1 0 06 Sequence for
1 1 0 0 0C Anti-clockwise rotation
1 0 0 1 09

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PROGRAM CODE

ORG 0000H
HERE: MOV A, #99H
MOV R0, #200
BACK : MOV P1, A
ACALL DELAY
RR A
DJNZ R0, BACK
SJMP HERE

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PROGRAM CODE

DELAY : MOV R2, #225

L2 : MOV R3, #225
L1 : DJNZ R3, L1
DJNZ R2, L2
RET
END

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ANOTHER CODE

back: setb p2.0

acall delay
clr p2.0
setb p2.1
acall delay
clr p2.1
setb p2.2
acall delay

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ANOTHER CODE

clr p2.2
setb p2.3
acall delay
clr p2.3
sjmp back
delay: mov r7,#64h
back1: mov tmod,#01h
mov th0,#0dbh

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ANOTHER CODE

mov tl0,#0ffh
setb tr1
l1: jnb tf1,l1
clr tr1
clr tf1
djnz r7,back1
ret
end

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20-08-2020 Interfacing stepper motor with 8051 12
Module II
EMBEDDED SYSTEMS
Contents
• LED pins
• LED Interfacing
• Programs
• Interfacing diagram with 8051
• LCD pins
• LCD Interfacing
• LCD Program

13-10-2020 EC 1503 Embedded Systems Gayathri R 2

8 LEDs are connected to port 0.Write a program to blink them with 1
sec delay.

back:mov a,#0ffh
mov p0,a
acall delay
mov a,#00h
mov p0,a
acall delay
sjmp back
delay:mov r7,#64h

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back1:mov tmod,#01h
mov th0,#0dbh
mov tl0,#0ffh
setb TR0
l1:jnb TF0,l1
clr TR0
clr TF0
djnz r7,back1
ret
End
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8 LEDs are connected to port 2.Write a program to blink them alternatively.
back:mov a,#0aah
mov p2,a
acall delay
mov a,#55h
mov p2,a
acall delay
sjmp back
delay:mov r7,#64h
back1:mov tmod,#01h
mov th0,#093h
mov tl0,#0ffh
setb TR0
l1:jnb TF0,l1
clr TR0
clr TF0
djnz r7,back1
ret
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13-10-2020 EC 1503 Embedded Systems Gayathri R 6
Designing a delay program using 8051 timers.

While designing delay programs in 8051, calculating the initial value

that has to be loaded into TH and TL registers forms a very important
thing.
• Assume the processor is clocked by a 12MHz crystal.
• That means, the timer clock input will be 12MHz/12 = 1MHz
• That means, the time taken for the timer to make one increment =
1/1MHz = 1uS
• For a time delay of “X” uS the timer has to make “X” increments.

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• 2^16 = 65536 is the maximum number of counts possible for a 16 bit
timer.
• Let TH be the value that has to be loaded to TH register and TL be the
value that has to be loaded to TL register.
• Then, THTL = Hexadecimal equivalent of (65536-X) where (65536-X)
is considered in decimal.

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 Pin No: Name Function

LCD Module 1 VSS This pin must be connected to the ground

2 VCC Positive supply voltage pin (5V DC)

3 VEE Contrast adjustment

4 RS Register selection

5 R/W Read or write

6 E Enable

7 DB0 Data

8 DB1 Data

9 DB2 Data

10 DB3 Data

11 DB4 Data

12 DB5 Data

13 DB6 Data

14 DB7 Data

15 LED+ Back light LED+

16 LED- Back light LED-

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16×2 LCD module commands.
16×2 LCD module has a set of preset command instructions. Each command will
make the module to do a particular task. The commonly used commands and their
function are given in the table below.
Command Function

0F LCD ON, Cursor ON, Cursor blinking ON

01 Clear screen

02 Return home

04 Decrement cursor

06 Increment cursor

0E Display ON ,Cursor blinking OFF

80 Force cursor to the beginning of 1st line

C0 Force cursor to the beginning of 2nd line

38 Use 2 lines and 5×7 matrix

83 Cursor line 1 position 3

3C Activate second line

08 Display OFF, Cursor OFF

C1 Jump to second line, position1

OC Display ON, Cursor OFF

C1 Jump to second line, position1

C2 Jump to second line, position2

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13-10-2020 EC 1503 Embedded Systems Gayathri R 11
The steps that has to be done for initializing the
LCD display is given below and these steps are
common for almost all applications.
• Send 38H to the 8 bit data line for initialization
• Send 0FH for making LCD ON, cursor ON and cursor blinking ON.
• Send 06H for incrementing cursor position.
• Send 01H for clearing the display and return the cursor.

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Sending data to the LCD.
The steps for sending data to the LCD module is given below. It is the
logic state of RS, R/W and E pins that make the module to determine
whether a given data input is a command or data to be displayed.
• Make R/W low.
• Make RS=0 if data byte is a command and make RS=1 if the data byte
is a data to be displayed.
• Place data byte on the data register.
• Pulse E from high to low.
• Repeat above steps for sending another data.

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MOV A,#38H // Use 2 lines and 5x7 matrix
ACALL CMND
MOV A,#0FH // LCD ON, cursor ON, cursor blinking ON
ACALL CMND
MOV A,#01H //Clear screen
ACALL CMND
MOV A,#06H //Increment cursor
ACALL CMND
MOV A,#82H //Cursor line one , position 2
ACALL CMND
MOV A,#3CH //Activate second line
ACALL CMND
MOV A,#49D
ACALL DISP
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MOV A,#54D
ACALL DISP
MOV A,#88D
ACALL DISP
MOV A,#50D
ACALL DISP
MOV A,#32D
ACALL DISP
MOV A,#76D
ACALL DISP
MOV A,#67D
ACALL DISP
MOV A,#68D
ACALL DISP
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MOV A,#0C1H //Jump to second line, position 1
ACALL CMND
MOV A,#67D
ACALL DISP
MOV A,#73D
ACALL DISP
MOV A,#82D
ACALL DISP
MOV A,#67D
ACALL DISP
MOV A,#85D
ACALL DISP
MOV A,#73D
ACALL DISP
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MOV A,#84D
ACALL DISP
MOV A,#83D
ACALL DISP
MOV A,#84D
ACALL DISP
MOV A,#79D
ACALL DISP
MOV A,#68D
ACALL DISP
MOV A,#65D
ACALL DISP
MOV A,#89D
ACALL
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DISP EC 1503 Embedded Systems Gayathri R 17
HERE: SJMP HERE
CMND: MOV P1,A
CLR P3.5
CLR P3.4
SETB P3.3
CLR P3.3
ACALL DELY
RET
DISP:MOV P1,A
SETB P3.5
CLR P3.4
SETB P3.3
CLR P3.3
ACALL DELY
RET
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DELY: CLR P3.3
CLR P3.5
SETB P3.4
MOV P1,#0FFh
SETB P3.3
MOV A,P1
JB ACC.7,DELY

CLR P3.3
CLR P3.4
RET

END
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MODULE II (lecture 14)
EMBEDDED SYSTEMS
Contents
• Frequency Counter Using 8051
• Frequency Counter Program
• Temperature Measurement Using 8051
• INTERFACE LM35 TEMPERATURE SENSOR WITH 8051 (AT89C51)
• Interfacing diagram
• PROGRAM

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 Frequency Counter using 8051
• When 8051 is used as a counter, it
is the pulse outside the 8051 that
increments the TH,TL registers.
Port 3 Pins used for Timers 0 and 1
Descriptio
Pin No Port Pin Function
n
Timer/Cou
nter 0
14 P3.4 T0
external
Input
Timer/Cou
nter 1
15 P3.5 T1
external
Input
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Design a counter for counting the pulses of an input signal. The pulses
to be counted are fed to pin P3.4.

ORG 00H
Start: MOV TMOD,#15H; timer 1 as timer and Timer0 as counter
SETB P3.4; set P3.4 as input pin
MOV TL0,#00H; clear TL0
MOV THO,#00H; CLEAR TH0
SETB TR0; Start counter
MOV R0,#28; R0=28,for time=1 sec
Again: MOV TL1,#00H;
MOV TH1,#00H;
SETB TR1; Start timer 1

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Back: JNB TF1,Back; monitor timer1 overflow flag
CLR TF1; monitor timer1 overflow flag
DJNZ R0,Again; repeat the loop until R0=0
MOV A,TL0; 1sec time period is finished now save count
from TLO in A
MOV P2,A; send it to port2
MOV A,TH0; move TH0 into A
MOV P1,A; Send it to port P1
SJMP Start
END

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INTERFACE LM35 TEMPERATURE SENSOR WITH 8051
(AT89C51)

• LM35 which is a very common Temperature Sensor giving high

precision reading in terms of Analog Voltage with most popular
8051 Microcontroller AT89C51. The sensitivity of LM35 is 10
mV/degree Celsius.
• LM35 gives analog reading and microcontroller process digital
data so we have to use a midway converter from Analog to
Digital i.e. AD0804 and display the result of a temperature on
LCD.

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• Temperature Sensor (LM35):
• LM35 looks like a transistor it will give you temperature in Celsius in terms
of millivolt. For example if the temperature is 25 C its output will give you
0.25V provided that you must supply at least 1V to it.
• Analog to Digital Converter (ADC0804):
• An analog-to-digital converter is a device that converts a continuous
physical quantity (usually voltage) to a digital number that represents the
quantity’s amplitude.

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Interfacing diagram

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Program
ORG 00H
MOV P1,#11111111B // initializes P1 as input port
MOV P0,#00000000B // initializes P0 as output port
MOV P3,#00000000B // initializes P3 as output port
MOV DPTR,#LABEL // loads the address of "LABEL" to DPTR
MAIN: MOV R4,#250D // loads register R4 with 250D
CLR P3.7 // makes CS=0
SETB P3.6 // makes RD high
CLR P3.5 // makes WR low
SETB P3.5 // low to high pulse to WR for starting conversion
WAIT: JB P3.4,WAIT // polls until INTR=0
CLR P3.7 // ensures CS=0
CLR P3.6 // high to low pulse to RD for reading the data from ADC

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 MOV A,P1 // moves the digital output of ADC to accumulator A
MOV B,#10D // load B with 10D
DIV AB // divides the content of A with that in B
MOV R6,A // moves the quotient to R6
MOV R7,B // moves the remainder to R7
DLOOP:SETB P3.2 // sets P3.2 which activates LED segment 1
MOV A,R6 // moves the quotient to A
ACALL DISPLAY // calls DISPLAY subroutine
MOV P0,A // moves the content of A to P0
ACALL DELAY // calls the DELAY subroutine
CLR A // clears A

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MOV A,R7 // moves the remainder to A
CLR P3.2 // deactivates LED segment 1
SETB P3.1 // activates LED segment 2
ACALL DISPLAY
MOV P0,A
ACALL DELAY
CLR A
CLR P3.1 // deactivates LED segment 2
DJNZ R4,DLOOP // repeats the loop "DLOOP" until R4=0
SJMP MAIN // jumps back to the main loop
DELAY: MOV R3,#255D // produces around 0.8mS delay
LABEL1: DJNZ R3,LABEL1
RET
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DISPLAY: MOVC A,@A+DPTR // converts A's content to corresponding digit
drive pattern
RET
LABEL: DB 3FH // LUT (look up table) starts here
DB 06H
DB 5BH
DB 4FH
DB 66H
DB 6DH
DB 7DH
DB 07H
DB 7FH
DB 6FH
END

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 27-09-2018

Synchronous Serial Interfaces What is I2C

 The name stands for “Inter - Integrated Circuit Bus”

I2C  A Small Area Network connecting ICs and other

electronic systems

 Originally intended for operation

on one single board / PCB
 Developed and patented by Philips
for connecting low speed peripherals
SPI to a motherboard, embedded system
or cell phone

 A variety of devices are at present available with I2C

Interfaces
 Microcontroller, EEPROM, Real-Timer, interface chips, LCD
driver, A/D converter
Dr Binu paul , EMB 1 of 40 Dr Binu paul , EMB 2 of 40

What is I2C What is I2C used for?

 Multi-master, two wire bus , up to 100 kbits/sec
 Data transfer between ICs and systems at
 Synchronous Serial Signal relatively low rates
 Two wires carry information between 3 modes of operation
a number of devices  “Classic” I2C is rated to 100K bits/second
 One wire used for the data [SDA]  “Fast Mode” devices support up to 400K bits/second
 One wire used for the clock [SCL]
 Master controls clock for slaves  A “High Speed Mode” is defined for operation up to 3.4M
bits/second
 Each connected slave has a
unique 7-bit address
 Reduces Board Space and Cost By:
 Allowing use of ICs with fewer pins and smaller packages
 Greatly reducing interconnect complexity
 Allowing digitally controlled components to be located
close to their point of use
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 27-09-2018

I2C Bus Characteristics I2C Bus Characteristics

 Includes electrical and timing specifications,  Unique start and stop condition
and an associated bus protocol
 Two wire serial data & control bus implemented with the serial  Transfers are byte oriented, most significant bit (msb)
data (SDA) and clock (SCL) lines first
 For reliable operation, a third line is required:Common ground
 Slave selection protocol uses a 7-Bit slave address
 Devices connected to the bus must have an open drain or open  The bus specification allows an extension to 10 bits
collector output for serial clock and data signal
 Bi-directional data transfer
 The serial clock and data lines are connected to Vdd(typically
 Acknowledgement after each transferred byte
+5V) through pull up resistors

 The device must be able to sense the logic level on these pins  No fixed length of transfer

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I2C Electrical Aspects I2C Bus Characteristics (cont’d)

 True multi-master capability

 Clock synchronization
 Arbitration procedure
 Transmission speeds up to 100Khz
(classic I2C)
 Max. line capacitance of 400pF,
approximately 4 meters (12 feet)
 Allows series resistor for IC protection
 Compatible with different IC technologies
• I2C devices are wire ANDed together.
• If any single node writes a zero, the entire line is zero

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 27-09-2018

I2C Bus Characteristics/ Protocol I2C Bus Characteristics/ Protocol

 Transfers are byte oriented, msb first  Slave: (can be RX only or both Tx and Rx)
 Master: (can be Tx only or both Tx and Rx)
 Start: SDA goes low while SCL is high
 Initiates a transfer by generating
 Master sends address of slave (7-bits) on next 7 clocks start and stop conditions  Responds only when addressed
 Master sends read/write request bit  Generates the clock  Timing is controlled by the clock
 0-write to slave  Transmits the slave address line
 1-read from slave  Determines data transfer direction
 Slave ACKs by pulling SDA low on next clock
 Data transfers Now commence Start and Stop Conditions
A transition of the data line while the clock line is high is defined as either
a start or a stop condition.
Both start and stop conditions are generated by the bus master
The bus is considered busy after a start condition, until a stop condition
occurs
SDA SDA

SCL SCL
Start Stop
Dr Binu paul , EMB 9 of 40 Condition Dr Binu paul , EMB Condition 10 of 40

Transfer on the I2C Bus I2C Addressing

 In normal data transfer, the data line only changes  Each node has a unique 7 (or 10) bit address
state when the clock is low
 Peripherals often have fixed and programmable
address portions
 Addresses starting with 0000 or 1111 have
special functions:-
SDA
 0000000 Is a General Call Address
 0000001 Is a Null (CBUS) Address
SCL  1111XXX Address Extension
Data line stable;
Data valid
Change
of data
 1111111 Address Extension – Next Bytes are the Actual
allowed Address

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 27-09-2018

First Byte in Data Transfer on the I2C Bus Acknowledgements

MSB LSB  Receivers (Master/slave) pull data line low for one clock pulse
after reception of a byte
R / Wr  Master receiver leaves SDA high after receipt of the last byte
requested
ACK
7 – Bit Slave Address  Slave receiver leaves SDA high on the byte following the last byte it
can accept

R / Wr 0 – Slave written to by Master Transmitter releases

SDA line during 9th clock
1 – Slave read by Master
pulse.

ACK – Generated by the slave whose address has been output. Acknowledgement
from receiver

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Data Formats Data Formats

Master reading from a Slave :
Master writing to a Slave Master is Receiver of data and Slave is Transmitter of data.

A A A A A A

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 27-09-2018

To summarise [the most important slide]

 Two simple rules dictate how to operate :
I2C – Why?
 When the SCL line is low, and only at this time, the SDA line can change.
 When the SCL line is high, the SDA line status indicates the value of a bit.
 Two exceptions to rule 1 create special conditions that are used to delimit the  At any time the electrical power is turned off, the
beginning and end of each transaction between two devices on the bus.
When SCL is high: Microcontroller will start from initial state after
 A START condition is indicated by the SDA line changing from high to low power is turned on, losing all intermediate states.
 A STOP condition is indicated by the SDA line changing from low to high

 To avoid this problem a Serial EEPROM is

interfaced to the microcontroller via I2C serial BUS.
PIC24 I2C Peripheral
Clock (SCL)
I2C interface

(Master) Data (SDA) (Slave)

 This is a two wire bus using a protocol to transfer
data between microcontroller and serial memory
and save the status of process event sequentially

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Available I2C Devices Available I2C Devices

A few examples of devices using the I2C interface :
 General Purpose Input/Output (GPIO) Expanders and LED
 1Mbit Serial EEPROMS: 24xx1025 Display Control: Servers, keyboard interface, expanders, mouse
 18-bit delta sigma ADCs: MCP3421 track balls, remote transducers, LED drive, interrupt output, drive
relays, switch input
 16-bit delta sigma ADCs: MCP3425
 Multiplexer & Switch: Telecom, automotive instrument driver
 12-bit SAR ADCs:MCP3221 clusters, metering systems, POS terminals, portable items,
 12-bit D/A: MCP4725 consumer electronics
 Serial RAM/ EEPROM: Scratch pad/ parameter storage
 Integrated Temperature Sensor (+/-0.5C): MCP9803
 Temperature & Voltage Monitor: Telecom, metering systems,
 I/O Expander 8/16-bit: MCP23016/MCP2308 portable items, PC, servers
 Voltage Level Translator: Telecom, servers, PC, portable items,
consumer electronics

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 27-09-2018

End use Example – EEPROM (Part 24WC32)

 Telecom: Mobile phones, Base stations, Switching, Routers  400 KHz I2C Bus Compatible*  Write Protection– Entire
 Data processing: Laptop, Desktop, Workstation, Server  1.8 to 6 Volt Read and Write Array Protected When WP
Operation at VIH
 Instrumentation: Portable instrumentation, Metering systems  1,000,000 Program/Erase
 Cascadable for up to Eight
 Automotive: Dashboard, Infotainment Devices Cycles
 32-Byte Page Write Buffer  100 Year Data Retention
 Consumer: Audio/video systems, Consumer electronics (DVD, TV
etc.)  Self-Timed Write Cycle with Auto-
Clear
Applications  Zero Standby Current
 Commercial, Industrial and
Automotive Temperature Ranges
 There are some specific applications for certain types of I2C devices
such as TV or radio tuners, but in most cases a general purpose I2C
device can be used in many different applications because of its
simple construction.

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24WC32 Characteristics Writing a Single Data Byte

 32KBit memory organise as 4K x 8bit
 12 address bits (2^12 = 4K)
 Device Address :

 Writing
 Byte Write
 Page Write
 Write time 10mS maximum
 Write acknowledge Polling After the STOP bit is receive the device internally programs
 Reading the EEPROM with the received data byte.
 Immediate/Current address reading The programming can take up to 10ms (max.). The device
 Selective/Random Read will be busy during this period and will not respond to its
 Sequential Read slave address.

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SPI - Serial Peripheral Interface

SPI - Serial Peripheral Interface

 Developed by Motorola
Also known as MicroWire (National Semiconductor),
QSPI (Queued)
 Simple, 3 wire, full duplex, synchronous serial data transfer
interface
 Interfaces to many devices, even many non-SPI peripherals
 Can be a master or slave interface
 Primarily used for serial communication between a host processor
and peripherals.
 Can also connect 2 processors via SPI
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SPI Serial Peripheral Interface SPI Configurations

 Simple, 3 wire, full duplex, synchronous serial data transfer

 Serial Clocks (SCK), Serial Data In (SDI) and Serial Data Out( SDO)  Multiple Independent Slave  Multiple slave cascaded
 Chip Select lines (CS) - number of slaves depends on the number of Configuration Configuration
chip select lines of the master.  All slave SDI tied to master  Slave1 SDO cascaded to
 Master sends out clocks and chip selects. Activates the slaves it wants SDO Slave 2 SDI
to communicate with  All slave SDO tied to master  All slaves have same Chip
SDI select
 Synchronous operation- latch on rising or falling edge of clock  For the slaves that are not
 SDI on rising edge, SDO on falling edge being talked to, the SDO
 Operates in 1 to 70 MHz range goes to a Hi Z state
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SPI protocol
SPI Module

The data transfer using SPI can be considered as a large shift register
4 interface pins:
3 registers:
-MOSI master out slave in shared between master and slaves.
-SPCR control register
-MIOS master in slave out Data is clocked IN at the same time as it is clocked OUT of the devices-
-SPSR status register
-SCK serial clock
-SPDR data register the CLK being shared
-SS_n slave select –Active low
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Tx and Rx has Buffers also

SPI Protocol SPI protocol *

 So SPI protocol is like a RING counter type Buffer

 Whenever the MASTER sends a byte to SLAVE , SLAVE sends one back - swapping
bits either way on every clk.. FULL DUPLEX

 If shift registers are 8 bit long, after 8 clocks the data in Master and Slave gets
exchanged

 SO On every SCK, Master sends a bit on MOSI line (SDO) and slaves reads it & SLAVE

 Data is shifted OUT of the master's MOSI (SDO) pin and IN through its MISO sends a bit on MISO line and Master reads it

(SDI) pin

 Data transfer is initiated by simply writing data to the SPI data register.

 All data movement is coordinated by SCK.

 Slave select from master is connected to chip select of slaves-

 Unselected slave’s SDO and SDI will be in High Z

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Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI)

SPI Status Register (SPSR)
SPI Control Register (SPCR)

reserved bits
interrupt enable: if set, interrupt interrupt flag: set when serial
occurs when SPI interrupt flag transfer is complete
(in SPSR) clock rate
and global interrupt enable are set write collision: set if SPDR is
spi enable: if set, SPI interface written during a receive transfer
is enabled SPI2X SPR1 SPR0 SCLK 2x clock rate: if set, doubles
0 0 0 fosc/4 clock rate in master mode
data order: if set, LSB is 0 0 1 fosc/16
transmitted first 0 1 0 fosc/64 SPI Data Register (SPDR)
master/slave select: if set, 0 1 1 fosc/128
SPI in master mode 1 0 0 fosc/2
clock polarity: 1 0 1 fosc/8
'0' SCK low in idle 1 1 0 fosc/32
'1' SCK high in idle 1 1 1 fosc/64 SPDR is a read/write register used for data transfer. Writing to SPDR sends data
clock phase: out MOSI. Reading from SPDR gets the data that was clocked into MISO.
'0' leading edge sample, trailing edge setup
'1' leading edge setup, trailing edge sample 33 of 40 34 of 40
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SPI – to summarise Available SPI Devices

 The data transfer using SPI can be considered as a large shift A few examples of devices using the I2C interface :
register shared between master and slaves.  Atmel: EEPROM, digital POTs
 Data is clocked IN at the same time as it is clocked OUT of the  Texas Instruments /MAXIM : DSP, ADC, DAC
devices- the CLK being shared  Infineon: Pressure sensors, Humidity sensors
 Tx and Rx has Buffers also  National Semiconductors: Integrated Temperature
Sensor
 Works best for single slave
 MOTOROLA 6812: SPI built in
 Clock upto 70 MHz  Intel 8051 some models have SPI also builtin
 ARM, PIC, etc have SPI: EEPROM , flash memory, LCD drivers,
serial ADC etc also have SPI

 Faster than I2C but no acknowledge signal

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SPI vs I2C SPI – Example Secure Digital memory card to PIC

SPI I2C

Max bit rate :10 Mbits/s 1 Mbits/s

Max Bus size: Ltd to no of CS pins 128 devices theoretically

No of pins: 3+n*CS 2

3 bus lines: SDI,SDO,SCK, CS - optional 2 bus lines SDA, SCL

Upto 10 MHz supported – high date rate Low data rate support

Good for single master, single slave – short Efficient for multimaster multislave models –
distance short distance
Less over head for point to point transfer More overhead

NO acknowledgement ACK present

No built in address Every device has a address

Simple, low cost, high speed Small pin count, slow

Best suited for data flow applications Suited best for communication on board

Ex: Serial EEPROMS, ADC, Ethernet Serial EEPROMS, Temperature sensors

controllers
Synchronous Synchronous
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 What are some real world applications of

CAN?
 Controller Area Networks are used in many different
fields, the bulk of which are
 Auto-motive industry
CAN –Controller Area Network  Factory Automation
 Machine Control
 Medical Equipment and devices
 And more….

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 27-09-2018

What is CANBUS? Message Oriented Transmission Protocol

CANBUS or CAN bus – Controller Area Network bus  Each node – receiver & transmitter
 A sender of information transmits to all devices on the bus
 All nodes read message, then decide if it is relevant to them
An automotive serial bus system developed to satisfy
 All nodes verify reception was error-free
the following requirements:  All nodes acknowledge reception
 Network multiple microcontrollers with 1 pair of wires.

 Allow microcontrollers communicate with each other.

 High speed, real-time communication.

 Provide noise immunity in an electrically noisy environment.

 Low cost

 Message oriented communication CAN bus © 2005 Microchip Technology Incorporated. All Rights Reserved.

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The Development of CAN CANBUS CANBUS

History Timeline
The development of CAN began when more and more electronic  First idea - The idea of CAN was  1983 : First CANBUS project at Bosch
devices were implemented into modern motor vehicles. Examples of first conceived by engineers at  1986 : CAN protocol introduced
such devices include engine management systems, active suspension, Robert Bosch Gmbh in Germany
 1987 : First CAN controller chips sold
ABS, gear control, lighting control, air conditioning, airbags and central in the early 1980s.
locking. All this means more safety and more comfort for the driver and  Early focus - develop a  1991 : CAN 2.0A specification
of course a reduction of fuel consumption and exhaust emissions. communication system between published
a number of ECUs (electronic  1992 : Mercedes-Benz used CAN
To improve the behavior of the vehicle even further, it was necessary for control units).
the different control systems (and their sensors) to exchange network
 New standard - none of the
information. This was usually done by discrete interconnection of the communication protocols at that  1993 : ISO 11898 standard
different systems (i.e. point to point wiring). The requirement for time met the specific  1995 : ISO 11898 amendment
information exchange has then grown to such an extent that a cable requirements for speed and
network with a length of up to several miles and many connectors was  Present : The majority of vehicles use
reliability so the engineers
required. This produced growing problems concerning material cost, developed their own standard. CAN bus.
production time and reliability.

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Before CAN  CAN - features  Multi-Master Protocol

 Serial communication  All devices on the network
 CSMA/CD/NDA receive every bit of information
 Carrier Sense Multiple Access/Collision
Detection with Non-Destructive Arbitration (
sent on the BUS
resend if error detedcted)  Compact
 Upto 1 Megabit per second  Twisted Pair Bus line with 120
 Common baud rates: 1 MHz, Ohm terminations
500 KHz and 125 KHz  Robust in noisy environments
 All nodes – same baud rate
CAN   Max length:120 ft to 15000 ft
• point-to-point wiring is (rate dependent)
replaced by one serial
 Maximum speed decided by 2 x tpd
bus connecting all
control systems. tpd = propagation delay of electrical
• CAN-specific hardware medium (wire)
to each control unit that
provides the "rules" or
the protocol for
transmitting and CAN Bus Length
receiving information via
the bus.
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CANBUS follows the OSI (open system Identification) Model

A Basic CAN controller
 Physical and Data Link layers in silicon.

DSP or Application Layer

microcontroller Data Logic Link
Embedded CAN Link control
controller Layer
Medium Access

CAN Transceiver Physic Physical

al Signalling
Layer Physical medium

 Cheap CAN controller – CPU could get overrun with CAN Bus line Interface
messages even if it didn’t need them. Basic Configuration
 Newer version use hardware filters to reorganise the Application layer: interacts with operating system or with CAN device
Data Link layer : involved in actual data transfer as per the protocol.. like
received data Send/receive/validate etc
Physical layer : denotes the required hardware
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Message Oriented Transmission Protocol The CAN Standard - message types

 Each node – receiver & transmitter
 A sender of information transmits to all devices on the bus  The CAN standard defines four message types
 All nodes read message, then decide if it is relevant to them  Data Frame – the predominantly used message type
 All nodes verify reception was error-free
 Remote Frame
 Error Frame
 All nodes acknowledge reception
 Overload Frame
 The CAN standard also defines an elaborate scheme for error
handling and confinement.
 CAN -number of different connector types in use.

CAN bus © 2005 Microchip Technology Incorporated. All Rights Reserved.

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CAN – Data frame message Format CAN Data frame Message Format
 Each message has an ID(11 bit or 29 bit) , Data and
overhead.
 The physical layer uses differential transmission on a twisted
 Data –8 bytes max
pair wire. The bus uses Non-Return To Zero (NRZ) with bit-
 Overhead – start, end, CRC, ACK
stuffing (see bit encoding slide)

 Max. transfer rate of 1000 kilobits per second at a maximum

bus length of 40 meters or 130 feet when using a twisted wire
pair which is the most common bus medium used for CAN.

 Message length is short with a maximum of 8 data bytes per

message

 The messages are protected by a CRC type checksum

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Message Format – with standard identifier CAN - Data frame Message Format - continued
Field name Length(bits) Purpose

Start-of-frame 1 Denotes the start of frame transmission

Identifier 11 A (unique) identifier for the data
 Identifier: (ID) denotes priority of
Remote transmission request (RTR) 1 Must be dominant (0)
message also-
Identifier extension bit (IDE) 1 Must be dominant (0)
 lower the value - higher priority
Reserved bit (it must be set to dominant (0), but accepted as  Wired AND connection between
Reserved bit (r0) 1 either dominant or recessive) nodes
Data length code (DLC) 4 Number of bytes of data (0-8 bytes)
 Has priority information and
Data field 0-8 bytes Data to be transmitted (length dictated by DLC field) arbitration information
CRC 15 Cyclic redundancy check
CRC delimiter 1 Must be recessive (1)

Transmitter sends recessive (1) and any receiver can assert a  RTR: “1” when information is
ACK slot 1 dominant (0)
ACK delimiter 1 Must be recessive (1)
needed from another node. But
End-of-frame (EOF) 7 Must be recessive (1) only that node whose identifier
matches takes the data

Other message types discussed later 

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Bus Characteristics – Wired AND Basic Bit Encoding

Only if all nodes transmit recessive If any one node transmits a dominant
bits (ones), the Bus is in the recessive bit (zero), the bus is in the dominant
state. state.

T is Transmitter, R is receiver. Note nodes can therefore check the line

while transmitting. This is important particularly during arbitration.

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Bus Arbitration – what? Bus Arbitration - how?

 Message importance is encoded in message ID.
 Arbitration – needed when multiple nodes try to transmit at the same Lower value = More important
time
 Only one transmitter is allowed to transmit at a time.
 As a node transmits each bit, it verifies that it sees the same bit
value on the bus that it transmitted.
 A node waits for bus to become idle
 Nodes with more important messages continue transmitting  A “0” on the bus wins over a “1” on the bus.
 Losing node stops transmitting, winner continues.

© 2005 Microchip Technology Incorporated. All Rights Reserved.

CAN bus
Bit-wise arbitration to control access to the bus, and each message is tagged
with a priority. (the one that sends a “0” bit first as its identifier, after start of frame
Dr Binu paul , EMB 57 of 40 wins the bus) Dr Binu paul , EMB 58 of 40

CAN Bus Overview Basic Bit Encoding

 The bus access is via the advanced serial communications
protocol Carrier Sense Multiple Access/Collision Detection
with Non-Destructive Arbitration. (CSMA/CD/NDA)
 collision of messages is avoided by bitwise arbitration without loss
of time.
 no explicit address in the messages, instead, each message
carries a numeric value which controls its priority on the bus,
and also serve as an identification of the contents of the
message.
 An elaborate error handling scheme that results in
retransmitted messages when they are not properly received.
6 concecutive bits same – error alert ( see bit encoding
format slide )

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The CAN Standard - message types The CAN Standard - message types
 The CAN standard defines four message types
(Data,Remote,Error,Overload frames)  Overload Frame
 Data Frame – the predominantly used message type (discussed earlier)  It is very similar to the Error Frame with regard to the format and it is
 Remote Frame transmitted by a node that becomes too busy.
 The Remote Frame is just like the Data Frame, with two important differences:  At present obsolete
 the RTR bit in the Arbitration Field is recessive value “1”  Today's CAN controllers are clever enough not to use it
 there is no Data Field.
 The CAN standard also defines an elaborate scheme for error
 Error Frame
handling and confinement.
 Error Frame is a special message that violates the framing rules of a CAN
message  CAN -number of different connector types in use.
 The Error Frame consists of an Error Flag, which is 6 bits of the same value
(thus violating the bit-stuffing rule) and an Error Delimiter, which is 8 recessive
bits( “1”)

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Advantages of CAN Comparison of Serial Interfaces

 Reduced wire looming as control is distributed

 Mst CAN chip come with data link and physical layers
built in ( in silicon). So Embedded system developer
need to develop only the application code to support
this Bus
 Good for electrically noisy environment because of
differential signalling
 Collision detection and Traffic congestion Avoidance is
in built
 Error free- as each node check for errors during
transmission with error frame being sent to alert all
nodes in case any node sense an error
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END of presentation
1. The Data Frame
 Summary: "Hello everyone, here's some data
labeled X, hope you like it!"
 The Data Frame is the most common message type.
 It has
 the Arbitration Field, which determines the priority of the message when
two or more nodes are contending for the bus. The Arbitration Field
contains:
 For CAN 2.0A, an 11-bit Identifier and one bit, the RTR bit, which is dominant
for data frames.
 For CAN 2.0B, a 29-bit Identifier (which also contains two recessive bits: SRR
and IDE) and the RTR bit.
 the Data Field, which contains zero to eight bytes of data.
 the CRC Field, which contains a 15-bit checksum calculated on most
parts of the message. This checksum is used for error detection.
 an Acknowledgement Slot; any CAN controller that has been able to
correctly receive the message sends an Acknowledgement bit at the end
of each message. The transmitter checks for the presence of the
Acknowledge bit and retransmits the message if no acknowledge was
detected.
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CAN Data Frames 2. The Remote Frame

Note 1: It is worth noting that the presence of an Acknowledgement Bit on the bus does not  Summary: "Hello everyone, can somebody please
mean that any of the intended addressees has received the message. The only thing we know produce the data labeled X?"
is that one or more nodes on the bus has received it correctly
Note 2: The Identifier in the Arbitration Field is not, despite of its name, necessarily identifying
the contents of the message.  The Remote Frame is just like the Data Frame, with two important
 CAN 2.0A (“standard CAN” 11-bit ID) Data Frame. differences:
 It is explicitly marked as a Remote Frame (the RTR bit in the Arbitration Field
is recessive), and
 there is no Data Field.
 The intended purpose of the Remote Frame is to solicit the transmission
of the corresponding Data Frame. If, say, node A transmits a Remote
Frame with the Arbitration Field set to 234, then node B, if properly
initialized, might respond with a Data Frame with the Arbitration Field also
 CAN 2.0B (“extended CAN” 29-bit ID) Data Frame. set to 234.
 Remote Frames can be used to implement a type of request-response
type of bus traffic management. In practice, however, the Remote Frame
is little used. It is also worth noting that the CAN standard does not
prescribe the behaviour outlined here. Most CAN controllers can be
programmed either to automatically respond to a Remote Frame, or to
notify the local CPU instead.

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Remote Frame (contd.) 3. The Error Frame

 There's one catch with the Remote Frame: the Data Length Summary: (everyone, aloud) "OH DEAR, LET'S TRY AGAIN"
Code must be set to the length of the expected response
Simply put, the Error Frame is a special message that violates the framing
message. Otherwise the arbitration will not work. rules of a CAN message. It is transmitted when a node detects a fault and will
cause all other nodes to detect a fault - so they will send Error Frames, too.
 Sometimes it is claimed that the node responding to the The transmitter will then automatically try to retransmit the message. There is
Remote Frame is starting its transmission as soon as the an elaborate scheme of error counters that ensures that a node can't destroy
identifier is recognized, thereby "filling up" the empty the bus traffic by repeatedly transmitting Error Frames.
Remote Frame. This is not the case. The Error Frame consists of an Error Flag, The Error Frame
which is 6 bits of the same value (thus violating
 A Remote Frame (2.0A type): the bit-stuffing rule) and an Error Delimiter,
which is 8 recessive bits. The Error Delimiter
provides some space in which the other nodes
on the bus can send their Error Flags when they
detect the first Error Flag.

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4 The Overload Frame

Summary: "I'm a very busy little 82526 device, could you
please wait for a moment?"
 The Overload Frame is mentioned here just for
completeness. It is very similar to the Error Frame with regard
to the format and it is transmitted by a node that becomes too
busy. The Overload Frame is not used very often, as today's
CAN controllers are clever enough not to use it. In fact, the
only controller that will generate Overload Frames is the now
obsolete 82526

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MODULE 2
EMBEDDED SYSTEMS
General Information
• Unlike, pic microcontroller, Arduino and avr microcontroller, 8051 microcontroller do not have
built in ADC. If we want to interface any sensor with 8051 microcontroller, we have to use external
ADC.
Eg: You want to measure temperature with 8051 microcontroller and you are using LM35
temperature sensor to measure temperature. LM35 temperature sensor gives output in the form of
analog voltage. So we need to use analog to digital converter.

• We use Analogue to digital convertor (ADC) to convert the analogue signal into digital form.
Analogue signal can be the output of some sensor. And then the data in digital format can then be
used for further processing by the digital processors.

03-11-2020 Gayathri R Embedded Systems 2

FEATURES OF ADC 0804:

• 8 bit resolution
• Differential analogue voltage inputs
• 0-5V input voltage range
• No zero adjustment
• Built-in clock generator
• Voltage at Vref/2 (pin9) can be externally adjusted to convert smaller input voltage
spans to full 8 bit resolution.

03-11-2020 Gayathri R Embedded Systems 3

RESOLUTION:
Resolution refers to the conversion of an analog voltage to a digital value. It
indicates the number of discrete values that an ADC can produce over the range of
analog values. The values are usually stored electronically in binary form, so the
resolution is usually expressed in bits.
STEP SIZE:
It is the voltage difference between one digital level and the next level that can be
measured by ADC. If ADC has higher resolution, it gives smaller step size. If ADC
has 8 bit resolution, input voltage span is 0-5V and the step size is 19.53mV
(5V/255).

03-11-2020 Gayathri R Embedded Systems 4

Pin Diagram
• CS: Chip Select
It is an active low pin and is used to activate ADC0804.
• RD: Read
It is an input pin and is active low. ADC stores the result in
an internal register after conversion of analog data. This pin
helps to get the data out of the ADC0804.When CS=0, high
to low pulse is given to RD pin, then digital output comes on
the pins D0-D7.
• WR :Write
It is an input pin and is active low which is used to initiate
the ADC to start the conversion process. When CS=0, WR
makes a low to high transition, then ADC starts the
conversion process.
• CLK IN : Clock In
This is an input pin which is connected to an external clock
source.
03-11-2020 Gayathri R Embedded Systems 5
Pin Diagram
• INTR: Interrupt
This is an output pin and is active low. When the
conversion is over, this pin goes low.
• Vin+: Analog Input
Analog input to ADC.
• Vin-: Analog Input
Analog input connected to ground.
• AGND: Analog Ground
Connected to ground.
• Vref/2:Reference Voltage
• Used to set the reference voltage. Default reference
voltage is 5V when not connected. Step size can be
reduced by using this pin.

03-11-2020 Gayathri R Embedded Systems 6

Pin Diagram
• DGND: Digital Ground
Connected to ground.
• D7-D0:OutputData Bits
Output bits of binary data.
• CLKR: Clock Reset
To reset the clock.
• Vcc: Positive Supply
Power supply of ADC.

03-11-2020 Gayathri R Embedded Systems 7

The voltage Vref
• The voltage at Vref/2 (pin9) of Vref/2 Input voltage Step size (mV)
ADC0804 can be externally (pin9) (volts) span (volts)
adjusted to convert smaller input
voltage spans to full 8 bit resolution. Left open 0–5 5/255 = 19.6
Vref/2 (pin9) left open means input 2 0–4 4/255 = 15.69
voltage span is 0-5V and step size is
5/255=19.6V. Have a look at the table 1.5 0–3 3/255 = 11.76
below for different Vref/2 voltages and
1.28 0 – 2.56 2.56/255 =
corresponding analogue input voltage
10.04
spans.
1.0 0–2 2/255 = 7.84

0.5 0–1 1/255 = 3.92

03-11-2020 Gayathri R Embedded Systems 8

Conversion Process

Steps for converting the analog input and reading the output from ADC0804.

• Make CS=0 and send a low to high pulse to WR pin to start the conversion.
• Now keep checking the INTR pin. INTR will be 1 if conversion is not finished
and INTR will be 0 if conversion is finished.
• If conversion is not finished (INTR=1) , poll until it is finished.
• If conversion is finished (INTR=0), go to the next step.
• Make CS=0 and send a high to low pulse to RD pin to read the data from the
ADC.

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Circuit Diagram

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Program
ORG 00H
MOV P1,#11111111B // initiates P1 as the input port
MAIN: CLR P3.7 // makes CS=0
SETB P3.6 // makes RD high
CLR P3.5 // makes WR low
SETB P3.5 // low to high pulse to WR for starting conversion
WAIT: JB P3.4,WAIT // polls until INTR=0
CLR P3.7 // ensures CS=0
CLR P3.6 // high to low pulse to RD for reading the data from ADC
MOV A,P1 // moves the digital data to accumulator
CPL A // complements the digital data
MOV P0,A // outputs the data to P0 for the LEDs
SJMP MAIN // jumps back to the MAIN program
END
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Introduction to DAC

where, Iref=Reference current=2mA

D7 = MSB bit
D0=LSB bit
How to convert Iout to voltage in DAC0808?
DAC gives output in the form of cureent, so outside of the DAC current(I) to voltage(V)
converter is connected, which is then provided to oscilloscope.

Interfacing
Algorithm and Flowchart
Interfacing Diagram

1 DAC interfacing with 8051 microcontroller

Assembly Language Programs

Program: Write an ALP to generate Square wave form on port P1 of 8051
microcontroller using DAC.
 Flowchart for Square Wave generation using DAC

Square Wave Generation using DAC

ORG 0000h
mov P1,#00H
repeat:Acall squarwave
sjmp repeat
squarwave:mov P1,#FFH
Acall delay
mov P1,#00H
Acall delay
ret
delay:mov r0,#20
up2:mov r1,#250
up1:mov r2,#250
Here:djnz r2,Here
djnz r1,up1
djnz r0,up2
ret
END

Program: Write an ALP to generate Triangular wave form on port P1 of 8051

microcontroller using DAC.
 Flowchart for Tringular Wave Generation using DAC
ORG 0000h
mov P1,#00H
repeat:Acall triwave; generate triangular wave
sjmp repeat
triwave:mov A,#00H
INCR:mov P1,A
INC A
CJNE A,#0FFH,INCR
DECR:mov P1,A
DEC A
CJNE A,#00H,DECR
ret
END
Program: Write an ALP to generate Stair-case wave form (with 5-steps) on port P1 of
8051 microcontroller using DAC.
Solution:- As we need 5-Step staircase waveform.Hence Accumulator can have
maximum value of 255 hence to get 5 steps initial value to be added is 51H
ORG 0000h
mov P1,#00H
repeat:Acall stair_case_wave; generate staircase wave
sjmp repeat
stair_case_wave:mov A,#00H
mov P1,A
Acall delay
Back:ADD A,#51H
mov P1,A
Acall delay
CJNE A,#0FFH,Back
SJMP stair_case_wave
delay:mov r0,#20
up2:mov r1,#250
up1: mov r2,#250
here:djnz r2,here
djnz r1,up1
djnz r0,up2
ret
END