SVCE TIRUPATI

COURSE MATERIAL

SUBJECT VLSI DESIGN (EC20APC603)

UNIT 1

COURSE B.TECH

DEPARTMENT ECE

SEMESTER 32

PREPARED BY
Dr. G. Sujatha
(Faculty Name/s) Professor

Version V-2

PREPARED / REVISED DATE 16-03-2023

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SVCE TIRUPATI

TABLE OF CONENTS – UNIT 1

S. NO CONTENTS PAGE NO.
1 COURSE OBJECTIVES 3
2 PREREQUISITES 3
3 SYLLABUS 4
4 COURSE OUTCOMES 4
5 CO - PO/PSO MAPPING 5
6 LESSON PLAN 5
7 ACTIVITY BASED LEARNING 6
8 LECTURE NOTES 7
1.1 INTRODUCTION (VLSI DESIGN FLOW) 6
1.2 IC era 9
1.3 BASIC MOS TRANSISTORS- ENHANCEMENT MODE AND 21
DEPLETION MODE TRANSISTOR ACTION
1.4 FABRICATION PROCESS: NMOS FABRICATION 26
1.5 FABRICATION PROCESS: CMOS FABRICATION 28
1.6 IDS VERSUS VDS RELATIONSHIPS 33
1.7 ASPECTS OF MOS TRANSISTOR THRESHOLD VOLTAGE 38
1.8 MOS TRANSISTOR TRANSCONDUCTANCE, OUTPUT 40
CONDUCTANCE AND FIGURE OF MERIT
9 PRACTICE QUIZ 42

10 ASSIGNMENTS 44

11 PART A QUESTIONS & ANSWERS (2 MARKS QUESTIONS) 45

12 PART B QUESTIONS 47

13 SUPPORTIVE ONLINE CERTIFICATION COURSES 48

14 REAL TIME APPLICATIONS 48

15 CONTENTS BEYOND THE SYLLABUS 48

16 PRESCRIBED TEXT BOOKS & REFERENCE BOOKS 49

17 MINI PROJECT SUGGESTION 49

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SVCE TIRUPATI

Course Objectives

The objectives of this course is to

1. Learn about the various processing steps involved in the fabrication of a Nmos,
Pmos AND CMOS transistors..

2. To Analyze the Ids Versus Vds Relationship.

2. Prerequisites

Students should have knowledge on

1. Digital Logic Design

2. Electronic Devices & Circuits

3. Fundamentals of electronic circuits

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3. Syllabus

UNIT I

IC era,Basic Mos transistrors- Enhancement mode and Depletion mode trasitor

action, NMOS farication, CMOS fabricaton- p-well, N-well and Twin tub process,
Thermal Aspects of processing and Bi-CMOS.Drain to source curren Ids versus Vds
Relationships, MOS Transconductance, Output Conductance and Figure of Merit.

4. Course outcomes

The outcome of this course is to

1. Understand the static and dynamic behaviour of MOSFETs (Metal Oxide

Semiconductor Field Effect Transistors) and the secondary effects of the MOS
transistor model.

2. Design digital systems using MOS circuits (Static and Switching characteristics
of inverters)

3. Implement Fabrication steps.

4. Approach the concept behind ASIC (Application Specific Integrated Circuits)

design and the different implementation approaches used in industry Explain
the principles of design of Jigs and fixtures, Types of clamping & work holding
devices and latest UBMTS.

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5. CO-PO / PSO Mapping

COs/
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PSO1 PSO2
POs

CO1
2 3
3

CO2 3 3 3

CO3
3
3

C04
3 3 3
3

6. Lesson Plan
Lecture No. Weeks Topics to be covered References

1.1 Introduction (VLSI Design flow) T1, R1

1.2 IC era T1, R1

1.3 1 Mos transistrors- Enhancement mode and Depletion T1, R1

mode trasitor action

1.4 NMOS farication T1, R1

1.5 CMOS fabricaton- p-well, N-well and Twin tub T1, R1

process
1.6 IDS VERSUS Vds Relationships T1, R1

1.7 Aspects of MOS transistor Threshold Voltage T1, R2

1.8 Mos Transistor Trans Output Conductance and Figure of T1, R1

Merit
2

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 7. Activity Based Learning

1. Analyze various methods in fabrication.

2. Understand the concepts of MOS Transistors

8. Lecture Notes

1.1 INTRODUCTION

VLSI DESIGN FLOW

The chip design includes different types of processing steps to finish the
entire flow. For anyone, who just started his career in VLSI industry has to
understand all the steps of the VLSI design flow. Each and every step of
the VLSI design flow has a dedicated EDA tool that covers all the
aspects related to the specific task perfectly. All the EDA tools can
import and export the different file types to help making a flexible VLSI
design flow that uses multiple tools from different vendors. The VLSI
design flow is shown in the figure below.

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 Fig 1.1: VLSI Design flow
1.1.1 System Specification
The first step of VLSI Design Flow is system specifications. System
specification is a high level representation of the system. The factors to be
considered in this process include performance, functionality and
interface.
1.1.1 Architectural Design
This is step where main work starts with the help of system
specification. Design engineer design the architecture according to
system specification.
1.1.3 Functional and Logic Design

In this step functionality of design are identified. It specify the

hardware implementation of system functionality. The outcome of
functional design is usually a timing diagram. In logic design step, register
allocation, logic and arithmetic operations of the design that represent the
functional design are derived and tested this description is called RTL
description. RTL stands for register transfer level. In this step, system
specification is expressed in hardware description language (HDL) such as
Verilog and VHDL. RTL description is used for simulation to test the
functionality with the help of EDA tools.
Functional verification is performed to ensure the RTL design is done
according to the specifications.RTL code is converted to gate level net list
using synthesis tools. Net list is a description of the circuit in terms of gates
and connections between them. To verify whether the synthesis tool has
correctly generated the gate-level net list verification should be done.

1.1.4 Circuit Design

In this step circuit is designed based on the logic design. The Boolean
expressions are converted into circuit representation by taking into
consideration the power and speed requirement of original design. Circuit
simulation is used to verify the correctness and timing of each component.
Diagram consists circuit elements such as gates and transistors.

1.1.5 Physical Design

In this step the net list is converted into physical
geometric representation. Layout is representation of an IC in terms of
planar geometric shapes which correspond to the patterns of metal

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 oxide or semiconductor layers that make up the components of the
Integrated circuit. Layout is designed by EDA tool such as cadence
virtuoso.
Physical design is a very complex step therefore it is divided into sub
steps such as floor planning, placement, clock tree synthesis, routing etc
and timing analysis checks are formed in each and every step during
physical design. Floor planning which is a process of placing the various
blocks and the I/O pads across the chip area based on the design
constraints. Placement of physical elements within each block and
integration of analog blocks or external IP cores is performed. When all
the elements are placed, a global and detailed routing is running to
connect all the elements together. Output of layout is GDSII file which is
given to the foundry to fabricate the chip. The layout should be done
according to foundry design rules.
1.1.6 Physical Verification and Signoff
In this step we perform physical verification checks such ass Layout Vs
schematic (LVS) and Design Rule check (DRC).DRC verifies whether the
given layout satisfies the design rules provided by the fabrication team.
DRC checks are nothing but physical checks of spacing rules between
metals, minimum width rules, via rules etc.LVS is a major check in the
physical verification stage. Layout is compared with the schematic for
verifying whether their functionally match or not. If match, then the LVS
reports clean.
1.1.7 Fabrication
After physical verification step the design is ready for fabrication. Tape
out is the final result of the design process for integrated circuits before
they are sent for manufacturing. The tape-out is specifically the point at
which the graphic for photo mask of the circuit is sent to foundry.
Fabrication process consists of several steps involving wafer growth,
epitaxial growth masking, etching, doping, deposition, and diffusion of
various materials on the wafer. During each step one mask is used.
1.1.8 Packaging and Testing
Each of the wafers contains hundreds of chips. These chips are
separated and packaged by a method called scribing and cleaving.
The chips that are failed in electrical test are discarded. Each chip is
packaged and tested to ensure that it meets all the design
specifications and functions properly.

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 1.2 INTEGRATED CIRCUIT TECHNOLOGY Era:
Machining is an essential process of finishing by which work pieces are
produced to the desired dimensions and surface finish by gradually
removing the excess material from the preformed blank in the form of
chips with the help of cutting tool(s) moved past the work surface(s).
There is no doubt that our daily lives are significantly affected by
electronic engineering technology. This is true on the domestic scene, in
our professional disciplines, in the workplace, and in leisure activities.
Indeed, even at school, tomorrow’s adults are exposed to and are
coming to terms with quite sophisticated electronic devices and
systems. There is no doubt that revolutionary changes have taken place
in a relatively short time and it is also certain that even more dramatic
advances will be made in the next decade.
Electronics as we know it today is characterized by reliability, low
power dissipation, extremely low weight and volume, and low cost,
coupled with an ability to cope easily with a high degree of
sophistication and complexity. Electronics, and in particular the
integrated circuit, has made possible the design of powerful and flexible
processors which provide highly intelligent and adaptable devices for
the user. Integrated circuit memories have provided the essential
elements to complement these processors and, together with a wide
range of logic and analog integrated circuitry, they have provided the
system designer with components of considerable capability and
extensive application. Furthermore, the revolutionary advances in
technology have not yet by any means run their full course and the
potential for future developments is exciting to say the least. Up until the
1950s electronic active device technology was dominated by the
vacuum tube and, although a measure of miniaturization and circuit
integration did take place, the technology did not lend itself to
miniaturization as we have come to accept it today. Thus the vast
majority of present-day electronics is the result of the invention of the
transistor in 1947.

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 Fig 1.2: Moore's first law: Transistors Integrated on a single chip
(commercial products).

The invention of the transistor by William B. Shockley, Walter H. Brattain

and John Bardeen of Bell Telephone Laboratories was followed by the
development of the Integrated Circuit (IC). The very first IC emerged at
the beginning of 1960 and since that time there have already been four
generations of ICs: SSI (small scale integration), MSI (medium scale
integration), LSI (large scale integration), and VLSI (very large scale
integration). Now we are beginning to see the emergence of the fifth
generation, ULSI (ultra large scale integration) which is characterized by
complexities in excess of 3 million devices on a single IC chip. Further
miniaturization is still to come and more revolutionary advances in the
application of this technology must inevitably occur.
Over the past several years, Silicon CMOS technology has
become the dominant fabrication process for relatively high
performance and cost in circuits on a single chip has grown as
indicated in Figure 1 effective VLSI circuits. The revolutionary nature of
this development is indicated by the way in which the number of
transistors integrated.2. Such progress is highlighted by recent products
such as RISC chips in which it is possible to process some 35 million
instructions per second.

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 Figure 1.3: Speed/power performance of available technologies.

In order to improve on this throughput rate it will be necessary to

improve the technology, both in terms of scaling and processing, and
through the incorporation of other enhancements such as BiCMOS.
The implication of this approach is that existing silicon technology
could effectively facilitate the tripling of rate. Beyond this, i.e., above
100 million instructions per second, one must look to other
technologies. In particular, the emerging Gallium Arsenide (GaAs)
based technology will be most significant in this area of ultra-high
speed logic/fast digital processors. GaAs also has further potential as
a result of its photo- electronic properties, both as a receiver and as a
transmitter of light. GaAs in combination with silicon will provide the
designer with some very exciting possibilities. It is most informative in
assessing the role of the currently available technologies to review
their speed and power performance domains. This has been set out
as Figure 1.3 and the potential presented by each may be readily
assessed.
This text deals mostly with silicon-based VLSI, including BiCMOS, but
also introduces GaAs-based technology. ECL-based technology is not
covered here, but much of the material given is relevant to the
general area of the design of digital integrated circuits.

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 Table 1.1: Microelectronics evolution

1.2.1 THE INTEGRATED CIRCUIT (IC) ERA

Such has been the potential of the silicon integrated circuit that
there has been an extremely rapid growth in the number of transistors
(as a measure of complexity) being integrated into circuits on a single
silicon chip. In less than three decades, this number has risen from tens
to millions as can be seen in Figure 1.1. The figure sets out what has
become known as “Moore’s first law” after predictions made by
Gordon Moore (of Intel) in the 1960s. It may be seen that his
predictions have largely come true except for an increasing
divergence between “predicted” and “actual” over the last few
years due to problems associated with the complexities involved in
designing and testing such very large circuits. Such has been the
impact of this revolutionary growth that IC technology now affects
almost every aspect of our lives. More is still to come since we have
not yet reached the limits of miniaturization and there is no doubt that
tens of millions of transistors will be readily integrated onto a single
chip in the future. This evolutionary process is reflected in Table 1.1.
Truly the 1970s, the 1980s and now the 1990s may well be described
as the integrated circuit era.

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 Basic Fabrication Processes

Present day very-large-scale integration (VLSI) technology is based on

silicon, which has bulk electrical resistance between that of a conductor and an
insulator. That is why it is known as a semiconductor material. Its conductivity can
be changed by several orders of magnitude by adding impurity atoms into the
silicon crystal lattice. These impurity materials supply either free electrons or holes.
The donor elements provide electrons and acceptor elements provide holes.
Silicon having a majority of donors is known as n-type. On the other hand, silicon
having a majority of acceptors is known as p-type. When n-type and p-type
materials are put together, a junction is formed where the silicon changes from
one type to the other type. Various semiconductor devices such as diode and
transistors are constructed by arranging these junctions in certain physical
structures and combining them with other types of physical structures, as we shall
discuss in the subsequent sections.

Wafer Fabrication

The MOS fabrication process starts with a thin wafer of silicon. The raw
material used for obtaining silicon wafer is sand or silicon dioxide. Sand is a cheap
material and it is available in abundance on earth. However, it has to be purified
to a high level by reacting with carbon and then crystallized by an epitaxial
growth process. The purified silicon is held in molten state at about 1500 °C, and
a seed crystal is slowly withdrawn after bringing in contact with the molten silicon.
The atoms of the molten silicon attached to the seed cool down and take the
crystalline structure of the seed. While forming this crystalline structure, the silicon
is lightly doped by inserting controlled quantities of a suitable doping material into
the crucible. The setup is for wafer fabrication to produce nMOS devices is shown
in Fig. 1.4a. Here, boron may be used to produce p-type impurity concentration
of 1015 cm3 to 1016 per cm3. It gives resistivity in the range of 25–2 Ω cm. After the

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 Withdrawal of the seed, an “ingot” of several centimeters length and about 8–10
cm diameter as shown in Fig. 1.4 b is obtained. The ingot is cut into slices of 0.3–0.4
mm thickness to obtain wafer for IC fabrication.

Figure 1.4 a: Set up for forming silicon ingot. b An ingot Oxidation

Silicon dioxide layers are used as an insulating separator between different

conducting layers. It also acts as mask or protective layer against diffusion and
high-energy ion implantation. The process of growing oxide layers is known as
oxidation be- cause it is performed by a chemical reaction between oxygen (dry
oxidation), or oxygen and water vapor (wet oxidation) and the silicon slice
surface in a high- temperature furnace at about 1000 °C as shown in Fig. 1.4. To
grow an oxide layer of thickness tox, the amount of silicon consumed is
approximately 0.5tox. Dry oxidation performed in O2 with a few percent of
hydrochloric acid added to produce thin, but robust oxide layers is used to form
the gate structure. These layers are known as gate oxide layers. The wet oxidation
produces a thicker and slightly porous layer. This layer is known as field oxide layer.
The oxide thickness is limited by the diffusion rate of the oxidizing agent through
the already grown layer and is about 1 µm at one atmospheric pressure, but can
be doubled by using higher pressure, say approximately 20 atm. Another
advantage of a high-pressure system is the possibility to grow thicker oxides in less
time at high temperature.

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 Figure 1.4 c: Furnace used for oxidation

Mask Generation

To create patterned layers of different materials on the wafer, masks are

used at different stages. Masks are made of either inexpensive green glass or
costly low- expansion glass plates with opaque and transparent regions created
using photo- graphic emulsion, which is cheap but easily damaged. Other
alternative materials used for creating masks are iron oxide or chromium, both of
which are more durable and give better line resolution, but are more expensive.

A mask can be generated either optically or with the help of an

electron beam. In the optical process, a reticle, which is a photographic plate
of exactly ten times the actual size of the mask, is produced as master copy of
the mask. Transparent and opaque regions are created with the help of
a pattern generator by projecting an image of the master onto the reticle.
Special masking features such as parity masks and fiducials are used on the reticle
to identify, align, and orient the mask. Master plates are generated from
reticles in a step-and- repeat process by projecting an image of the reticle ten
times reduced onto the photosensitized plate to create an array of geometrical
shapes in one over the entire plate. Fiducials are used to control the separation
between exposures and align the reticle images relative to one another. This
process has the disadvantage that if there is a defect on the reticle, it is
reproduced on all the chips. The step-and-repeat process not only is slow but also
suffers from alignment problems and defect propagation due to dust specks.
The electron beam mask generation technique overcomes these problems.

In the electron beam masking process, the masking plate is generated in

one step. It is based on the raster scan approach where all the geometrical data
are converted into a bit map of 1’s and 0’s. While scanning the masking plate in

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 a raster scan manner, squares containing 1’s are exposed and those containing
0’s are not. Exposures are made by blanking and un-blanking the beam
controlled by the bit map. Using this technique, several different chip types can
be imprinted on the same set of masks. The main disadvantage of this approach
is that it is a sequential technique. A better alternative is to use the soft X-ray
photolithographic technique in which the entire chip can be eradicated
simultaneously. This technique also gives higher resolution.

These master plates are usually not used for mask fabrication. Working
plates made from the masters by contact printing are used for fabrication. To
reduce turn- around time, specially made master plates can be used for wafer
fabrication.

Photolithography

The photolithographic technique is used to create patterned layers of

different materials on the wafer with the help of mask plates. It involves several
steps. The first step is to put a coating of photosensitive emulsion called photo-
resist on the wafer surface. After applying the emulsion on the surface, the wafer
is spun at high speed (3000 rpm) to get a very thin (0.5–1 µm) and uniform layer of
the photo-resist. Then the masking plate is placed in contact with the wafer in a
precise position and exposed to the UV light. The mask plate, with its transparent
and opaque regions, defines different areas. With negative photo-resist, the areas
of the wafer exposed to UV light are polymerized (or hardened), while with
positive photo-resist, the exposed areas are softened and removed.

The removal of the unwanted photo-resist regions is done by a process

known as development. Unexposed (negative) or exposed (positive) portions of
the photo- resist are chemically dissolved at the time of development. A low-
temperature baking process hardens the subsequently remaining portion.

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 To create the desired pattern, actual removal of the material is done by
the etching process. The wafer is immersed in a suitable etching solution, which
eats out the exposed material leaving the material beneath the protective
photo-resist intact. The etching solution depends on the material to be etched
out. Hydrofluoric acid (HF) is used for SiO2 and poly-silicon, whereas phosphoric
acid is used for nitride and metal.

Another alternative to this wet chemical etching process is the plasma

etching or ion etching. In this dry process, a stream of ions or electrons is used to
blast the material away. Ions created by glow discharge at low pressure are
directed to the target. Ions can typically penetrate about 800 Å of oxide or photo-
resist layers, and thick layers of these materials are used as a mask of some area,
whereas the exposed material is being sputtered away. This plasma technique
can produce vertical etching with little undercutting. As a consequence, it is
commonly used for producing fine lines and small geometries associated with
high-density VLSI circuits.

Finally, the photo-resist material is removed by a chemical reaction of this

material with fuming nitric acid or exposure to atomic oxygen which oxides away
the photo-resist. Patterned layers of different materials in engraved form are left
at the end of this process.

Diffusion

After masking some parts of the silicon surface, selective diffusion can be
done in the exposed regions. There are two basic steps: pre-deposition and drive-
in. In the pre-deposition step, the wafer is heated in a furnace at 1000 °C, and
dopant atoms such as phosphorous or boron mixed with an inert gas, say
nitrogen, and are introduced into it. Diffusion of these atoms takes place onto the
surface of the silicon, forming a saturated solution of the dopant atoms and solid.

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 The impurity concentration goes up with a temperature up to 1300 °C and then
drops. The depth of penetration depends on the duration for which the process is
carried out. In the drive-in step, the wafer is heated in an inert atmosphere for few
hours to distribute the atoms more uniformly and to a higher depth.

Another alternative method for diffusion is ion implantation. Dopant gas is

first ionized with the help of an ionizer and ionized atoms are accelerated
between two electrodes with a voltage difference of 150 kV. The accelerated
gas is passed through a strong magnetic field, which separates the stream of
dopant ions on the basis of molecular weights, as it happens in mass
spectroscopy. The stream of these dopant ions is deflected by the magnetic field
to hit the wafer. The ions strike the silicon surface at high velocity and penetrate
the silicon layer to a certain depth as determined by the concentration of ions
and accelerating field. This process is also followed by drive-in step to achieve
uniform distribution of the ions and increase the depth of penetration.

Different materials, such as thick oxide, photo-resist, or metal can serve as

mask for the ion implantation process. But implantation can be achieved through
thin oxide layers. This is frequently used to control the threshold voltage of MOS
transistor. This control was not possible using other techniques, and ion
implantation is now widely used not only for controlling the threshold voltage but
also for all doping stages in MOS fabrication.

Deposition

In the MOS fabrication process, conducting layers such as poly-silicon and

aluminium, and insulation and protection layers such as SiO2 and Si3N4 are
deposited onto the wafer surface by using the chemical vapor deposition (CVD)
technique in a high-temperature chamber:

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Poly-silicon is deposited simply by heating silane at about 1000 °C, which releases
hydrogen gas from silane and deposits silicon. To deposit silicon dioxide, a mixture of
nitrogen, silane, and oxygen is introduced at 400–450 °C. Silane reacts with oxy- gen
to produce silicon dioxide, which is deposited on the wafer.Todeposit silicon nitride
silane and ammonia are heated at about 700 °C to produce nitride andhydrogen.
Aluminium is deposited by vaporizing aluminium from a heated filament in high
vacuum.

BASIC MOS TRANSISTORS

METAL-OXIDE-SEMICONDUCTOR (MOS) AND RELATED VLSI TECHNOLOGY

Within the bounds of MOS technology, the possible circuit realizations may
be based on pMOS, nMOS, CMOS and now BiCMOS devices.
However, this text will deal with nMOS, then with. CMOS (which includes
pMOS transistors) and BICMOS, and finally with GaAs technology, all of which may
be classed as leading Integrated circuit technologies.
Although CMOS is the dominant technology, some of the examples used to
illustrate the design processes will be presented in nMOS form. The reasons for this
are as follows:
 For nMOS technology, the design methodology and the design rules are
easily learned, thus providing a simple but excellent introduction to
structured design for VLSI.
 nMOS technology and design processes provide an excellent background
for other technologies. In particular, some familiarity with nMOS allows a

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 relatively easy transition to CMOS technology and design.
 For GaAs technology some arrangements in relation to logic design are
similar to those employed in nMOS technology. Therefore, understanding
the basics of nMOS design will assist in the layout of GaAs circuits.
 Not only is VLSI technology providing the user with a new and more
complex range of ‘off the shelf’ circuits, but VLSI design processes are
such that system designers can readily design their own special circuits of
considerable complexity. This provides a new degree of freedom for
designers and it is probable that some very significant advances will
result. Couple this with the fact that integration density is increasing
rapidly, as advances in technology shrink the feature size for circuits
integrated in silicon. Typical manufacturers’ commercial IC products have
shown this trend quite clearly as shown in Figure 1.11 and,
simultaneously, the effectiveness of the circuits produced has increased
with scaling down.

A common measure of effectiveness is the speed power product of the

basic logic gate circuit of the technology (for nMOS, the nor gate, with nand &
nor gates for CMOS). Speed power product is measured in picojoules (pJ) and
is the product of the gate switching delay in nanoseconds and the gate power
dissipation in milliwatts. Typical figures are implied in Figure 1.11.

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 Figure 1.2.1: Approximate minimum line width of commercial products versus
year.

1.3 MOS TRANSISTORS

Having now established some background, let us turn our attention to

basic MOS processes and devices. In particular, let us examine the basic nMOS
enhancement and depletion mode transistors as shown in Figures 1.13(a) and (b).
nMOS devices are formed in a p-type substrate of moderate doping level. The
source and drain regions are formed by diffusing n-type impurities through
suitable masks into these areas to give the desired n-impurity concentration and
give rise to depletion regions which extend mainly in the more lightly doped p-
region as shown. Thus, source and drain are isolated front one another by two
diodes. Connections to the source and drain are made by a deposited metal
layer. In order to make a useful device, there must be the capability for
establishing and controlling a current between source and drain, and this is
commonly achieved in one of two ways, giving rise to the enhancement mode
and depletion mode transistors.

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 Figure 1.13: MOS transistors (VD = 0 V. Source gate and substrate to 0 V).

Consider the enhancement mode device first, shown in Figure 1.13 (a). A
polysilicon gate is deposited on a layer of insulation over the region between
source and drain. Figure 1.13(a) shows a basic enhancement mode device in
which the channel is not established and the device is in a non-conducting
condition, VD = Vs = Vgs = 0. If this gate is connected to a suitable positive voltage
with respect to the source, then the electric fluid established between the gate
and the substrate gives rise to a charge inversion region in the substrate under the
gate insulation and a conducting path or channel is formed between source and
drain.
The channel may also be established so that it is present under the
condition Vgs = 0 by implanting suitable impurities in the region between source
and drain during manufacture and prior to depositing the insulation and the
gate. This arrangement is shown in Figure 1.13(b). Under these circumstances,
source and drain are connected by a conducting channel, but the channel may
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now be closed by applying a suitable negative voltage to the gate.

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 In both cases, variations and the gate voltage allow control of any current
flow between source and drain.

Figure 1.13(c) shows the basic pMOS transistor structure for an

enhancement mode device. In this case the substrate is of n-type material and
the source and drain diffusions are consequently p-type. In the figure, the
conditions shown are those for an unbiased device; however, the application
of a negative voltage of suitable magnitude (> IVtI) between gate and source
will give rise to the formation of a channel (p-type) between the source and
drain and current may then flow if the drain is made negative with respect
to the source. In this case the current is carried by holes as opposed to electrons
(as is the case for nMOS devices). In consequence, pMOS transistors are
inherently slower than nMOS, since hole mobility μp is less, by a factor of
approximately 2.5, than electron mobility μn. However, bearing these differences
in mind, the discussions of nMOS transistors which follow relate equally well to
pMOS transistors.

1.3.2 ENHANCEMENT MODE TRANSISTOR ACTION

To gain some understanding of this mechanism, let us further consider the

enhancement mode device, as in Figure 1.14, under three sets of conditions. It
must first be recognized that in order to establish the channel in the first place
a minimum voltage level of threshold voltage Vt, must be established between
gate and source (and of course between gate and substrate as a result).
Figure 1.14(a) then indicates the conditions prevailing with the channel
established but no current flowing between source and drain (Vds = 0). Now
consider the conditions prevailing when current flows in the channel by applying
a voltage Vds, between drain and source. There must, of course, be a
corresponding IR drop = Vds along the channel. This results in the voltage
between gate and channel varying with distance along the channel with the
voltage being a maximum of Vgs, at the source end. Since the effective gate
voltage
23 | VisL SVIg D
=EVSgs
I G–NV- tU(no
N I Tcurrent
-I flows when Vgs < Vt) there will be voltage

BTECH_ECE-SEM 41
available to invert the channel at the drain end so long as Vgs - Vt ≥ Vds. The
limiting condition comes when Vds = Vgs – Vt. For all voltages Vds < Vgs - Vt the
device is in the non-saturated region of operation which is the condition shown in
Figure 1.14(b).

Figure 1.3.2 : Enhancement mode transistor for particular values of Vds with
(Vgs > Vt).

Consider now what happens when Vds is increased to a level greater than
Vgs - Vt. In this case, an IR drop = Vgs - Vt takes place over less than the whole
length of the channel so that over part of the channel, near the drain, there
is insufficient electric field available to give rise to an inversion layer to create
24 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
the channel. The channel is, therefore, ‘pinched off’ as indicated in Figure
1.14(c). Diffusion current completes the path from source to drain in this case,
causing the channel to exhibit a high resistance and behave as a constant
current source. This region, known as saturation, is characterized by almost
constant current for increase of Vds above Vds = Vgs - Vt. In all cases, the channel
will cease to exist and no current will flow when Vgs < Vt. Typically, for
enhancement mode devices, Vt = 1 volt for VDD = 5 V or, in general terms, Vt = 0.2
VDD.

1.3.3 DEPLETION MODE TSANSISTOR ACTION

n-MOS Depletion mode MOSFETs are built with P-type silicon substrates, and
P-channel versions are built on N-type substrates. In both cases they include a thin
gate oxide formed between the source and drain regions. A conductive channel
is deliberately formed below the gate oxide layer and between the source and
drain by using ion implantation. By implanting the correct ion polarity in the
channel region during fabrication determines the polarity of the threshold voltage
(i.e. -Vt for an N channel transistor, or + Vt for an P-channel transistor). The actual
concentration of ions in the substrate-to-channel region is used to adjust the
threshold voltage (Vt) to the desired value. Depletion-mode devices are a little
more difficult to manufacture and their characteristics harder to control than
enhancement types, which do not require ion implantation.

For depletion mode devices the channel is established, due to the

implant, even when Vgs = 0, and to cause the channel to cease to exist a negative
voltage Vtd must be applied between gate and source. Vtd is typically < - 0.8 VDD,
depending on the implant and substrate bias, but, threshold voltage differences
apart, the action is similar to that of the enhancement mode transistor. Commonly
used symbols for n MOS and pMOS transistors are set out in Figure 1.15a and
depletion mode transistor is shown in Fig. 1.15b.

25 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 Figure 1.3.3 : Transistor circuit symbols.

Figure 1.3.3 b: nMOS depletion mode transistor

1.4 NMOSFABRICATION PROCESS:

Fig 1.4: nMOS fabrication steps

26 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
1.4.1 nMOS Fabrication Steps

Using the basic processes mentioned in the previous section, typical

processing steps of the poly-silicon gate self-aligning nMOS technology
are given below. It can be better understood by considering the
fabrication of a single enhancement-type transistor. Figure 1.5 shows
the step-by-step production of the transistor. Step 1 the first step is to
grow a thick silicon dioxide (SiO2) layer, typically of 1 µm thickness all
over the wafer surface using the wet oxidation technique. This oxide
layer will act as a barrier to dopants during subsequent processing and
pro- vide an insulting layer on which other patterned layers can be
formed.

Step 2 In the SiO2 layer formed in the previous step, some regions are
defined where transistors are to be formed. This is done by the
photolithographic process discussed in the previous section with the
help of a mask (MASK 1). At the end of this step, the wafer surface is
exposed in those areas where diffusion regions along with a channel are
to be formed to create a transistor.
Step 3 A thin layer of SiO2, typically of 0.1 μm thickness, is grown all over
the entire wafer surface and on top of this poly-silicon layer is deposited.
The poly- silicon layer, of 1.5 μm thickness, which consists of heavily
doped poly-silicon is deposited using the CVD technique. In this step,
precise control of thickness, impurity con- centration, and resistivity is
necessary.
Step 4 Again by using another mask (MASK 2) and photographic
process, the poly-silicon is patterned. By this process, poly-gate structures
and interconnections by poly layers are formed.
Step 5 Then the thin oxide layer is removed to expose areas where n-
diffusions are to take place to obtain source and drain. With the poly-
silicon and underlying thin oxide layer as the protective mask, the
diffusion process is performed. It may be noted that the process is self-
aligning, i.e., source and drain are aligned automatically with respect to
the gate structure.
Step 6 A thick oxide layer is grown all over again and holes are made at
selected areas of the poly-silicon gate, drain, and source regions by
using a mask (MASK 3) and the photolithographic process.
Step 7 A metal (Aluminium) layer of 1 μm thickness is deposited on the
entire surface by the CVD process. The metal layer is then patterned
27 | V L S I D E S I G N - U N I T - I
with the help of a mask (MASK 4) and the photolithographic process.

BTECH_ECE-SEM 41
 Necessary interconnections are provided with the help of this metal
layer.
Step 8 The entire wafer is again covered with a thick oxide layer—this is
known as over-glassing. This oxide layer acts as a protective layer to
protect different parts from the environment. Using a mask (MASK 5),
holes are made on this layer to pro- vide access to bonding pads for
taking external connections and for testing the chip.

The above processing steps allow only the formation of nMOS

enhancement-type transistors on a chip. However, if depletion-type
transistors are also to be formed, one additional step is necessary for the
formation of n-diffusions in the channel regions where depletion
transistors are to be formed. It involves one additional step in between
step 2 and step 3 and will require one additional mask to define channel
regions following a diffusion process using the ion implantation
technique.

1.5 CMOS Fabrication Steps

There are several approaches for CMOS fabrication, namely, p-well, n-

well, twin- tub, triple-well, and SOI. The n-well approach is compatible
with the nMOSprocess and can be easily retrofitted to it. However, the
most popular approach is the p-well approach, which is similar to the n-
well approach. The twin-tub and silicon on sapphire are more complex
and costly approaches. These are used to produce superior quality
devices to overcome the latch-up problem, which is predominant in
CMOS devices. (i)
1.5.1 The p-well Process:
The p-well structure consists of an n-type substrate in which p-devices
may be formed by suitable masking and diffusion and, in order to
accommodate n-type devices, a deep p-well is diffused into the n-type
substrate as shown in the Fig. below.

28 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 This diffusion should be carried out with special care since the p-well
doping concentration and depth will affect the threshold voltages as
well as the breakdown voltages of the n-transistors. To achieve low
threshold voltages (0.6 to 1.0 V) either deep-well diffusion or high-well
resistivity is required. However, deep wells require larger spacing
between the n- and p-type transistors and wires due to lateral diffusion
and therefore a larger chip area. The p-wells Act as substrates for the n-
devices within the parent n-substrate, and, the two areas are electrically
isolated. Except this in all other respects- like masking, patterning, and
diffusion-the process is similar to NMOS fabrication.

Fig 1.6: P-well fabrication process (Figs 1, 2, 3 & 4)

29 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 The diagram below shows the CMOS p-well inverter showing VDD and Vss
substrate connections

Fig 1.7: P-well fabrication process

1.5.2 The n-well Process : Though the p-well process is widely used in C-
MOS fabrication the n-well fabrication is also very popular because of
the lower substrate bias effects on transistor threshold voltage and also
lower parasitic capacitances associated with source and drain regions.
The typical n-well fabrication steps are shown in the diagram below.

Fig 1.8: n-well fabrication steps

30 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 The first mask defines the n-well regions. This is followed by a low dose
phosphorus implant driven in by a high temperature diffusion step to
form the n-wells. The well depth is optimized to ensure against-substrate
top+ diffusion breakdown without compromising then-well to n+ mask
separation. The next steps are to define the devices and diffusion paths,
grow field oxide, deposit and pattern the poly silicon, carry out the
diffusions, make contact cuts, and finally metalize as before. Lt will be
seen that an n+ mask and its complement may be used to define the n-
and p-diffusion regions respectively. These same masks also include the
VDD and Vss contacts (respectively). It should be noted that,
alternatively, we could have used a p+ mask and its complement since
the n + and p + masks are generally complementary. The diagram
below shows the Cross-sectional view of n-well CMOS Inverter.

Fig 1.9 N-well fabrication

Due to the differences in charge carrier mobilities, the n-well process

creates non-optimum p-channel characteristics. However, in many
CMOS designs (such as domino-logic and dynamic logic structures), this
is relatively unimportant since they contain a preponderance of n-
channel devices. Thus then-channel transistors are mainly those used to
form1ogic elements, providing speed and high density of elements.
However, a factor of the n-well process is that the performance of the
already poorly performing p-transistor is even further degraded. Modern
process lines have come to grips with these problems, and good device
performance may be achieved for both p-well and n-well fabrication.
31 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
1.5.3 Twin-Tub Process

In the twin-tub process, the starting material is either an n+ or p+

substrate with a lightly doped epitaxial layer, which is used for protection
against latch-up. The process is similar to the n-well process, involving the
following steps:
 Tub formation

 Thin oxide construction

 Source and drain implantations

 Contact cut definition

 Metallization

This process allows n-transistors and p-transistors to be separately

optimized to pro- vide balanced performance of both types of
transistors. The threshold voltage, body effect, and the gain associated
with n- and p-devices have to be independently optimized. Figure 1.10
visualizes a CMOS inverter fabricated using the twin-tub process.

Fig1.10: CMOS transistor realized using twin-tub process

1.5.4 Silicon-on-Insulator (SOI) CMOS Process:

32 | VRather
L S I D E than
S I G Nusing
- U N I Tsilicon
-I as the substrate material, technologists have
sought to use an insulating substrate to improve process characteristics

BTECH_ECE-SEM 41
 such as speed and latch-up susceptibility. The SOI CMOS technology
allows the creation of independent, completely isolated nMOS and
pMOS transistors virtually side-by- side on an insulating substrate. The
main advantages of this technology are the higher integration density
(because of the absence of well regions), complete avoidance of the
latch-up problem, and lower parasitic capacitances compared to the
conventional p & n-well or twin-tub CMOS processes. A cross- section of
nMOS and pMOS devices using SOI process is shown below in Figure
1.10.

Figure 1.11: A cross-section of nMOS and pMOS devices using SOI

process

The SOI CMOS process is considerably more costly than the standard p &
n-well CMOS process. Yet the improvements of device performance
and the absence of latch-up problems can justify its use, especially for
deep-sub-micron devices.

1.6 DRAIN-TO-SOURCE CURRENT IDS VERSUS VOLTAGE VDS RELATIONSHIPS:

The working of a MOS transistor is based on the principle that the

use of a voltage on the gate induces a charge in the channel between
source and drain, which may then be caused to move from source to
drain under the influence of an electric field created by voltage Vds
applied between drain and source. Since the charge induced is
dependent on the gate to source voltage Vgs then Ids is dependent on
both Vgs and Vds. Let us consider the diagram below in which electrons
will flow source to drain So, the drain current is given by

Charge induced in channel (Qc)

Ids =-Isd = _____________________

Electron transit time (τ)

33 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 Length of the channel (L)

Where the transit time is given by τsd = ------------------------------

Velocity (v)

But velocity v= µ Eds

Where

µ =electron or hole mobility and Eds = Electric field

Also Eds = Vds/L

So, v = µ.Vds/L

And τsd= L2 / µ.Vds

The typical values of µ at room temperature are given below.

34 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
1.6.1 The Non-saturated Region:

Let us consider the Id vs Vd relationships in the non-saturated region The charge

induced in the channel due to due to the voltage difference between the gate
and the channel, Vgs (assuming substrate connected to source). The voltage
along the channel varies linearly with distance X from the source due to the IR
drop in the channel .In the non-saturated state the average value is Vds/2. Also
the effective gate voltage Vg = Vgs – Vt where Vt, is the threshold voltage
needed to invert the charge under the gate and establish the channel.

Hence the induced charge is Qc = Eg εins εo w. L Where

Eg = average electric field gate to channel

Εins = relative permittivity of insulation between gate and channel

Εo = permittivity of free space.

So, we can write that

Here D is the thickness of the oxide layer. Thus

So, by combining the above two equations ,we get

Or the above equation can be written as

35 | VInL Sthe
I Dnon-saturated
E S I G N - U N I T or
- I resistive region where Vds < Vgs – Vt and

BTECH_ECE-SEM 41
Generally , a constant β is defined as

So that ,the expression for drain –source current will become

The gate /channel capacitance is

Hence we can write another alternative form for the drain current as

Some time it is also convenient to use gate –capacitance per unit area , Cg

So, the drain current is

This is the relation between drain current and drain-source voltage in

non-saturated region.

36 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
1.7.2. The Saturated Region

Saturation begins when Vds = Vgs - V, since at this point the IR drop in the
channel equals the effective gate to channel voltage at the drain and
we may assume that the current remains fairly constant as Vds increases
further. Thus

Or we can also write that

Or it can also be written as

Or

The expressions derived above for Ids hold for both enhancement and
depletion mode devices. Here the threshold voltage for the NMOS depletion
mode device (denoted as Vtd) is negative. MOS Transistor Threshold Voltage Vt.

1.7 ASPECTS OF MOS TRANSISTOR THRESHOLD VOLTAGE VT:

The gate structure of a MOS transistor consists, of charges stored in the

dielectric layers and in the surface to surface interfaces as well as in the
substrate itself. Switching an enhancement mode MOS transistor from
the off to the on state consists in applying sufficient gate voltage to
neutralize these charges and enable the underlying silicon to undergo
an inversion due to the electric field from the gate. Switching a
depletion mode nMOS transistor from the on to the off state consists in
applying enough voltage to the gate to add to the stored charge and
invert the 'n' implant region to 'p'. The threshold voltage Vt may be
expressed as:
37 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 where

QB = the charge per unit area in the depletion layer below the oxide
Qss = charge density at Si: SiO2 interface
C0 =Capacitance per unit area.
Φms = work function difference between gate and Si
ΦfN = Fermi level potential between inverted surface and bulk Si

For polynomial gate and silicon substrate, the value of Φns is negative
but negligible and the magnitude and sign of Vt are thus determined by
balancing the other terms in the equation. To evaluate the Vt the other
terms are determined as below.

1.7.1 Body Effect:

Generally while studying the MOS transistors it is treated as a three

terminal device. But, the body of the transistor is also an implicit terminal
which helps to understand the characteristics of the transistor.
Considering the body of the MOS transistor as a terminal is known as the
body effect. The potential difference between the source and the body
(Vsb) affects the threshold voltage of the transistor. In many situations,
this Body Effect is relatively insignificant, so we can (unless otherwise
stated) ignore the Body Effect. But it is not always insignificant, in some
cases it can have a tremendous impact on MOSFET circuit performance.

38 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 Figure 1.16: Body effect – nMOS device

Increasing Vsb causes the channel to be depleted of charge carriers

and thus the threshold voltage is raised.
Change in Vt is given by ΔVt = (Vsb)1/2 where is a constant which
depends on substrate doping so that the more lightly doped the
substrate, the smaller will be the body effect. The threshold voltage can
be written as

Where Vt(0) is the threshold voltage for Vsd = 0

For n-MOS depletion mode transistors, the body voltage values at
different VDD voltages are given below.
VSB = 0 V ;
Vsd = -0.7VDD (= - 3.5 V for VDD =+5V)
VSB = 5 V;
Vsd = -0.6VDD (= - 3.0 V for VDD =+5V)

39 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
1.8 MOS TRANSISTOR TRANSCONDUCTANCE GM AND OUTPUT CONDUCTANCE
GDS:

Trans conductance expresses the relationship between output current

Ids and the input voltage Vgs and defined as

But change the charge

40 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 So that

Now

In saturation

It is possible to increase the gm of a MOS device by increasing width.

And submitting for

Alternatively

The output conductance gds can be expressed by

41 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 1.8.1 MOS transistor figure of merit ω0

An indication of frequency response may be obtained from the

parameter ω0

This shows that switching speed depends on gate voltage above

threshold and on carrier mobility and inversely as the square of channel
length .a fast circuit requires that gm be as high as passable

9. Practice Quiz

1. VLSI technology use_________________ to form integrated circuit.

a) transistors
b) switches
c) diode
d) buffers

2. Medium scale integration has_______________

a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates

3. The difficulty in achieving high doping concentration leads to ____________-

a) error in concentration
b) error in variation
c) error in doping
d) distribution error

42 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
4. Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic

5. The field effect transistor is a _______ device?

a) uinpolar
b) bipolar
c) both a & b
d) none

6. The number of inputs to a gate is called as ________

a) Fanin
b) Fanout
c) Fan
d) None

7. In Moors law the no.of_________on an integrated ckt will double every 18

monthhs
a) Transistors
b) capacitors
c) both a&b
d) None

8. p well created on
a) p substrate
b) n substrate
c) p&n substrate
d) None

8. A photoresist layer is exposed to

a) Visible light
b) LED
c) infrared light
d) Ultraviolet light
43 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
10. Which is used for the interconnection
a) boron
b) oxigen
c) silicon
d) Aluminium

10. Assignments

S.No Question BL Co

Explain Enhancement mode and Depletion mode

1 2 1
transistors

Explain CMOS Fabrication process in

2 1 1
a. P well process

b. N well process

c. Twin tub process

a. Explain transconductance, output conductance

3 2 1
b. Explain figure of merit .

a. Explain IC era.
4 2 1
b. Explain thermal aspects of processing

E x pl ai n I d s Ve r s u s V d s r el a ti o n s h i p i n N o n
5 1 2
s a tu r a ti o n r e g i o n a n d S a tu r a ti o n r e g i o n .

44 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
11. Part A- Question & Answers

S.No Question & Answers BL CO

What is an Integrated circuit?

An integrated circuit (IC) is an electronic circuit fabricated

on a small semiconductor wafer by building thousands or
millions of resistors, capacitors, diodes and transistors on it.
ICs are the heart and brains of most circuits.

1 The integrated circuits are divided into different categories

1
depending on the number of components that are 1
fabricated in the chip. They are,

Small Scale Integration (SSI)

Medium Scale Integration (MSI)

Large Scale Integration (LSI)

Very Large Scale Integration (VLSI).

Give the basic process for IC fabrication?

Silicon wafer Preparation, Epitaxial Growth

Oxidation , photolithography

Diffusion, Ion implantation

2 1
2
Isolation technique

Metallization

Assembly processing & Packaging

45 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 What are the steps involved in twin-tub process?

Tub Formation

3 Thin-oxide Construction 1
1
Source & Drain Implantation

Contact cut definition

Metallization

What are four generations of Integration circuits?

4 1
SSI( Small scale integration) 1
MSI(Medium scale integration)
LSI(Large scale integration)
VLSI(Very large scale integration)

Give advantages of IC?

5 1
Size is less, High speed, Less power dissipation etc. 1

Define Short Channel devices?

Transistors with Channel length less than 3- 5 microns are

6 1
termed as Short channel devices. With short channel devices 1
the ratio between the lateral & vertical dimensions are
reduced.
Define Threshold voltage in CMOS?

The Threshold voltage, VT for a MOS transistor can be defined as

7 1
the voltage applied between the gate and the source ofthe 1
MOS transistor below which the drain to source current,
IDS effectively drops to zero.

46 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 What is Body effect?

The threshold voltage VT is not a constant w. r. to the voltage

8 1
difference between the substrate and the source of MOS 1

transistor. This effect is called substrate-bias effect or body

effect.

12. Part B- Questions

S.No Question BL CO

Explain the Mos transistor transconductance, output

1 conductance and figure of merit 3 1

Explain clearly about n-well CMOS fabrication process with

2 2 1
neat diagrams.

3 Explain the NMOS fabrication procedure. 2 1

Explain its operation and derive the drain to source current equation
4 in saturation and resistance region. 3 1

Explain in detail about the steps involved in CMOS IC

5 2 1
fabrication process with essential diagrams
Draw the Ids-Vds relationship curve and discuss in detail
6 2 2
about its role in the MOS design equations

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BTECH_ECE-SEM 41
13. Supportive Online Certification Courses
1. Digital circuits By Prof. Santanu Chattopdhayay, conducted by IIT Kharagpur
on NPTEL – 12 weeks
2. Digital Electronic Circuits By Prof. Goutam Saha, conducted IIT Kharagpur on
NPTEL – 12 weeks

14. Real Time Applications

S.No Application CO

3D Lifting based Discrete Wavelet Transform

The main aim of this project is to aid with image coding in order to
1
produce high accurate images without losing any information. To
1
achieve the task, this approach implements a lifting filter based 3D
discrete wavelet transform VLSI architecture.

15. Contents Beyond Syllabus

Low Power Design for safety Critical applications: safe operation constraints vs
low-power techniques, Unsuitable low power design techniques for safety critical
applications, Low-power and safe-operating circuits

16. Prescribed Text Books & Reference Books

Text Books:
1. Kamran Eshraghian, Eshraghian Douglas and A. Pucknell, “Essentials of VLSI
circuits and systems”, PHI, 2013 Edition.

2. K.Lal Kishore and V.S.V. Prabhakar, “VLSI Design”, IK Publishers

48 | V L S I D E S I G N - U N I T - I

BTECH_ECE-SEM 41
 References:

1. Weste and Eshraghian, “Principles of CMOS VLSI Design”, Pearson

Education, 1999.

2. Wayne Wolf, “Modern VLSI Design”, Pearson Education, 3rd Edition, 1997.

3. John P. Uyemura, “Chip Design for Submicron VLSI: CMOS layout and
Simulation”, Thomson Learning.

4. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John wiley,

2003.

5. John M. Rabaey, “Digital Integrated Circuits”, PHI, EEE, 1997.

17. Mini Project Suggestion

1. An Efficient VLSI Architecture for Removal of Impulse Noise in Image:

This project aims to enhance the visual quality of images and to avoid
chances of being corrupted by impulse noise by implementing an efficient
VLSI architecture using edge preserving filter.

2. VHDL Model of Smart Sensor:

The aim of this project is to build a VHDL model of smart sensor by

implementing algorithm for smart sensor with noise cancellation using IEEE 1451
communication standard. The complete simulation of this project is carried by
VHDL program.

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