TMUX1108

SCDS388B – NOVEMBER 2018 – REVISED FEBRUARY 2024

TMUX1108 5V / ±2.5V, Low-Leakage-Current, 8:1 Precision Multiplexer

1 Features 3 Description
• Wide supply range: ±2.5V, 1.08V to 5.5V The TMUX1108 is a precision complementary metal-
• Low leakage current: 3pA oxide semiconductor (CMOS) multiplexer (MUX). The
• Low charge injection: 1pC TMUX1108 offers a single channel, 8:1 configuration.
• Low on-resistance: 2.5Ω A wide operating supply of 1.08V to 5.5V makes
• -40°C to +125°C operating temperature this device an excellent choice for a wide array
• 1.8V logic compatible of applications from medical equipment to industrial
• Fail-safe logic systems. The device supports bidirectional analog
• Rail to rail operation and digital signals on the source (Sx) and drain (D)
• Bidirectional signal path pins ranging from GND to VDD. All logic inputs have
• Break-before-make switching action 1.8V logic compatible thresholds, allowing for both
• ESD protection HBM: 2000V TTL and CMOS logic compatibility when operating
in the valid supply voltage range. Fail-Safe Logic
2 Applications circuitry allows voltages on the control pins to be
• Ultrasound scanners applied before the supply pin, protecting the device
• Patient monitoring and diagnostics from potential damage.
• Optical networking
The TMUX1108 is part of the precision switches and
• Optical test equipment
multiplexers family of devices. These devices have
• Remote radio unit
very low on and off leakage currents and low charge
• ATE test equipment
injection, allowing them to be used in high precision
• Factory automation and industrial process controls
measurement applications. A low supply current of
• Programmable logic controllers (PLC)
8nA and small package options enable use in portable
• Analog input modules
applications.
• Digital multimeters
• Battery monitoring systems Package Information
PART NUMBER(1) PACKAGE(2) PACKAGE SIZE(3)
PW (TSSOP, 16) 5mm × 6.4mm
TMUX1108
RSV (QFN, 16) 2.6mm × 1.8mm

(1) See Device Comparison

(2) For more information, see Section 11
(3) The package size (length × width) is a nominal value and
includes pins, where applicable.

VDD TMUX1108
VDD
VREF S1
EN S2
S3
Bridge Sensor REF
S4
D
S1 + S5
Op Amp S6
S2
- S7
S3 S8
Thermocouple D
S4 + 1-OF-8
S5 Op Amp DECODER
Precision
S6 ADC
-
S7 A0 A1 A2 EN
Current Sensing
S8
A1
A2 Block Diagram
A0
GND 1.8V Logic
Photo Signals
LED Detector
Optical Sensor
TMUX1108
Analog Inputs

Application Example

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram......................................... 21
2 Applications..................................................................... 1 7.3 Feature Description...................................................21
3 Description.......................................................................1 7.4 Device Functional Modes..........................................23
4 Device Comparison Table...............................................2 8 Application and Implementation.................................. 24
5 Pin Configuration and Functions...................................2 8.1 Application Information............................................. 24
6 Specifications.................................................................. 4 8.2 Typical Application.................................................... 24
6.1 Absolute Maximum Ratings........................................ 4 8.3 Power Supply Recommendations.............................25
6.2 ESD Ratings............................................................... 4 8.4 Layout....................................................................... 26
6.3 Recommended Operating Conditions.........................4 9 Device and Documentation Support............................27
6.4 Thermal Information....................................................5 9.1 Documentation Support............................................ 27
6.5 Electrical Characteristics (VDD = 5V ±10 %)............... 5 9.2 Receiving Notification of Documentation Updates....27
6.6 Electrical Characteristics (VDD = 3.3V ±10 %)............ 7 9.3 Support Resources................................................... 27
6.7 Electrical Characteristics (VDD = 2.5V ±10 %), 9.4 Trademarks............................................................... 27
(VSS = –2.5V ±10 %)..................................................... 8 9.5 Electrostatic Discharge Caution................................27
6.8 Electrical Characteristics (VDD = 1.8V ±10 %)............ 9 9.6 Glossary....................................................................27
6.9 Electrical Characteristics (VDD = 1.2V ±10 %).......... 11 10 Revision History.......................................................... 27
6.10 Typical Characteristics............................................ 13 11 Mechanical, Packaging, and Orderable
7 Detailed Description......................................................16 Information.................................................................... 28
7.1 Overview................................................................... 16

4 Device Comparison Table

PRODUCT DESCRIPTION
TMUX1108 8:1, 1-Channel. single-ended multiplexer

5 Pin Configuration and Functions EN

A0

A1

A2
A0 1 16 A1

EN 2 15 A2
16

15

14

13
VSS 3 14 GND VSS 1 12 GND

S1 4 13 VDD
S1 2 11 VDD

S2 5 12 S5
S2 3 10 S5
S3 6 11 S6
S3 4 9 S6
S4 7 10 S7
5

D 8 9 S8

Not to scale
Not to scale
S4

S8

S7

Figure 5-1. TMUX1108: PW Package, 16-Pin TSSOP Figure 5-2. TMUX1108: RSV Package, 16-Pin QFN
(Top View) (Top View)

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Table 5-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME TSSOP UQFN
A0 1 15 I Address line 0
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
EN 2 16 I
the A[2:0] logic inputs determine which switch is turned on.
Negative power supply. This pin is the most negative power-supply potential. For reliable
VSS 3 1 P operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VSS and GND.
VSS can be connected to ground for single supply applications.
S1 4 2 I/O Source pin 1. Can be an input or output.
S2 5 3 I/O Source pin 2. Can be an input or output.
S3 6 4 I/O Source pin 3. Can be an input or output.
S4 7 5 I/O Source pin 4. Can be an input or output.
D 8 6 I/O Drain pin. Can be an input or output.
S8 9 7 I/O Source pin 8. Can be an input or output.
S7 10 8 I/O Source pin 7. Can be an input or output.
S6 11 9 I/O Source pin 6. Can be an input or output.
S5 12 10 I/O Source pin 5. Can be an input or output.
Positive power supply. This pin is the most positive power-supply potential. For reliable
VDD 13 11 P
operation, connect a decoupling capacitor ranging from 0.1µF to 10µF between VDD and GND.
GND 14 12 P Ground (0V) reference
A2 15 13 I Address line 2
A1 16 14 I Address line 1

(1) I = input, O = output, I/O = input and output, P = power

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN MAX UNIT
VDD–VSS –0.5 6 V
VDD Supply voltage –0.5 6 V
VSS –3.0 0.3 V
VSEL or VEN Logic control input pin voltage (EN, A0, A1, A2) –0.5 6 V
ISEL or IEN Logic control input pin current (EN, A0, A1, A2) –30 30 mA
VS or VD Source or drain voltage (Sx, D) –0.5 VDD+0.5 V
IS or ID (CONT) Source or drain continuous current (Sx, D) IDC ± 10 %(4) IDC ± 10 %(4) mA
Source and drain peak current: (1 ms period maximum, 10% duty
IS or ID (PEAK) Ipeak ± 10 %(4) Ipeak ± 10 %(4) mA
cycle maximum) (Sx, SxA, SxB, D, DA, DB)
Tstg Storage temperature –65 150 °C
Ptot Total power dissipation(5) (6) 500 mW
TJ Junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
(4) Refer to Recommended Operating Conditions for IDC and IPeak ratings.
(5) For TSSOP package: Ptot derates linearly above TA=90°C by 8.41mW/°C
(6) For QFN package: Ptot derates linearly above TA=82°C by 7.43mW/°C

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±750
specification JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Positive power supply voltage (single) 1.08 5.5 V
VSS Negative power supply voltage (dual) -2.75 0 V
VDD - VSS Supply rail voltage difference 1.08 5.5 V
VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V
VSEL or VEN Address or enable pin voltage 0 5.5 V
TA Ambient temperature –40 125 °C
Tj = 25°C 150 mA
Tj = 85°C 120 mA
IDC Continuous current through switch
Tj = 125°C 60 mA
Tj = 130°C 50 mA

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Tj = 25°C 300 mA

Peak current through switch(1 ms period maximum, Tj = 85°C 300 mA

Ipeak
10% duty cycle maximum) Tj = 125°C 180 mA
Tj = 130°C 160 mA

6.4 Thermal Information

DEVICE DEVICE
THERMAL METRIC(1) PW (TSSOP) RSV (QFN) UNIT
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 118.9 134.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 49.3 74.3 °C/W
RθJB Junction-to-board thermal resistance 65.2 62.8 °C/W
ΨJT Junction-to-top characterization parameter 7.6 4.3 °C/W
ΨJB Junction-to-board characterization parameter 64.6 61.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics (VDD = 5V ±10 %)

at TA = 25°C, VDD = 5V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
25°C 2.5 4 Ω
VS = 0V to VDD
RON On-resistance –40°C to +85°C 4.5 Ω
ISD = 10mA
–40°C to +125°C 4.9 Ω
25°C 0.13 Ω
On-resistance matching between VS = 0V to VDD
ΔRON –40°C to +85°C 0.4 Ω
channels ISD = 10mA
–40°C to +125°C 0.5 Ω
25°C 0.85 Ω
RON VS = 0V to VDD
On-resistance flatness –40°C to +85°C 1.6 Ω
FLAT ISD = 10mA
–40°C to +125°C 1.6 Ω
VDD = 5V 25°C –0.08 ±0.005 0.08 nA
Switch Off
IS(OFF) Source off leakage current(1) –40°C to +85°C –0.3 0.3 nA
VD = 4.5V / 1.5V
VS = 1.5V / 4.5V –40°C to +125°C –0.9 0.9 nA
VDD = 5V 25°C –0.1 ±0.01 0.1 nA
Switch Off
ID(OFF) Drain off leakage current(1) –40°C to +85°C –1 1 nA
VD = 4.5V / 1.5V
VS = 1.5V / 4.5V –40°C to +125°C –5.5 5.5 nA
25°C –0.025 ±0.003 0.025 nA
VDD = 5V
ID(ON)
Channel on leakage current Switch On –40°C to +85°C –0.5 0.5 nA
IS(ON)
VD = VS = 2.5V
–40°C to +125°C –0.95 0.95 nA
25°C –0.1 ±0.01 0.1 nA
VDD = 5V
ID(ON)
Channel on leakage current Switch On –40°C to +85°C –0.75 0.75 nA
IS(ON)
VD = VS = 4.5V / 1.5V
–40°C to +125°C –4 4 nA

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6.5 Electrical Characteristics (VDD = 5V ±10 %) (continued)

at TA = 25°C, VDD = 5V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
LOGIC INPUTS (EN, A0, A1, A2)
VIH Input logic high –40°C to +125°C 1.49 5.5 V
VIL Input logic low –40°C to +125°C 0 0.87 V
IIH
Input leakage current 25°C ±0.005 µA
IIL
IIH
Input leakage current –40°C to +125°C ±0.05 µA
IIL
CIN Logic input capacitance 25°C 1 pF
CIN Logic input capacitance –40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.008 µA
IDD VDD supply current Logic inputs = 0V or 5.5V
–40°C to +125°C 1 µA
DYNAMIC CHARACTERISTICS
25°C 14 ns
VS = 3V
tTRAN Transition time between channels –40°C to +85°C 18 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 19 ns
25°C 8 ns
tOPEN VS = 3V
Break before make time –40°C to +85°C 1 ns
(BBM) RL = 200Ω, CL = 15pF
–40°C to +125°C 1 ns
25°C 12 ns
VS = 3V
tON(EN) Enable turn-on time –40°C to +85°C 19 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 20 ns
25°C 6 ns
VS = 3V
tOFF(EN) Enable turn-off time –40°C to +85°C 8 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 9 ns
VS = 1V
QC Charge Injection 25°C –1 pC
RS = 0Ω, CL = 1nF
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
OISO Off Isolation
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
XTALK Crosstalk
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
BW Bandwidth RL = 50Ω, CL = 5pF 25°C 90 MHz
CSOFF Source off capacitance f = 1MHz 25°C 7 pF
CDOFF Drain off capacitance f = 1MHz 25°C 60 pF
CSON
On capacitance f = 1MHz 25°C 65 pF
CDON

(1) When VS is 4.5V, VD is 1.5V, and vice versa.

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6.6 Electrical Characteristics (VDD = 3.3V ±10 %)

at TA = 25°C, VDD = 3.3V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
25°C 4 8.75 Ω
VS = 0V to VDD
RON On-resistance –40°C to +85°C 9.5 Ω
ISD = 10mA
–40°C to +125°C 9.75 Ω
25°C 0.13 Ω
On-resistance matching between VS = 0V to VDD
ΔRON –40°C to +85°C 0.4 Ω
channels ISD = 10mA
–40°C to +125°C 0.5 Ω
25°C 1.9 Ω
RON VS = 0V to VDD
On-resistance flatness –40°C to +85°C 2 Ω
FLAT ISD = 10mA
–40°C to +125°C 2.2 Ω
VDD = 3.3V 25°C –0.05 ±0.001 0.05 nA
Switch Off
IS(OFF) Source off leakage current –40°C to +85°C –0.1 0.1 nA
VD = 3V / 1V
VS = 1V / 3V –40°C to +125°C –0.5 0.5 nA
VDD = 3.3V 25°C –0.1 ±0.005 0.1 nA
Switch Off
ID(OFF) Drain off leakage current –40°C to +85°C –0.5 0.5 nA
VD = 3V / 1V
VS = 1V / 3V –40°C to +125°C –1.5 1.5 nA
25°C –0.1 ±0.005 0.1 nA
VDD = 3.3V
ID(ON)
Channel on leakage current Switch On –40°C to +85°C –0.5 0.5 nA
IS(ON)
VD = VS = 3V / 1V
–40°C to +125°C –1.5 1.5 nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH Input logic high –40°C to +125°C 1.35 5.5 V
VIL Input logic low –40°C to +125°C 0 0.8 V
IIH
Input leakage current 25°C ±0.005 µA
IIL
IIH
Input leakage current –40°C to +125°C ±0.05 µA
IIL
CIN Logic input capacitance 25°C 1 pF
CIN Logic input capacitance –40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.006 µA
IDD VDD supply current Logic inputs = 0V or 5.5V
–40°C to +125°C 1 µA
DYNAMIC CHARACTERISTICS
25°C 15 ns
VS = 2V
tTRAN Transition time between channels –40°C to +85°C 23 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 23 ns
25°C 8 ns
tOPEN VS = 2V
Break before make time –40°C to +85°C 1 ns
(BBM) RL = 200Ω, CL = 15pF
–40°C to +125°C 1 ns
25°C 14 ns
VS = 2V
tON(EN) Enable turn-on time –40°C to +85°C 25 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 25 ns
25°C 7 ns
VS = 2V
tOFF(EN) Enable turn-off time –40°C to +85°C 12 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 12 ns

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6.6 Electrical Characteristics (VDD = 3.3V ±10 %) (continued)

at TA = 25°C, VDD = 3.3V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
VS = 1V
QC Charge Injection 25°C –2 pC
RS = 0Ω, CL = 1nF
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
OISO Off Isolation
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
XTALK Crosstalk
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
BW Bandwidth RL = 50Ω, CL = 5pF 25°C 90 MHz
CSOFF Source off capacitance f = 1MHz 25°C 7 pF
CDOFF Drain off capacitance f = 1MHz 25°C 60 pF
CSON
On capacitance f = 1MHz 25°C 65 pF
CDON

6.7 Electrical Characteristics (VDD = 2.5V ±10 %), (VSS = –2.5V ±10 %)
at TA = 25°C, VDD = +2.5V, VSS = –2.5V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
25°C 2.5 4 Ω
VS = VSS to VDD
RON On-resistance –40°C to +85°C 4.5 Ω
ISD = 10mA
–40°C to +125°C 4.9 Ω
25°C 0.13 Ω
On-resistance matching between VS = VSS to VDD
ΔRON –40°C to +85°C 0.4 Ω
channels ISD = 10mA
–40°C to +125°C 0.5 Ω
25°C 0.85 Ω
RON VS = VSS to VDD
On-resistance flatness –40°C to +85°C 1.6 Ω
FLAT ISD = 10mA
–40°C to +125°C 1.6 Ω
VDD = +2.5V, VSS = –2.5V 25°C –0.08 ±0.005 0.08 nA
Switch Off
IS(OFF) Source off leakage current –40°C to +85°C –0.3 0.3 nA
VD = +2V / –1V
VS = –1V / +2V –40°C to +125°C –0.9 0.9 nA
VDD = +2.5V, VSS = –2.5V 25°C –0.1 ±0.01 0.1 nA
Switch Off
ID(OFF) Drain off leakage current –40°C to +85°C –1 1 nA
VD = +2V / –1V
VS = –1V / +2V –40°C to +125°C –5.5 5.5 nA
25°C –0.1 ±0.01 0.1 nA
VDD = +2.5V, VSS = –2.5V
ID(ON)
Channel on leakage current Switch On –40°C to +85°C –0.75 0.75 nA
IS(ON)
VD = VS = +2V / –1V
–40°C to +125°C –4 4 nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH Input logic high –40°C to +125°C 1.2 2.75 V
VIL Input logic low –40°C to +125°C 0 0.73 V
IIH
Input leakage current 25°C ±0.005 µA
IIL
IIH
Input leakage current –40°C to +125°C ±0.05 µA
IIL
CIN Logic input capacitance 25°C 1 pF

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6.7 Electrical Characteristics (VDD = 2.5V ±10 %), (VSS = –2.5V ±10 %) (continued)
at TA = 25°C, VDD = +2.5V, VSS = –2.5V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
CIN Logic input capacitance –40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.008 µA
IDD VDD supply current Logic inputs = 0V or 2.75V
–40°C to +125°C 1 µA
25°C 0.008 µA
ISS VSS supply current Logic inputs = 0V or 2.75V
–40°C to +125°C 1 µA
DYNAMIC CHARACTERISTICS
25°C 14 ns
VS = 1.5V
tTRAN Transition time between channels –40°C to +85°C 21 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 21 ns
25°C 8 ns
tOPEN VS = 1.5V
Break before make time –40°C to +85°C 1 ns
(BBM) RL = 200Ω, CL = 15pF
–40°C to +125°C 1 ns
25°C 13 ns
VS = 1.5V
tON(EN) Enable turn-on time –40°C to +85°C 21 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 21 ns
25°C 8 ns
VS = 1.5V
tOFF(EN) Enable turn-off time –40°C to +85°C 11 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 12 ns
VS = –1V
QC Charge Injection 25°C –2.5 pC
RS = 0Ω, CL = 1nF
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
OISO Off Isolation
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
XTALK Crosstalk
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
BW Bandwidth RL = 50Ω, CL = 5pF 25°C 85 MHz
CSOFF Source off capacitance f = 1MHz 25°C 7 pF
CDOFF Drain off capacitance f = 1MHz 25°C 60 pF
CSON
On capacitance f = 1MHz 25°C 65 pF
CDON

6.8 Electrical Characteristics (VDD = 1.8V ±10 %)

at TA = 25°C, VDD = 1.8V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
25°C 40 Ω
VS = 0V to VDD
RON On-resistance –40°C to +85°C 80 Ω
ISD = 10mA
–40°C to +125°C 80 Ω
25°C 0.3 Ω
On-resistance matching between VS = 0V to VDD
ΔRON –40°C to +85°C 1.5 Ω
channels ISD = 10mA
–40°C to +125°C 1.5 Ω

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6.8 Electrical Characteristics (VDD = 1.8V ±10 %) (continued)

at TA = 25°C, VDD = 1.8V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
VDD = 1.98V 25°C –0.05 ±0.003 0.05 nA
Switch Off
IS(OFF) Source off leakage current –40°C to +85°C –0.1 0.1 nA
VD = 1.62V / 1V
VS = 1V / 1.62V –40°C to +125°C –0.5 0.5 nA
VDD = 1.98V 25°C –0.1 ±0.005 0.1 nA
Switch Off
ID(OFF) Drain off leakage current –40°C to +85°C –0.3 0.3 nA
VD = 1.62V / 1V
VS = 1V / 1.62V –40°C to +125°C –1.5 1.5 nA
25°C –0.1 ±0.003 0.1 nA
VDD = 1.98V
ID(ON)
Channel on leakage current Switch On –40°C to +85°C –0.5 0.5 nA
IS(ON)
VD = VS = 1.62V / 1V
–40°C to +125°C –2 2 nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH Input logic high –40°C to +125°C 1.07 5.5 V
VIL Input logic low –40°C to +125°C 0 0.68 V
IIH
Input leakage current 25°C ±0.005 µA
IIL
IIH
Input leakage current –40°C to +125°C ±0.05 µA
IIL
CIN Logic input capacitance 25°C 1 pF
CIN Logic input capacitance –40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.001 µA
IDD VDD supply current Logic inputs = 0V or 5.5V
–40°C to +125°C 0.85 µA
DYNAMIC CHARACTERISTICS
25°C 28 ns
VS = 1V
tTRAN Transition time between channels –40°C to +85°C 48 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 48 ns
25°C 16 ns
tOPEN VS = 1V
Break before make time –40°C to +85°C 1 ns
(BBM) RL = 200Ω, CL = 15pF
–40°C to +125°C 1 ns
25°C 28 ns
VS = 1V
tON(EN) Enable turn-on time –40°C to +85°C 48 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 48 ns
25°C 16 ns
VS = 1V
tOFF(EN) Enable turn-off time –40°C to +85°C 27 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 27 ns
VS = 1V
QC Charge Injection 25°C –0.5 pC
RS = 0Ω, CL = 1nF
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
OISO Off Isolation
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
XTALK Crosstalk
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
BW Bandwidth RL = 50Ω, CL = 5pF 25°C 80 MHz
CSOFF Source off capacitance f = 1MHz 25°C 7 pF

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6.8 Electrical Characteristics (VDD = 1.8V ±10 %) (continued)

at TA = 25°C, VDD = 1.8V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
CDOFF Drain off capacitance f = 1MHz 25°C 65 pF
CSON
On capacitance f = 1MHz 25°C 70 pF
CDON

6.9 Electrical Characteristics (VDD = 1.2V ±10 %)

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
25°C 70 Ω
VS = 0V to VDD
RON On-resistance –40°C to +85°C 105 Ω
ISD = 10mA
–40°C to +125°C 105 Ω
25°C 0.15 Ω
On-resistance matching between VS = 0V to VDD
ΔRON –40°C to +85°C 1.5 Ω
channels ISD = 10mA
–40°C to +125°C 1.5 Ω
VDD = 1.32V 25°C –0.05 ±0.003 0.05 nA
Switch Off
IS(OFF) Source off leakage current(1) –40°C to +85°C –0.1 0.1 nA
VD = 1V / 0.8V
VS = 0.8V / 1V –40°C to +125°C –0.5 0.5 nA
VDD = 1.32V 25°C –0.1 ±0.003 0.1 nA
Switch Off
ID(OFF) Drain off leakage current(1) –40°C to +85°C –0.3 0.3 nA
VD = 1V / 0.8V
VS = 0.8V / 1V –40°C to +125°C –1.5 1.5 nA
25°C –0.1 ±0.003 0.1 nA
VDD = 1.32V
ID(ON)
Channel on leakage current Switch On –40°C to +85°C –0.3 0.3 nA
IS(ON)
VD = VS = 1V / 0.8V
–40°C to +125°C –1.5 1.5 nA
LOGIC INPUTS (EN, A0, A1, A2)
VIH Input logic high –40°C to +125°C 0.96 5.5 V
VIL Input logic low –40°C to +125°C 0 0.36 V
IIH
Input leakage current 25°C ±0.005 µA
IIL
IIH
Input leakage current –40°C to +125°C ±0.05 µA
IIL
CIN Logic input capacitance 25°C 1 pF
CIN Logic input capacitance –40°C to +125°C 2 pF
POWER SUPPLY
25°C 0.001 µA
IDD VDD supply current Logic inputs = 0V or 5.5V
–40°C to +125°C 0.7 µA
DYNAMIC CHARACTERISTICS
25°C 60 ns
VS = 1V
tTRAN Transition time between channels –40°C to +85°C 210 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 210 ns
25°C 28 ns
tOPEN VS = 1V
Break before make time –40°C to +85°C 1 ns
(BBM) RL = 200Ω, CL = 15pF
–40°C to +125°C 1 ns
25°C 60 ns
VS = 1V
tON(EN) Enable turn-on time –40°C to +85°C 190 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 190 ns

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6.9 Electrical Characteristics (VDD = 1.2V ±10 %) (continued)

PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
25°C 45 ns
VS = 1V
tOFF(EN) Enable turn-off time –40°C to +85°C 150 ns
RL = 200Ω, CL = 15pF
–40°C to +125°C 150 ns
VS = 1V
QC Charge Injection 25°C –0.5 pC
RS = 0Ω, CL = 1nF
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
OISO Off Isolation
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
RL = 50Ω, CL = 5pF
25°C –65 dB
f = 1MHz
XTALK Crosstalk
RL = 50Ω, CL = 5pF
25°C –45 dB
f = 10MHz
BW Bandwidth RL = 50Ω, CL = 5pF 25°C 80 MHz
CSOFF Source off capacitance f = 1MHz 25°C 7 pF
CDOFF Drain off capacitance f = 1MHz 25°C 65 pF
CSON
On capacitance f = 1MHz 25°C 70 pF
CDON

(1) When VS is 1V, VD is 0.8V, and vice versa.

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6.10 Typical Characteristics

at TA = 25°C, VDD = 5V (unless otherwise noted)

6 6
VDD = 3V 5.5
5 5
VDD = 3.3V 4.5
On Resistance (:)

On Resistance (:)
4 4 TA = 85qC TA = 125qC
VDD = 4.5V 3.5
3 VDD = 5.5V 3
2.5
2 2
1.5
1 1 TA = -40qC TA = 25qC
0.5
0 0
0 1 2 3 4 5 5.5 0 1 2 3 4 5
Source or Drain Voltage (V) D001
Source or Drain Voltage (V) D002

TA = 25°C VDD= 5V
Figure 6-1. On-Resistance vs Source or Drain Voltage Figure 6-2. On-Resistance vs Temperature

6 8

7
5
TA = 85qC TA = 125qC
VDD = 2.25V 6
On Resistance (:)

On Resistance (:)

4 VSS = -2.25V
5

3 4

3
2
VDD = 2.75V 2
1 VSS = -2.75V TA = -40qC TA = 25qC
1

0 0
-3 -2 -1 0 1 2 3 0 0.5 1 1.5 2 2.5 3 3.5
Source or Drain Voltage (V) D003
Source or Drain Voltage (V) D004

TA = 25°C VDD= 3.3V

Figure 6-3. On-Resistance vs Source or Drain Voltage Figure 6-4. On-Resistance vs Temperature

80 40
75 VDD = 1.08V
70 30
65
60 20
On Resistance (:)

55 VDD = 1.32V VDD = 1.32V VDD = 1.98V VDD = 3.63V

On-Leakage (pA)

50 10
45
40 0
35 VDD = 1.62V
30 -10
25
20 -20
15 VDD = 1.98V
10 -30
5
0 -40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.5 1 1.5 2 2.5 3 3.5 4
Source or Drain Voltage (V) D005
Source or Drain Voltage (V) D006

TA = 25°C TA = 25°C
Figure 6-5. On-Resistance vs Source or Drain Voltage Figure 6-6. On-Leakage vs Source or Drain Voltage

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6.10 Typical Characteristics (continued)

at TA = 25°C, VDD = 5V (unless otherwise noted)

400 2

300 1.5

200 VDD = 2.5V VDD = 5V 1

Leakage Current (nA)

VSS = -2.5V VSS = 0V
On-Leakage (pA)

IS(OFF)
100 0.5

0 0

-100 -0.5
ID(OFF)
-200 -1
ID(ON)
-300 -1.5

-400 -2
-3 -2 -1 0 1 2 3 4 5 -40 -20 0 20 40 60 80 100 120
Source or Drain Voltage (V) D007
Temperature (qC) D008

TA = 25°C VDD= 3.3V

Figure 6-7. On-Leakage vs Source or Drain Voltage Figure 6-8. Leakage Current vs Temperature

3.5 1

2.5 VDD = 5V
0.8
Leakage Current (nA)

1.5
Supply Current (PA)

IS(OFF) VDD = 3.3V

0.6
0.5

-0.5
0.4 VDD = 1.8V
ID(OFF)
-1.5
ID(ON) 0.2
-2.5
VDD = 1.2V
-3.5 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (qC) D009
Temperature (qC) D010

VDD= 5V VSEL= 5.5V

Figure 6-9. Leakage Current vs Temperature Figure 6-10. Supply Current vs Temperature

1400 20

1200 15

10 VDD = 3.3V VDD = 5V

Charge Injection (pC)

1000
Supply Current (PA)

VSS = 0V VSS = 0V
5
800
0
600
VDD = 5V -5
400 VDD = 2.5V
-10
VSS = -2.5V
200 -15
VDD = 3.3V
0 -20
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -3 -2 -1 0 1 2 3 4 5
Logic Voltage (V) D011
Source or Drain Voltage (V) D012

TA = 25°C TA = 25°C
Figure 6-11. Supply Current vs Logic Voltage Figure 6-12. Charge Injection vs Source or Drain Voltage

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6.10 Typical Characteristics (continued)

at TA = 25°C, VDD = 5V (unless otherwise noted)

5 30

27
3 24
Charge Injection (pC)

VDD = 1.2V 21
1

Time (ns)
18
TON
15
-1
12
VDD = 1.8V
9
-3 TOFF
6

3
-5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
0 0.5 1 1.5 2 VDD - Supply Voltage (V)
Source or Drain Voltage (V) D014
D013
TA = 25°C
TA = 25°C
Figure 6-14. TON (EN) and TOFF (EN) vs Supply Voltage
Figure 6-13. Charge Injection vs Source or Drain Voltage

20 30

25
16
TON
20
12
Time (ns)

TTRANSITION_FALLING
Time (ns)

15
TOFF
8
10
TTRANSITION_RISING
4 5

0
0
0.5 1.5 2.5 3.5 4.5 5.5
-60 -30 0 30 60 90 120 150 VDD - Supply Voltage (V)
TA - Temperature (qC) D016
D015
TA = 25°C
VDD= 5V
Figure 6-16. TTRANSITION vs Supply Voltage
Figure 6-15. TON (EN) and TOFF (EN) vs Temperature
0
-10
-20
-30
-40
Gain (dB)

-50
-60
-70
-80 TMUX1208 Bandwidth
-90 TMUX1209 Bandwidth
Off-Isolation
-100
100k 1M 10M 100M
Frequency (Hz) D006

TA = 25°C
Figure 6-17. Frequency Response

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7 Detailed Description
7.1 Overview
7.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the
device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote
on-resistance. The measurement setup used to measure RON is shown in Figure 7-1. Voltage (V) and current
(ISD) are measured using this setup, and RON is computed with RON = V / ISD:

ISD
Sx D

VS

Figure 7-1. On-Resistance Measurement Setup

7.1.2 Off-Leakage Current

There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 7-2.

VDD VSS VDD VSS

VDD VSS VDD VSS

Is (OFF)
S1 S1
A
S2 ID (OFF)
S2 D
D
A
VS
S8
S8

VS
VD VD

GND GND

Figure 7-2. Off-Leakage Measurement Setup

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7.1.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).

VDD VSS VDD VSS

VDD VSS VDD VSS

IS (ON)
S1 S1
N.C. A
S2 ID (ON) S2
D D
A N.C.
S8 S8
Vs
VS VS

VD

GND GND

Figure 7-3. On-Leakage Measurement Setup

7.1.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 7-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.

VDD VSS
0.1…F 0.1…F

VDD
VDD VSS
ADDRE SS
tr < 5ns tf < 5ns
DRIVE
(VSEL) VIH S1
VIL VS OUTPUT
D
0V S2

S8
RL CL

tTRAN SITION tTRAN SITION

A0
90%
A1
OUTPUT
VSEL
A2
10% GND

0V

Figure 7-4. Transition-Time Measurement Setup

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7.1.5 Break-Before-Make Delay

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 7-5 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD VSS
0.1…F 0.1…F

VDD VSS

VDD
S1
ADDRE SS VS OUTPUT
DRIVE tr < 5ns tf < 5ns D
(VSEL) S2-S7
0V
RL CL
S8

90%
Output
A0
tBBM 1 tBBM 2
0V A1
tOPEN (BBM) = min ( tBBM 1, tBBM 2) VSEL
A2
GND

Figure 7-5. Break-Before-Make Delay Measurement Setup

7.1.6 Turn-On and Turn-Off Time

Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 7-6 shows
the setup used to measure turn-on time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 7-6 shows
the setup used to measure turn-off time, denoted by the symbol tOFF(EN).
VDD VSS
0.1…F 0.1…F

VDD
VDD VSS

tr < 5ns tf < 5ns

ENABL E
S1
DRIVE VS OUTPUT
VIH
(VEN) D
VIL
S2
0V RL CL
S8

tON (EN) tOFF (EN)

A0
EN
90%
A1
OUTPUT
VEN
A2
10% GND
0V

Figure 7-6. Turn-On and Turn-Off Time Measurement Setup

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7.1.7 Charge Injection

The TMUX1108 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. Figure 7-7 shows the setup used to measure charge injection from source (Sx) to drain (D).

VDD VSS
0.1…F 0.1…F

VDD VSS
VDD

VS S1
OUTPUT
D
VOUT
0V S2
CL
S8

Output
VOUT
VS QC = CL × VOUT A0
EN

A1
VEN
A2
GND

Figure 7-7. Charge-Injection Measurement Setup

7.1.8 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 7-8 shows the setup used to measure off isolation. Use the off isolation
equation to compute off isolation.

VDD VSS
0.1µF 0.1µF

NETWORK
VDD VSS ANALYZER
VS

S 50Q

VSIG

VOUT

RL
SX/DX
50Q

GND
RL
50Q

Figure 7-8. Off Isolation Measurement Setup

§V ·
Off Isolation 20 ˜ Log ¨ OUT ¸
© VS ¹ (1)

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7.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 7-9 shows the setup used to measure, and the equation used to
compute crosstalk.

VDD VSS
0.1µF 0.1µF

NETWORK
VDD VSS
ANALYZER

S1
VOUT
RL
D
50Q
VS
RL
S2 50Q

50Q

VSIG SX

RL GND
50Q

Figure 7-9. Crosstalk Measurement Setup

§V ·
Channel-to-Channel Crosstalk 20 ˜ Log ¨ OUT ¸
© VS ¹ (2)

7.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure
7-10 shows the setup used to measure bandwidth.

VDD VSS
0.1µF 0.1µF

NETWORK
VDD VSS ANALYZER
VS

S 50Q

VSIG

VOUT

RL
50Q
GND

Figure 7-10. Bandwidth Measurement Setup

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7.2 Functional Block Diagram

The TMUX1108 is an 8:1, single-ended (1-ch.), analog mux. Each channel is turned on or turned off based on
the state of the address lines and enable pin.

TMUX1108

S1
S2
S3
S4
D
S5
S6
S7
S8

1-OF-8
DECODER

A0 A1 A2 EN

Figure 7-11. TMUX1108 Functional Block Diagram

7.3 Feature Description

7.3.1 Bidirectional Operation
The TMUX1108 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
7.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1108 ranges from VSS to VDD.
7.3.3 1.8V Logic Compatible Inputs
The TMUX1108 has 1.8V logic compatible control for all logic control inputs. The logic input thresholds scale with
supply but still provide 1.8V logic control when operating at 5.5V supply voltage. 1.8V logic level inputs allows
the TMUX1108 to interface with processors that have lower logic I/O rails and eliminates the need for an external
translator, which saves both space and BOM cost. For more information on 1.8V logic implementations refer to
Simplifying Design with 1.8V logic Muxes and Switches.
7.3.4 Fail-Safe Logic
The TMUX1108 support Fail-Safe Logic on the control input pins (EN, A0, A1, A2) allowing for operation up to
5.5V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied
before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity
by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1108 to be ramped to 5.5V while VDD = 0V. Additionally, the feature
enables operation of the TMUX1108 with VDD = 1.2V while allowing the select pins to interface with a logic level
of another device up to 5.5V.

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7.3.5 Ultra-low Leakage Current

The TMUX1108 provides extremely low on-leakage and off-leakage currents. The TMUX1108 is capable of
switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset
error because of the ultra-low leakage currents. Figure 7-12 shows typical leakage currents of the TMUX1108
versus temperature.
3.5

2.5

Leakage Current (nA)

1.5
IS(OFF)
0.5

-0.5
ID(OFF)
-1.5
ID(ON)
-2.5

-3.5
-40 -20 0 20 40 60 80 100 120
Temperature (qC) D009

Figure 7-12. Leakage Current vs Temperature

7.3.6 Ultra-low Charge Injection

The TMUX1108 has a transmission gate topology, as shown in Figure 7-13. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.

OFF ON

CGSN CGDN

S D

CGSP CGDP

OFF ON

Figure 7-13. Transmission Gate Topology

The TMUX1108 has special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to as low as 1pC at VS = 1V as shown in Figure 7-14.

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20

15

10 VDD = 3.3V VDD = 5V

Charge Injection (pC)

VSS = 0V VSS = 0V
5

-5

-10 VDD = 2.5V

VSS = -2.5V
-15

-20
-3 -2 -1 0 1 2 3 4 5
Source or Drain Voltage (V) D012

Figure 7-14. Charge Injection vs Source or Drain Voltage

7.4 Device Functional Modes

When the EN pin of the TMUX1108 is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the
address lines.
7.4.1 Truth Tables
Table 7-1 shows the truth table for the TMUX1108.
Table 7-1. TMUX1108 Truth Table
Selected Channel Connected To Drain (D)
EN A2 A1 A0
Pin
0 X(1) X(1) X(1) All channels are off
1 0 0 0 S1
1 0 0 1 S2
1 0 1 0 S3
1 0 1 1 S4
1 1 0 0 S5
1 1 0 1 S6
1 1 1 0 S7
1 1 1 1 S8

(1) X denotes do not care.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The TMUX11xx family offers ultra-low input/output leakage currents and low charge injection. These devices
operate up to 5.5V, and offer true rail-to-rail input and output. The TMUX1108 has a low on-capacitance which
allows faster settling time when multiplexing inputs in the time domain. These features make the TMUX11xx a
family of precision, robust, high-performance analog multiplexer for low-voltage applications.
8.2 Typical Application
Figure 8-1 shows a 16-bit, 8 input, multiplexed, data-acquisition system. This example is typical in industrial
applications that require low distortion for precision measurements. The circuit uses the ADS8864, a 16-bit,
400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision
amplifier, and an 8 input mux.

VDD
VDD

Bridge Sensor EN

3.3V
S1 REF +
S2 OPA333
-
Thermocouple S3
S4 D
+
...

S5 OPA333 Gain / Filter

Network ADS8864
S6 -
S7
Current
S8
Sensing A2
A1
A0
GND 1.8V Logic
Signals
Photo
LED Detector
TMUX1108
Optical Sensor

Analog Inputs

Figure 8-1. Multiplexing Signals to External ADC

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 8-1.
Table 8-1. Design Parameters
PARAMETERS VALUES
Supply (VDD) 3.3V
I/O signal range 0V to VDD (Rail to Rail)
Control logic thresholds 1.8V compatible

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8.2.2 Detailed Design Procedure

The TMUX1108 can operate without any external components except for the supply decoupling capacitors. If
the device desired power-up state is disabled, the enable pin should have a weak pull-down resistor and be
controlled by the MCU via GPIO. All inputs being muxed to the ADC must fall within the recommend operating
conditions of the TMUX1108 including signal range and continuous current. For this design with a supply of 3.3V
the signal range can be 0V to 3.3V and the maximum continuous current can be 30mA.
The design example highlights a multiplexed, data-acquisition system for highest system linearity and fast
settling. The overall system block diagram is shown in Figure 8-1. The circuit is a multichannel, data-acquisition
signal chain consisting of an input low-pass filter, mux, mux output buffer, SAR ADC driver, and the reference
buffer. The architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost
solution.
8.2.3 Application Curve

40

30

20
VDD = 1.32V VDD = 1.98V VDD = 3.63V
On-Leakage (pA)

10

-10

-20

-30

-40
0 0.5 1 1.5 2 2.5 3 3.5 4
Source or Drain Voltage (V) D006

TA = 25°C

Figure 8-2. On-Leakage vs Source or Drain Voltage

8.3 Power Supply Recommendations

The TMUX1108 operates across a wide supply range of 1.08V to 5.5V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD
supply to other components. Good power-supply decoupling is important to achieve optimum performance.
For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1μF to 10μF from VDD
to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using
low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems or systems in harsh noise environments, connecting the capacitors to the device pins
without vias may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance
and is beneficial for connections to ground planes.

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8.4 Layout
8.4.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self-inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 8-3 shows progressively better techniques of rounding corners. Only the last example
(BEST) maintains constant trace width and minimizes reflections.
WORST BETTER BEST

2W
1W min.

Figure 8-3. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance.
Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up
interference from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Figure 8-4 shows an example of a PCB layout with the TMUX1108. Some key considerations are as follows:
• Decouple the VDD pin with a 0.1µF capacitor, placed as close to the pin as possible. Ensure that the capacitor
voltage rating is sufficient for the VDD supply.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
8.4.2 Layout Example

Via to
ground plane
Via to
ground plane

Wide (low inductance) A0 A1

C
trace for power EN A2
C Wide (low inductance)
VSS GND trace for power
Via to
ground plane VDD
S1
S2 S5
S3 TMUX1108 S6
S4 S7
D S8

Figure 8-4. TMUX1108 Layout Example

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9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
• Texas Instruments, Simplifying Design with 1.8V logic Muxes and Switches.
• Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
• Texas Instruments, QFN/SON PCB Attachment.
• Texas Instruments, Quad Flatpack No-Lead Logic Packages.
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2018) to Revision B (February 2024) Page
• Updated Is or Id (Continuous Current) values.................................................................................................... 4
• Added Ipeak values to Recommended Operating Conditions table................................................................... 4

Changes from Revision * (November 2018) to Revision A (November 2018) Page

• Added footnotes to Absolute Maximum Ratings: table.......................................................................................4
• Added RSV (QFN) thermal information to Thermal Information: table............................................................... 5
• Added footnote to clarify test conditions ............................................................................................................7
• Changed leakage current test conditions for dual supply...................................................................................8

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 1-May-2025

PACKAGING INFORMATION

Orderable Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
part number (1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TMUX1108PWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 TM1108
TMUX1108RSVR Active Production UQFN (RSV) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1B2

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without
limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available
for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the
finish value exceeds the maximum column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per
JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the
previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1108PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TMUX1108RSVR UQFN RSV 16 3000 178.0 13.5 2.1 2.9 0.75 4.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMUX1108PWR TSSOP PW 16 2000 356.0 356.0 35.0
TMUX1108RSVR UQFN RSV 16 3000 189.0 185.0 36.0

Pack Materials-Page 2
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RSV 16 UQFN - 0.55 mm max height
1.8 x 2.6, 0.4 mm pitch ULTRA THIN QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4231225/A

www.ti.com
 PACKAGE OUTLINE
RSV0016A SCALE 5.000
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

1.85
B A
1.75

PIN 1 INDEX AREA

2.65
2.55

0.55 C
0.45
SEATING PLANE

0.05 0.05 C
0.00

2X 1.2

SYMM (0.13) TYP

5 ℄ 8
0.45
15X
0.35

4
9

SYMM
2X 1.2 ℄

12X 0.4

1 0.25
12 16X
0.15
0.07 C A B
0.05
16 13
0.55
0.45 PIN 1 ID
(45° X 0.1)

4220314/C 02/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RSV0016A UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

SYMM
(0.7) ℄

16 13 SEE SOLDER MASK

DETAIL

16X (0.2) 1 12

SYMM
12X (0.4) ℄ (2.4)

(R0.05) TYP 4 9

15X (0.6)

5 8
(1.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 25X

0.05 MIN
0.05 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK

EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK

OPENING METAL OPENING

NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4220314/C 02/2020
NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com
 EXAMPLE STENCIL DESIGN
RSV0016A UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD

(0.7)
16 13

16X (0.2) 1 12

SYMM
12X (0.4) ℄ (2.4)

(R0.05) TYP
4 9

15X (0.6)

5 8
SYMM
℄

(1.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 25X

4220314/C 02/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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