Q1: Answer the following questions.

[2 + 3 = 5 Marks]

(a) Describe the main categories of interrupts. Provide situations where each interrupt
type may be encountered.

Interrupts can be categorized into several types, with the most common ones being:

1. Hardware Interrupts:

o Description: Hardware interrupts are initiated by external hardware devices

or system components (such as I/O devices) to signal that they need
attention. These interrupts are generated by hardware components like
keyboards, mice, disk drives, or network interfaces.

o Situations:

 Timer Interrupt: A system clock or timer interrupt occurs at regular

intervals, typically used for task scheduling.

 I/O Interrupt: Generated by input/output devices like a keyboard or

mouse when data is ready to be processed or an event has occurred
(e.g., data read from disk).

 Hardware Faults: For example, memory parity errors or system

overheating, where the system needs to handle the error promptly.

2. Software Interrupts:

o Description: Software interrupts are initiated by software programs or

operating systems to request services or perform specific actions. This
includes system calls and exceptions that occur during program execution.

o Situations:

 System Calls: When a user program requests an operating system

service, such as input/output operations or memory allocation.

 Exceptions: These occur when the program encounters unexpected

situations, like division by zero or invalid memory access. For example,
a program might generate a software interrupt to handle an exception
like an illegal instruction or arithmetic error.

3. Maskable Interrupts:

o Description: Maskable interrupts can be disabled (or "masked") by setting a

specific bit in the interrupt control register. This is useful to prevent certain
interrupts from interrupting the program flow while critical operations are
being performed.

o Situations:
  Example: The system might mask interrupts temporarily during a
critical section where the integrity of data or operations must be
preserved, such as during a context switch in multitasking
environments.

4. Non-Maskable Interrupts (NMI):

o Description: Non-maskable interrupts cannot be disabled or ignored. They

are used for critical system events that require immediate attention.

o Situations:

 Example: A hardware fault like a memory parity error or a power

failure where the system cannot afford to ignore or delay the
response.

(b) Imagine a benchmark program operating on a system with a clock rate of 30 MHz. The
program involves 75,000 executable instructions, each categorized by instruction type, and
each type has a designated count of clock cycles for execution.

Clock Rate: 30 MHz = 30,000,000 cycles per second.

Let's calculate the total execution time for the benchmark program using the given
information.

Given:

 Instruction Types and Counts:

o Integer Arithmetic: 35,000 instructions, 1 cycle per instruction.

o Data Transfer: 20,000 instructions, 2 cycles per instruction.

o Floating Point: 12,000 instructions, 2 cycles per instruction.

o Control Transfer: 8,000 instructions, 2 cycles per instruction.

Step 1: Total Cycles for Each Instruction Type

 Integer Arithmetic: 35,000×1=35,00035,000 \times 1 = 35,00035,000×1=35,000

cycles

 Data Transfer: 20,000×2=40,00020,000 \times 2 = 40,00020,000×2=40,000 cycles

 Floating Point: 12,000×2=24,00012,000 \times 2 = 24,00012,000×2=24,000 cycles

 Control Transfer: 8,000×2=16,0008,000 \times 2 = 16,0008,000×2=16,000 cycles

Step 2: Total Cycles for the Entire Program The total number of cycles for the program is the
sum of cycles for all instruction types:
Total Cycles=35,000+40,000+24,000+16,000=115,000 cycles\text{Total Cycles} = 35,000 +
40,000 + 24,000 + 16,000 = 115,000 \
text{ cycles}Total Cycles=35,000+40,000+24,000+16,000=115,000 cycles

Step 3: Calculate the Execution Time The clock rate is 30 MHz, which is 30,000,000 cycles
per second. We can now calculate the execution time in seconds using the formula:

Execution Time=Total CyclesClock Rate\text{Execution Time} = \frac{\text{Total Cycles}}{\

text{Clock Rate}}Execution Time=Clock RateTotal Cycles
Execution Time=115,00030,000,000 seconds\text{Execution Time} = \frac{115,000}
{30,000,000} \text{ seconds}Execution Time=30,000,000115,000 seconds
Execution Time=0.00383 seconds\text{Execution Time} = 0.00383 \
text{ seconds}Execution Time=0.00383 seconds

So, the benchmark program will take approximately 0.00383 seconds to execute.

Final Answer:

(a) Categories of Interrupts:

 Hardware Interrupts: Triggered by hardware devices (e.g., I/O devices, timer).

 Software Interrupts: Triggered by software requests (e.g., system calls, exceptions).

 Maskable Interrupts: Can be ignored temporarily by setting control registers.

 Non-Maskable Interrupts: Critical interrupts that cannot be ignored (e.g., hardware

failures).

(b) Execution Time for the Benchmark Program:

 The execution time of the program on a 30 MHz system with the given instructions is
0.00383 seconds.

Q2: Answer the following questions. [2 + 3 = 5 MARKS]

(a) The “INgate” company which manufactures Magnetic Disk Drives seeks your help in
evaluating critical metrics using the following inputs:

 Magnetic Disc pack has:

o 16 surfaces

o 256 tracks per surface

o 512 sectors per track

o 512 bytes per sector

i. What is the capacity of the disk pack?

To calculate the total capacity of the disk pack, we multiply the number of surfaces, the
number of tracks per surface, the number of sectors per track, and the number of bytes per
sector.

Capacity of the disk pack=Number of surfaces×Number of tracks per surface×Number of sect

ors per track×Bytes per sector\text{Capacity of the disk pack} = \text{Number of surfaces} \
times \text{Number of tracks per surface} \times \text{Number of sectors per track} \times \
text{Bytes per
sector}Capacity of the disk pack=Number of surfaces×Number of tracks per surface×Number
of sectors per track×Bytes per sector

Substitute the given values:

Capacity=16×256×512×512\text{Capacity} = 16 \times 256 \times 512 \times

512Capacity=16×256×512×512 Capacity=16×256×262,144\text{Capacity} = 16 \times 256 \
times 262,144Capacity=16×256×262,144 Capacity=1,073,741,824 bytes\text{Capacity} =
1,073,741,824 \text{ bytes}Capacity=1,073,741,824 bytes

So, the capacity of the disk pack is 1,073,741,824 bytes, or 1 GB (gigabyte).

ii. What is the number of bits required to address a sector?

The number of bits required to address a sector can be calculated by determining the total
number of sectors on the disk and then finding how many bits are needed to represent that
number.

First, calculate the total number of sectors:

Total sectors=Number of surfaces×Number of tracks per surface×Number of sectors per trac

k\text{Total sectors} = \text{Number of surfaces} \times \text{Number of tracks per
surface} \times \text{Number of sectors per
track}Total sectors=Number of surfaces×Number of tracks per surface×Number of sectors pe
r track

Substitute the given values:

Total sectors=16×256×512\text{Total sectors} = 16 \times 256 \times

512Total sectors=16×256×512 Total sectors=2,097,152\text{Total sectors} =
2,097,152Total sectors=2,097,152

Now, we need to find how many bits are required to represent 2,097,152 sectors. The
number of bits required to address NNN sectors is given by:

Number of bits=log⁡2(N)\text{Number of bits} = \log_2(N)Number of bits=log2(N)

Substitute N=2,097,152N = 2,097,152N=2,097,152:

Number of bits=log⁡2(2,097,152)=21\text{Number of bits} = \log_2(2,097,152) =

21Number of bits=log2(2,097,152)=21

So, 21 bits are required to address a sector.

(b) Following is the code word generated using Hamming code:

 Code word: 0 1 1 0 1 0 1 0 1 0 1 0

This code word contains both data and syndrome bits.

i. Identify the syndrome bits.

In a Hamming code, the syndrome bits (also known as parity bits) are placed at positions
that are powers of 2 (1, 2, 4, 8, etc.). In this case, we are working with a 12-bit code, so the
syndrome bits will be at positions 1, 2, 4, and 8.

Let’s separate the data and syndrome bits:

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Position: 1 2 3 4 5 6 7 8 9 10 11 12

Code Word: 0 1 1 0 1 0 1 0 1 0 1 0

 Syndrome bits are at positions P1P_1P1, P2P_2P2, P4P_4P4, and P8P_8P8:

o P1P_1P1 = 0

o P2P_2P2 = 1

o P4P_4P4 = 0

o P8P_8P8 = 0

So, the syndrome bits are 0, 1, 0, 0.

ii. What is the decimal equivalent of the data?

The data bits are the bits that are not syndrome bits. In this case, the data bits are at
positions 3, 5, 6, 7, 9, 10, 11, and 12:

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Data Bits: 1 1 0 1 1 0 1 0

The data bits are 11011010.

Now, convert this binary number into its decimal equivalent:

110110102=(1×27)+(1×26)+(0×25)+(1×24)+(1×23)+(0×22)+(1×21)+(0×20)11011010_2 = (1 \
times 2^7) + (1 \times 2^6) + (0 \times 2^5) + (1 \times 2^4) + (1 \times 2^3) + (0 \times 2^2)
+ (1 \times 2^1) + (0 \times 2^0)110110102
=(1×27)+(1×26)+(0×25)+(1×24)+(1×23)+(0×22)+(1×21)+(0×20) =128+64+16+8+2=218= 128 +
64 + 16 + 8 + 2 = 218=128+64+16+8+2=218

So, the decimal equivalent of the data is 218.

iii. Is there any error in the data? If so, what is the correct data?

To detect if there's an error in the data, we need to check the syndrome bits. The syndrome
bits are used to detect and correct errors in the Hamming code.

Let’s calculate the syndrome:

 P1P_1P1 checks positions 1, 3, 5, 7, 9, 11.

 P2P_2P2 checks positions 2, 3, 6, 7, 10, 11.

 P4P_4P4 checks positions 4, 5, 6, 7, 12.

 P8P_8P8 checks positions 8, 9, 10, 11, 12.

From the code word, the received syndrome bits are 0, 1, 0, 0.

Now, let's recalculate the syndrome using the bits from the code word.

1. P1P_1P1 calculation:

o Positions 1, 3, 5, 7, 9, 11: 0,1,1,0,1,10, 1, 1, 0, 1, 10,1,1,0,1,1

o Sum: 0+1+1+0+1+1=40 + 1 + 1 + 0 + 1 + 1 = 40+1+1+0+1+1=4 (even), so

P1P_1P1 should be 0.

2. P2P_2P2 calculation:

o Positions 2, 3, 6, 7, 10, 11: 1,1,0,1,0,11, 1, 0, 1, 0, 11,1,0,1,0,1

o Sum: 1+1+0+1+0+1=41 + 1 + 0 + 1 + 0 + 1 = 41+1+0+1+0+1=4 (even), so

P2P_2P2 should be 0 (but it's 1, which indicates an error).

3. P4P_4P4 calculation:
 o Positions 4, 5, 6, 7, 12: 0,1,0,1,00, 1, 0, 1, 00,1,0,1,0

o Sum: 0+1+0+1+0=20 + 1 + 0 + 1 + 0 = 20+1+0+1+0=2 (even), so P4P_4P4

should be 0 (and it is).

4. P8P_8P8 calculation:

o Positions 8, 9, 10, 11, 12: 0,1,0,1,00, 1, 0, 1, 00,1,0,1,0

o Sum: 0+1+0+1+0=20 + 1 + 0 + 1 + 0 = 20+1+0+1+0=2 (even), so P8P_8P8

should be 0 (and it is).

From this analysis, we can see that the error was in the parity bit P2P_2P2.

Correcting the Data:

To correct the data, we need to flip the bit at the error position. In this case, the error is
detected at position 2 (since P2P_2P2 was incorrect), so we flip the bit at position 2.

Original code word: 0 1 1 0 1 0 1 0 1 0 1 0

Flipping position 2 gives: 0 0 1 0 1 0 1 0 1 0 1 0

Now, the corrected data bits are 101010, which is 42 in decimal.

Final Answer:

 Syndrome bits: 0, 1, 0, 0

 Decimal equivalent of data: 218

 Error in the data: Yes. The error is in position 2.

 Corrected data: 42

Q3: Answer the following questions [5 MARKS]

Given:

 The system uses a 32-bit address to address byte-addressable main memory.

 The cache has a 16 KB line size.

 The cache is four-way set-associative.

 The cache stores a 6-bit tag along with data blocks in each cache line.

Let’s break down the questions and solve them step by step:
(a) Calculate the total capacity of main memory in GBytes.

The main memory is byte-addressable, and the address is 32 bits.

 Addressable units: With a 32-bit address, the total number of addressable units
(bytes) is:

Total addressable units=232 bytes\text{Total addressable units} = 2^{32} \

text{ bytes}Total addressable units=232 bytes

Now, to convert bytes to gigabytes (GB), we divide by 2302^{30}230 (since 2302^{30}230

bytes = 1 GB):

Total capacity in GB=232230=22=4 GB\text{Total capacity in GB} = \frac{2^{32}}{2^{30}} =

2^{2} = 4 \text{ GB}Total capacity in GB=230232=22=4 GB

So, the total capacity of the main memory is 4 GB.

(b) Calculate the number of blocks in main memory.

 The cache line size is 16 KB, which is equal to 16×1024=16,38416 \times 1024 =
16,38416×1024=16,384 bytes.

 Since the system is byte-addressable, each block in memory will be of size 16 KB

(same as the cache line size).

Now, the number of blocks in main memory can be calculated by dividing the total capacity
of the main memory by the block size:

Number of blocks=Total capacity of main memoryBlock size=232 bytes16,384 bytes=232214

=218\text{Number of blocks} = \frac{\text{Total capacity of main memory}}{\text{Block size}}
= \frac{2^{32} \text{ bytes}}{16,384 \text{ bytes}} = \frac{2^{32}}{2^{14}} =
2^{18}Number of blocks=Block sizeTotal capacity of main memory=16,384 bytes232 bytes
=214232=218

So, the total number of blocks in main memory is 218=262,1442^{18} =

262,144218=262,144 blocks.

(c) Show the main memory address format with the number of bits needed for each field.

Given the system is 32-bit addressable and uses a 16 KB block size, let's break down the
main memory address format.

1. Block offset:

o The block size is 16 KB = 16×1024=16,38416 \times 1024 =

16,38416×1024=16,384 bytes.
 o To address each byte in a 16 KB block, we need log⁡2(16,384)=14\
log_2(16,384) = 14log2(16,384)=14 bits.

o Block offset = 14 bits.

2. Set index:

o The cache is four-way set-associative, meaning there are 4 cache lines per
set.

o We need to calculate how many sets there are in the cache. To do this, let’s
first determine the number of cache lines.

The total cache size is given by the cache line size (16 KB) multiplied by the number of lines
(we’ll calculate this later in part (e)).

3. Tag:

o The tag size is given as 6 bits.

So, the total address format can be divided into:

 Tag: 6 bits

 Set index: To be calculated in part (d)

 Block offset: 14 bits

(d) Calculate the number of lines per set and number of sets in the cache.

To determine the number of sets, we need the total cache size and the line size.

1. Cache size:

o Since each line is 16 KB, the cache size (which we will calculate next) is the
total number of cache lines multiplied by the cache line size.

2. Number of cache lines:

o The number of cache lines in the cache is the total cache size divided by the
cache line size (16 KB).

3. Number of sets:

o The cache is four-way set-associative, meaning there are 4 lines per set.

o The number of sets is the total number of cache lines divided by 4.

(e) Calculate the total number of lines in cache.

  The number of cache lines can be determined by dividing the total cache size by the
cache line size.

Q4: Answer the following question. [4 + 1 = 5 MARKS]

(a) Mr. Joel proposed a new cache replacement algorithm using two existing cache
memory replacement algorithms: LRU (Least Recently Used) and FIFO (First In First Out).
The new algorithm works in two phases:

 Phase 1 (Clock 0 to 4): LRU is followed.

 Phase 2 (Clock 5 to 9): FIFO is followed.

Given:

 The main memory block sequence is: 3 4 3 6 7 3 8 7 4 3.

 The cache uses associative mapping.

We need to calculate the hit ratio for the new replacement algorithm.

Step 1: Cache configuration

 The cache has 4 lines (L0, L1, L2, L3), and each line can hold one memory block.

 For associative mapping, any memory block can be placed in any cache line.

Phase 1 (Clock 0 to 4): LRU (Least Recently Used)

Let's simulate how the cache evolves with the LRU policy from clock 0 to 4:

 Time 0: Address 3 is accessed.

o Cache is empty. Miss. The cache becomes: [3, -, -, -].

 Time 1: Address 4 is accessed.

o Cache has 3 but not 4. Miss. The cache becomes: [3, 4, -, -].

 Time 2: Address 3 is accessed.

o Cache has 3. Hit. The cache remains: [3, 4, -, -].

 Time 3: Address 6 is accessed.

o Cache has 3 and 4, but not 6. Miss. The cache becomes: [3, 4, 6, -].

 Time 4: Address 7 is accessed.

 o Cache has 3, 4, 6, but not 7. Miss. The cache becomes: [3, 4, 6, 7].

Phase 1 Summary:

 Cache misses: 5 misses (addresses 3, 4, 6, 7, and 3 in the first 4 accesses).

 Cache hits: 1 hit (address 3 in time 2).

Phase 2 (Clock 5 to 9): FIFO (First In First Out)

Now, let’s simulate how the cache evolves with the FIFO policy from clock 5 to 9:

 Time 5: Address 3 is accessed.

o Cache has 3, 4, 6, 7. Hit. The cache remains: [3, 4, 6, 7].

 Time 6: Address 8 is accessed.

o Cache has 3, 4, 6, 7, but not 8. Miss. Using FIFO, we replace the first element
(3). The cache becomes: [8, 4, 6, 7].

 Time 7: Address 7 is accessed.

o Cache has 7. Hit. The cache remains: [8, 4, 6, 7].

 Time 8: Address 4 is accessed.

o Cache has 4. Hit. The cache remains: [8, 4, 6, 7].

 Time 9: Address 3 is accessed.

o Cache has 8, 4, 6, 7, but not 3. Miss. Using FIFO, we replace the first element
(8). The cache becomes: [3, 4, 6, 7].

Phase 2 Summary:

 Cache misses: 3 misses (addresses 8, 7, and 3).

 Cache hits: 2 hits (addresses 7 and 4).

Total Summary:

 Total cache misses: 5 (Phase 1) + 3 (Phase 2) = 8 misses.

 Total cache hits: 1 (Phase 1) + 2 (Phase 2) = 3 hits.

 Total accesses: 10 (5 in Phase 1 and 5 in Phase 2).

Hit Ratio:
The hit ratio is the number of hits divided by the total number of accesses:

Hit Ratio=Total HitsTotal Accesses=310=0.3\text{Hit Ratio} = \frac{\text{Total Hits}}{\

text{Total Accesses}} = \frac{3}{10} = 0.3Hit Ratio=Total AccessesTotal Hits=103=0.3

So, the hit ratio is 0.3 or 30%.

(b) Assume the content of Register A is 10101101. Find out the content of Register A for
the following cases:

Register A = 10101101 (in binary).

i. Arithmetic left shift (one time):

An arithmetic left shift moves all bits to the left by one position and inserts a 0 at the
rightmost bit. The leftmost bit (most significant bit) is shifted out and lost.

 Original Register A: 10101101

 After arithmetic left shift (one time):

o Shift left: 01011010 (shifted left and inserted 0 at the rightmost position).

So, the new content of Register A is 01011010.

ii. Arithmetic right shift (one time):

An arithmetic right shift moves all bits to the right by one position, and the sign bit (the
leftmost bit) is inserted into the leftmost position. For this operation, the sign bit (most
significant bit) is preserved to maintain the number's sign in a signed number system.

 Original Register A: 10101101

 After arithmetic right shift (one time):

o Shift right: 11010110 (the sign bit 1 is shifted into the leftmost position).

So, the new content of Register A is 11010110.

Final Answer:

 Hit Ratio of the new replacement algorithm: 30% (or 0.3).

 Register A after arithmetic left shift: 01011010.

 Register A after arithmetic right shift: 11010110.

Q5: Answer the following questions. [1 + 4 = 5 MARKS]

(a) Register Indirect addressing results in very fast execution but limited memory space
compared to register addressing mode. State True/False with proper justifications.

Answer: False

 Justification:

o Register Indirect Addressing involves using a register to store the address of

the operand in memory. The execution is fast because the processor only
needs to access the register to find the operand's memory address.

o However, Register Indirect Addressing does not result in limited memory

space. In fact, the processor can access any location in memory using the
value stored in the register. On the other hand, register addressing mode is
faster because the operand is directly in the register, but it is limited by the
number of registers available in the processor, which is often a small number
(e.g., 32 or 64 registers).

Hence, the statement that Register Indirect addressing has limited memory space
compared to register addressing is false because indirect addressing does not have a space
limitation like registers.

(b) A RISC-based processor is designed with 32 instructions and 13-bit addresses. The
opcode field of the instruction has a fixed number of bits.

i. There are 60 two-address instructions. How many one-address instructions can be

accommodated?

To answer this, we first need to calculate the total number of bits available for the
instruction format and then determine how many of those can be allocated to one-address
instructions.

 Total bits in the address field: 13 bits (given).

 Number of instructions: 32 instructions, which implies we need at least 5 bits for the
opcode (since 25=322^5 = 3225=32).

 Two-address instructions: There are 60 two-address instructions. Each of these

instructions needs to be split into 5 bits for the opcode and additional bits for the
two addresses (each address field requires 13 bits). So, the size of the instruction for
the two-address type will be:

Instruction size for two-address=5 bits (opcode)+2×13 bits (address)=5+26=31 bits\

text{Instruction size for two-address} = 5 \text{ bits (opcode)} + 2 \times 13 \text{ bits
(address)} = 5 + 26 = 31 \text{ bits}Instruction size for two-address=5 bits (opcode)
+2×13 bits (address)=5+26=31 bits
  Now, we need to determine how many one-address instructions can be
accommodated. These instructions will require 5 bits for the opcode and 1 address
field (13 bits). Therefore, the size of the instruction for the one-address type will be:

Instruction size for one-address=5 bits (opcode)+13 bits (address)=18 bits\text{Instruction

size for one-address} = 5 \text{ bits (opcode)} + 13 \text{ bits (address)} = 18 \
text{ bits}Instruction size for one-address=5 bits (opcode)+13 bits (address)=18 bits

Now, the total size for the instruction set is constrained to 32 bits. We can calculate the
number of one-address instructions that can fit:

Number of one-address instructions=32 bits available18 bits per one-address instruction=32

18≈1.78\text{Number of one-address instructions} = \frac{32 \text{ bits available}}{18 \
text{ bits per one-address instruction}} = \frac{32}{18} \approx 1.78Number of one-
address instructions=18 bits per one-address instruction32 bits available=1832≈1.78

Hence, only 1 one-address instruction can be accommodated within the 32-bit instruction
format.

ii. Draw the instruction format for one-address instruction and two-address instruction.

 One-address instruction format:

o Opcode (5 bits) | Address (13 bits).

o Total size: 5 bits (opcode) + 13 bits (address) = 18 bits.

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| 5 bits Opcode | 13 bits Address |

 Two-address instruction format:

o Opcode (5 bits) | Address 1 (13 bits) | Address 2 (13 bits).

o Total size: 5 bits (opcode) + 13 bits (address 1) + 13 bits (address 2) = 31 bits.

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| 5 bits Opcode | 13 bits Address 1 | 13 bits Address 2 |

iii. List 2 differences between 2-address instruction and 3-address instruction with an
example.
 1. Number of operands:

o Two-address instruction: Operands share the same memory location (the

first operand is used for both input and output). Example: ADD R1, R2 (adds
the contents of R1 and R2, and stores the result in R1).

o Three-address instruction: Each operand is independent, and all operands

have distinct memory locations. Example: ADD R1, R2, R3 (adds the contents
of R2 and R3, and stores the result in R1).

2. Memory access:

o Two-address instruction: May overwrite one of the operands. This can

reduce the flexibility in accessing operands.

o Three-address instruction: All operands are distinct, making it more flexible

since no operand is overwritten.

Q6: Answer the following questions. [3 + 2 = 5 MARKS]

(a) Consider a reservation table for a pipeline with four stages: S0, S1, S2, and S3.

The reservation table indicates which stages are being used at each time step for different
tasks. We are given a table for 4 stages: S0, S1, S2, and S3.

Time 0 1 2 3

S0 XX

S1 X

S2 X

S3 X

(i) Draw the complete pipeline diagram.

A pipeline diagram represents how tasks move through the stages at each time step. Here is
the pipeline diagram for the given reservation table:

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Time | 0 | 1 | 2 | 3 |

-----|-----|-----|-----|-----|

T1 | S0 | S1 | S2 | S3 |
T2 | | S0 | S1 | S2 |

T3 | | | S0 | S1 |

(ii) Draw time-space diagram showing 3 tasks (T1, T2, T3) execution.

The time-space diagram shows when each task is in each stage. In this case, there are three
tasks (T1, T2, T3), and we will track their movement through the pipeline:

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Time | 0 | 1 | 2 | 3 |

-----|-----|-----|-----|-----|

T1 | S0 | S1 | S2 | S3 |

T2 | | S0 | S1 | S2 |

T3 | | | S0 | S1 |

(b) State whether the following statements are True or False with proper justification.

a. RAID 0 is not a true member of the RAID family.

Answer: False

 Justification: RAID 0 is indeed a true member of the RAID family. It is known for
striping, where data is divided into blocks and spread across multiple disks. RAID 0
does not provide redundancy, but it improves performance by parallelizing read and
write operations across multiple disks. It is part of the RAID family despite not
providing fault tolerance.

b. During instruction fetch operation, the instruction is directly transferred to the

instruction register from the main memory before it is decoded.

Answer: True

 Justification: During the instruction fetch operation in most processors, the

instruction is fetched from the main memory and placed into the Instruction Register
(IR) before it is decoded. The IR temporarily holds the instruction so that the CPU can
decode and execute it.

4o mini