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A new gate driver integrated circuit for IGBT devices with advanced
protections

Article in IEEE Transactions on Power Electronics · February 2006

DOI: 10.1109/TPEL.2005.861115 · Source: IEEE Xplore

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38 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 1, JANUARY 2006

A New Gate Driver Integrated Circuit for IGBT

Devices With Advanced Protections
Laurent Dulau, Serge Pontarollo, Anthony Boimond, Jean-François Garnier, Nicole Giraudo, and Olivier Terrasse

Abstract—The aim of this paper is to discuss new solutions in

the design of insulated gate bipolar transistor (IGBT) gate drivers
with advanced protections such as two-level turn-on to reduce
peak current when turning on the device, two-level turn-off to limit
over-voltage when the device is turned off, and an active Miller
clamp function that acts against cross conduction phenomena.
Afterwards, we describe a new circuit which includes a two-level
turn-off driver and an active Miller clamp function. Tests and
results for these advanced functions are discussed, with particular
emphasis on the influence of an intermediate level in a two-level
turn-off driver on overshoot across the IGBT. Fig. 1. IGBT equivalent circuit.
Index Terms—Active Miller clamp, bipolar CMOS DMOS
(BCD), cross conduction, insulated gate bipolar transistor (IGBT),
overshoot, peak current, two-level driver.

I. INTRODUCTION

I NSULATED gate bipolar transistor (IGBT) [1] devices

play a large role in power applications due to their high
current, voltage capability, and ease of driving. The majority
of industrial applications commonly use a three-phase inverter
with a 1200-V IGBT. Driving these devices in medium or
large power applications requires separate, floating, high-, and
low-side drivers with galvanic insulation. Control and protec- Fig. 2. Inductive load schematic for transient analysis.
tion functions are also required to ensure reliable operation
[2]. The challenge in gate driver design is to find solutions to II. IGBT SWITCHING ANALYSIS
the dilemma between the requirement to minimize switching
losses and the requirement to limit di/dt (IGBT collector cur- A. Introduction
rent slope), dv/dt (IGBT collector voltage slope), peak reverse An IGBT combines the advantages of a bipolar transistor and
recovery current at turn-on, and voltage overshoot at turn-off a metal-oxide semiconductor field-effect transistor (MOSFET)
[3]. This paper highlights the essential requirements of the gate [8]. As a first approximation, the IGBT can be modeled as
driver circuits for safe switching of the IGBT. a transistor driven by an -channel power MOSFET
We propose several new features available using bipolar [Fig. 1(b)]. This model is very simple and does not take into
CMOS DMOS (BCD) [4] technology. These features are: account the negative effects on latch-up due to the parasitic
an output driver with a two-level turn-on, in order to reduce transistor [Fig. 1(a)]. But this approach is useful to
peak reverse recovery current; an output driver with two-level explain the principal characteristics of the IGBT. Turn-on and
turn-off for limiting overshoot; and an active Miller clamp turn-off can be analyzed in the simple way by using a typical
function that allows the use of simpler power supply systems, schematic (Fig. 2) including a free-wheeling diode and a re-
and in most cases, avoids having to use a negative gate drive sistor on the gate. IGBT only requires power for turn-on and
to prevent occurring cross conduction [5]. Afterwards, we turn-off stages. A positive gate current ( 0) is necessary
will describe a new integrated circuit that includes, in a single to charge at turn-on the IGBT input capacitance to create an
chip, a two-level turn-off output driver, an active Miller clamp electron channel. Once switched on, the IGBT needs no extra
function, a desaturation protection [6], [7] and the possibility power ( 0) to keep this channel. In the same way at
to use a negative off-state control voltage. Then we will discuss turn-off, a negative gate current ( 0) discharges the IGBT
tests and results for this integrated circuit. input capacitance for removing the electron channel.

Manuscript received December 16, 2004; revised May 11, 2005. Recom-
B. Turn-On Analysis
mended by Associate Editor J. A. Ferreira. The IGBT turn-on stage (a positive step voltage is applied
The authors are with STMicroelectronics, Grenoble F-38019, France (e-mail:
[email protected]). on the input IN), shown in Fig. 3(a), is very similar to a power
Digital Object Identifier 10.1109/TPEL.2005.861115 MOSFET turn-on stage.
0885-8993/$20.00 © 2006 IEEE
DULAU et al.: NEW GATE DRIVER INTEGRATED CIRCUIT 39

Fig. 4. IGBT operating area.

part of the switching losses [3], cannot be reduced by the

Fig. 3. IGBT turn-on and turn-off. driving circuit.

1) The first interval corresponds to the time delay required D. Real Operating Area
to bring the gate voltage (VGE) from zero to its VGEth
The operating point can go outside of the safe operating area
threshold. Both the voltage across the switching device
(Fig. 4) [9], [10] under fast switching slope as dv/dt or di/dt [3]
(VCE) and the current through it are unaffected
due to stray inductances and parasitic capacitors.
during this delay time.
Our main goal in the next section is to propose new solutions
2) The second period starts when the gate voltage has
to protect the IGBT during these abnormal operation conditions.
reached the VGEth threshold and the collector current
begins to increase.
III. ADVANCED PROTECTION AND DRIVING
3) During the third period, known as Miller plateau, the
CONTROL FOR IGBT
input capacitance of the IGBT appears to be infinite. The
collector voltage begins to fall rapidly, while the IGBT A. Reduction of Over-Current at Turn-On
is carrying maximum current. Most of the drive current The gate resistor (RG) controls the IGBT collector current
from the driver is used to discharge the Miller capacitance slope [8]. The choice of this resistor is based on a compro-
CGC. If one considers the diode ( ) as nonideal, then mise between reduced power consumption (which requires a
due to the reverse recovery, you will see a hump on the low value of RG) and a tolerable dv/dt or di/dt in order to limit
VGE curve, as well as in that of the collector current the peak current due to the recovery diode and the electromag-
[3]. netic interference (EMI) [11] generation requiring a high value
4) After this period, the VGE continues to increase exponen- of RG. The latching current depends upon the gate resistance
tially to its final value, which determines the of the value. The manufacturers guarantee a minimum gate resistance
IGBT. At the same time, the VCE attains its lowest value. value to avoid the latching phenomenon. IGBT drivers are gen-
erally implemented using two resistors: one resistor is employed
C. Turn-Off Description
at turn-on and the other one for turn-off. Advanced methods are
The IGBT turn-off stage (a negative step voltage is applied proposed to limit di/dt and dv/dt based on the feedback control
on the input IN), shown in Fig. 3(b), can be divided into four of the IGBT collector current or the collector voltage slope [2],
phases. [9], [12]–[14]. However, it is not easy to achieve these complex
1) During the first phase, the gate voltage, with a constant methods, which require considerable silicon area.
current, begins to decrease until it reaches the value when In order to protect the IGBT from over-current, risk of
the Miller effect occurs. latch-up and to limit the EMI, without incurring any increase
2) In the second phase, due to the Miller effect, the gate in the values of gate resistance and the power consumption, the
voltage remains constant because of the modulation of gate voltage must be increased in two separate stages [15]–[17].
the collector gate capacitance. The collector voltage is in- By increasing the gate to an intermediate stage for a short
creased to its maximum value. time before the final turn-on, the IGBT collector current and
3) After, in the third phase, the collector current begins to its slope di/dt are limited. Hence, the peak current due to the
fall quickly. diode reverse recovery is reduced. A two-level turn-on driver
4) Finally, when the gate voltage is equal to the VGEth can be implemented as seen in Fig. 5 [18]. The low-side driver
threshold, the input MOSFET switches off and the col- is an -channel DMOS. In BCD, the high-voltage -channel
lector current continues to decrease with the tail current MOSFET takes up a lot of area due to the mobility, , which is
that is due to the recombination of minority carriers in superior to , and a minimum length that is much longer than
the substrate. The tail current, which causes the major for the -channel DMOS. Because of these considerations, we
40 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 1, JANUARY 2006

Fig. 5. Two-level turn-on driver [18].

Fig. 6. Two-level turn-off driver [18].

chose to use a Darlington architecture for the high-side To turn off the IGBT, we only have to turn off the current
driver, controlled by a current source. A voltage reference, source and close switches LD1 and M1.
VON, is applied to the LVON input in order to create an So with this schematic, users can adjust the intermediate level
intermediate level during the turn-on stage. Before the turn-on at the output by placing a potential (using a Zener diode, for
stage, LD1 and M1 are on and OUTH OUTL . To example) on the LVON pin, with a value above all of the IGBT
begin the turn-on stage, we open M1 and LD1 and switch on thresholds.
S4. Furthermore, we put the current source on with S0.
The Darlington drives a big current. The output potential B. Reduction of Over-Voltage at Turn-Off
will increase as the output current charges the output capacitor. If there is a short-circuit or over-current in the load, a large
When the potential at point B reaches VON VD (where VD1 voltage overshoot can occur across the IGBT at turn-off and can
is threshold of the diode D1), D1 becomes on. Then, the input exceed the IGBT breakdown voltage [2]. We propose driving
current of the Darlington , which is equal to 10 , flows the IGBT by applying a signal on the gate with two different
to the pin LVON via S4 and D1. The Darlington is no longer stages. By reducing the gate voltage to an intermediate level for
controlled by and is not able to provide the output current. a short time before the final turn-off, the IGBT collector current
The potential of the output stays at a level near VON throughout is limited and hence the potential overshoot is reduced [19].
the duration of the period Tb. After this period has elapsed, A two-level turn-off driver can be implemented using
S4 is switched off and the Darlington is again controlled by a high-side Darlington architecture and a low-side
. The output curve finishes its slope and the output potential with an -DMOS (Fig. 6) [18]. Before the turn-off stage,
finally reaches its maximum value equal to about VH-2 V. the DMOS LD1 and M1 switches are off, is on, and
DULAU et al.: NEW GATE DRIVER INTEGRATED CIRCUIT 41

a latch, and a laterally diffused metal oxide semiconductor

(LDMOS) (see Fig. 8). This switch clamp goes on when the
gate voltage becomes lower than 2 V relative to the GND level.
Then the latch is set and the switch is pulled to ground until the
next turn-on.

IV. NEW DRIVING CIRCUIT

We propose a new family of IGBT gate drivers, which, at
present, is comprised of three integrated circuits. All three ICs
use 1- m BCD3S process. The more complete circuit (Fig. 9)
Fig. 7. Miller clamp principle. includes a desaturation protection, an active Miller clamp, and a
two-level turn-off driver. It can be used with either a single pos-
OUTH OUTL VH, 0 1, 1 1 and 1 0. A itive power supply, or a dual positive/negative supply. Separated
voltage reference, VOFF, is applied on the LVOFF input to source (OUTH) and sink (OUTL) output pins allow the use of
create an intermediate level at turn-off. We put the current different gate resistors for turn-on and turn-off. The source stage
source off with 0 0 in order to have no sourcing current. is built with a bipolar Darlington architecture, whereas
One puts the output of the tri-state switch in a high impedance the sink stage uses a LDMOS architecture. Peak output currents
state by setting the logic signal 1 equal to one and closing are 1.2-A sink, and 0.75-A source in worst case over the full
the DMOS M0 switch. The transistor, T1, changes to temperature range ( 20 C to 125 C). This circuit is especially
on because a current flows from its base, via R0 and M0, to adapted to 1200-V IGBT with current ratings of 25–80 A and
the ground. The collector current of T1 will put the DMOS the die area is only 5.55 mm .
M1 and LD1 in conduction due to the polarization of R2. At An output driver including two-level for turn-on and turn-off
this point, the output, OUTH OUTL, begins to fall. When has been validated as an intellectual property and tested with
the VOFF1 potential is equal to VOFF VD , the diode D2 an output capacitance (Fig. 10). We do not propose integrated
becomes on and the transistor, T1, is off, which cancels circuits including this driver, because the major request by IGBT
the collector current of T1. The DMOS switches M1 and LD1 applications manufacturers is to solve voltage overshoot failure
become off and the output remains at an intermediate level near at turn-off.
VOFF during the duration of the period Ta. After this period,
the tri-state switch becomes on to control the gate of M1 and V. EXPERIMENTAL RESULTS
LD1 ( 1 0 and 1 0). Thus, the output falls to the VL A. Two-Level Turn-Off
potential.
If we want to turn-on the IGBT, we only have to open the In a first application, the circuit drives a pure capacitor and
DMOS LD1 and M1 switches and set the current source to we obtain at the circuit output a signal with an intermediate level
on. This current source provides, via the Darlington, the current close to 11 V (Fig. 11).
at the output that charges the output capacitor to a potential near Then, the two-level turn-off function is validated with IGBT
VH—2 V ( 0 1, 1 1, 1 0). using the schematics given in Fig. 12. The purpose of these mea-
With this schematic, users can adjust the intermediate level surements is to show the influence of VOFF on VCEmax [3].
at the output by putting a potential (using a Zener diode, for This analysis was performed on two types of 1200-V IGBT (50
example) on the LVOFF pin above all the IGBT thresholds. and 25 A). Under high current conditions, with a classical turn-
off, a big overshoot appears for example, over 600 V [Fig. 13(a)]
C. Cross Conduction in Half Bridge with 150 A and the turn-off switching losses
15 mJ on the second type of IGBT. By using a two-level turn-off,
When the high-side IGBT Th in half bridge [Fig. 7(a)] turns
with the same current and an intermediate level VOFF equal to
on, OUT increases from almost 0 to V power with a high dv/dt.
11 V, the overshoot is only 240 V [Fig. 13(b)] with an increase
Following this, the current in the Miller capacitor, CGC, and the
of the turn-off switching losses ( 23 mJ).
voltage on the gate of the low-side Tl, increase. This voltage can
exceed the gate threshold level voltage of Tl and a large current
can flow from Vpower to ground. This resulting voltage spike B. Active Miller Clamp and Cross Conduction
on the low-side IGBT [5]–[10] gate depends upon the level of The tests were performed on a half-bridge configuration using
dv/dt and gate off-state resistance. A negative off-state control two 1200-V 25-A IGBTs. Without an active Miller clamp, a big
voltage is generally used to prevent occurring cross conduction voltage spike appears on the IGBT gate in high dv/dt conditions
[20]. [Fig. 14(a)]. The waveforms in Fig. 14(b) show the impact of
We propose an alternative solution to solve this problem: the active Miller clamp on the voltage spike of the IGBT gate.
by using a dedicated clamp [Fig. 7(b)]. When Tl is off, a The spike is decreased both in amplitude and duration with the
low-impedance path is established with this clamp between active Miller clamp.
the IGBT gate and emitter to derive the Miller current and the Therefore, we can conclude that the active Miller clamp func-
voltage spike on the IGBT gate is greatly reduced. The active tion is suitable for reducing the risk of induced turn-on in high
Miller clamp function is implemented using a comparator, dv/dt conditions.
42 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 1, JANUARY 2006

Fig. 8. Active Miller clamp function.

Fig. 9. IGBT driver block diagram and die.

Fig. 10. Two-level turn-on and turn-off driver results with C = 1 nF,
VON = 12 V and VOFF =11 V.
Fig. 11. Two-level turn-off driver results with C = 1 nF, VOFF = 11 V.
VI. CONCLUSION
or turn-off and to present a solution when the IGBT goes out-
A brief review of the IGBT operation has been presented. The side the safe operating area at both turn-on and turn-off. A new
main objective was to give a description of the IGBT turn-on output driver using BCD technology was implemented to limit
DULAU et al.: NEW GATE DRIVER INTEGRATED CIRCUIT 43

In conclusion, the advanced functions (active Miller clamp

and two-level turn-off driver) and the well-known desaturation
protection proposed inside this integrated circuit allow safe and
reliable operation, with a minimum of external components, in
applications such as motor control.

ACKNOWLEDGMENT
The authors wish to thank U. Jaeger and P. Jensen, DAN-
FOSS, Denmark, for technical exchange on IGBT application
drivers, and A. S. Mackinnie, H. Esch, and A. Recchia, STMi-
croelectronics, for their valuable suggestions.
Fig. 12. Test bench for two-level turn-off driver.

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44 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 1, JANUARY 2006

Laurent Dulau received the M.S. degree in micro- Jean-François Garnier received the Ph.D. degree
electronics, the M.S. degree in electrical engineering, in electronics engineering from the Institut National
and the Ph.D. degree in electronics from the Univer- Polytechnique de Grenoble (INPG), Grenoble,
sity of Bordeaux, Bordeaux, France, in 1994, 1995, France.
and 2000, respectively. He has 15 years of experience in analog and power
From 1994 to 1999, he was a Researcher with electronics. He joined the Discrete and Standard ICs
the IXL Laboratory, University of Bordeaux. His Group (currently Micro Linear and Digital Group),
fields of interest were ASIC design, electronics for STMicroelectronics, Grenoble, in 1999, and is cur-
gas sensors, ADC tests, and video coding. He has rently in charge of defining new innovative products
published in theses research domains more than for power management applications.
ten papers in international journals and conference
proceedings. From 1996 to 1999, he also taught electrical engineering at the
ENSEIRB, Bordeaux. From July 1999 to the end of July 2000, he designed
ST7 microcontrollers for STMicroelectronics, Rousset, France. He joined
STMicroelectronics, Grenoble, France, in August 2000. He is currently a
Designer for power integrated circuits and recently, he has been engaged in
research on plasma display drivers in BCD6SOI process.
Dr. Dulau is a member of the European Power Electronics and Drives Asso-
ciation. Nicole Giraudo received the B.S. degree in bio-
physics from Ecole Technique Supérieure de
Laboratoire (ETSL), Paris, France, in 1973 and the
M.S. degree in solid state physics from the Univer-
Serge Pontarollo received the M.S. degree in sity Joseph Fourier, Grenoble, France, in 1981.
microelectronics from the University of Lyon, Lyon, She joined Thomson Semiconducteurs (currently
France, in 1987. STMicroelectronics), Grenoble, in 1974 as a Device
In 1988, he joined STMicroelectronics, Grenoble, Engineer. Since 1995, she has been responsible for
France, as a designer of analog integrated circuits. He layout in the areas of power management devices,
has worked in the field of power management, RF, ADC converters, and high-speed operational ampli-
and standard functions (operational amplifiers, com- fiers.
parators, voltage references). From 1999 to 2004, he
was a Design Manager for the Power Management
Ics Family. Since January 2005, he has been a De-
sign Manager for standard integrated circuits. He has
published two papers in conference proceedings and holds ten patents.

Anthony Boimond received the M.S. degree in Olivier Terrasse received the B.S. degree in elec-
electrical engineering from the Institut National trical engineering, the B.S. degree in robotics, and the
Polytechnique de Grenoble (INPG), Grenoble, M.S. degree in microelectronics from the Institut Na-
France and from the Politecnico di Torino, Turin, tional Polytechnique de Grenoble (INPG), Grenoble,
Italy, in 1998. France, in 1989, 1991, and 1999, respectively.
He joined the Discrete and Standard ICs Group He joined SGS-Thomson Microelectronics (cur-
(currently Micro Linear and Digital Group), STMi- rently STMicroelectronics), Grenoble, in 1992 as a
croelectronics, Grenoble, France, in 2000 as an Ap- Product Engineer. Since 1995, he has been respon-
plication Engineer for power management ICs. sible for test development and industrialization for
power management devices.

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