3/13/2015

Introduction to
STATIC TIMING ANALYSIS

Concepts Covered

• Introduction to STA
• Timing Paths
• Skew
• Problems
• Clock & Timing Constraints
• Exceptional Paths
• Pipelining
• Retiming

1
 3/13/2015

FPGA Design Flow

Plan & Create Code/ HDL RTL

Budget Schematic Simulation
Implement
Functional Synthesize
Translate
Simulation to Create Netlist

Map

Place & Route

Attain Timing Timing Create

Closure Simulation BIT File

Why Timing Constraints

• Can you solve this equation and arrive at a hardware?

– F(x) = Σ(0,1,2,4,6,9,11)

• Tools also can ☺

2
 3/13/2015

Why Timing Constraints

• The implementation tools do not attempt to place & route the

circuit that will obtain the best speed
– Instead, the implementation tools try to optimize, P&R for
best area

Without Timing Constraints

• This design had no timing

constraints or pin
assignments
– Note the logical structure
of the placement and
pins

3
 3/13/2015

With Timing Constraints

• This is the same design with

global timing constraints
• Note that the logic is placed
closer to the I/O pins

– Moving the logic closer

to the pins improves on-
chip and off-chip timing

4
 3/13/2015

Need for Timing Analysis

• To check whether the given design meets timing or not.

• To verify that a circuit works at the specified frequency.

Timing Analysis

Timing analysis is a method of analyzing the

timing correctness of any design

Types of timing analysis

1) Dynamic Timing Analysis
2) Static Timing Analysis

10

5
 3/13/2015

Dynamic Timing Analysis

• Dynamic timing analysis / simulation guarantees 100%

coverage
• It is design specific
• One method can not be used to all designs
• Hence for each design a unique test bench needs to be created
• A generalized approach is required so that verification process
is speeded up

11

Static Timing Analysis

• An approach in which no inputs are required

• A general approach which can be applied to any design
• Design is considered as collection of groups / paths
• Each group / path is verified against its specification
• A path which satisfies its timing requirement can not offer
timing violation
• Functionality of the paths are NOT checked
• Importance given to logic levels rather Logic values

12

6
 3/13/2015

STA vs. DTA

Static Timing Analysis Dynamic Timing Analysis
– Fast – Slow
– No input stimuli required – Depends on Input Stimuli
– Covers all timing paths – May or May not cover all paths
– Complex equation in timing
– Relatively simple timing models
models are used
– Efficient for synchronous as
– More efficient for well as asynchronous systems
synchronous systems – Verifies both functionality as
– Verifies only timing well as timing

13

STATIC TIMING ANALYSIS

• STA is a method of analyzing ,debugging and validating the

timing performance of a design
• STA is the process in which the delays of a circuit are
calculated by adding the individual gate and net delays for
each path.

14

7
 3/13/2015

Why only STA?

• STA approach is very fast when compared to dynamic

simulation and verifies all parts of the design for timing.
• Verifying millions of gates per ASIC through dynamic
simulation proves to be impossible due to longer run
times(usually days or sometimes weeks).
Advantages:
• Much faster than timing-driven, gate-level simulation.
• Exhaustive
• Vector generation NOT required.

15

Timing Graphs

16

8
 3/13/2015

STA - Timing Graph Introduction

Node: where timing information is stored on the design
Top
Data D Q Output
Clk QB OutputBar

Bottom

Q. How many nodes are in our design?

A node exists for every
Model pin 4
Cell Pin 8
Hierarchical pin 2
14 17

STA - Node Types

Top
Data D Q Output
Clk QB OutputBar

Data Nodes
Clock Nodes
All nodes along clock path
Created from “force clock constraints”

18

9
 3/13/2015

STA - Events
• At each node it is a group of events modeling
signal transitions
AT RT
D Q

QB

SLEW

Arrival Time (AT) - when the signal arrives

Required Time (RT) - when the signal is needed
Slew (SLEW) - time for signal transition from logic levels

19

STA - Meeting Timing

Q. Am I meeting timing at this node?
AT RT
+SLACK

SLEW

SLACK = RT - AT
• Timing is met when slack is greater than or equal to
zero

20

10
 3/13/2015

STA - Meeting Timing

Q. Am I meeting late mode timing at this node?
SLACK = RT - AT AT +SLACK
RT

RT AT

-SLACK

No, the falling edge slack is negative...

HINT: RT should always be after AT
21

STA - Levels
Q. How many levels of logic are in this design?

4 5
3

3 4 9 10
1 2 1 2
6 7 8

Q. How many timing levels are in this design?

HINT: Determine the nodes first
HINT: Timing Levels = 2 * Logic Levels + 2
22

11
 3/13/2015

STA - Calculating AT
1
1.0 1.2
2.4
25
1 2.6
1.0 2 3
1.2 4 1.9 9
1.7
1 9 10
1.0
4 1.9
1.7 7 3.8 4.0
1
1.0 1.23 4 1.9
2 3.1
8
1.2 3.3
1 6
2 5 2.6
1.0 2.4
2
1.2

STEP 1 : Calculate timing level for each node

STEP 2 : Calculate AT from level 1 to level n
Simplifying assumptions:
Input arrival time of 1
Wire delay 0.2 ; gate delay 0.5
23

STA - Calculating RT
1.4
1 1.2 1.2 1.9
1.0 2.4
2
5
2.1
1 0.5 0.7 2
1.0 1.2 3 2.6
4 1.9 9
1.7 1.4
1 -0.2 1.2 9 10
1.0 1.4
0.0 0.5 4 1.9
7 4.0
1 -0.2 1.2 1.7 0.7 3.8
1.0 2 3 4 1.9 2.6
3.1
8 2.8
0.0 1.2 3.3
6 1.9
1 2
5 2.6 2.1
1.0 2 2.4
0.5 1.4
1.2 1.2
0.7

STEP: Calculate RT from level n to level 1

Simplifying assumptions:
One number for rise and fall
Output required time of 2.8
Wire delay 0.2 ; gate delay 0.5

24

12
 3/13/2015

STA - Calculating Slack

0.2 0.2 -0.5
1.4
1 1.2 1.2 1.9
1.0 2.4
2 -0.5
-0.5 -0.5 5
2.1
1 0.5 0.7 2
1.0 1.2 3 2.6
4 1.9 -0.5 9
-1.2 1.7 1.4 10
1 -0.2 -1.2 1.2 1.4 -0.5
9
1.0 -1.2 0.5 -0.5
0.0 4 1.9
1 -0.2 1.2 1.7 0.7 7 3.8 4.0
1.0 2 3 4 1.9 -1.2 8 2.6 2.8
-1.2 0.0 1.2 3.1
1.9 3.3 -1.2 -1.2
1 -1.2 2 6
5 2.6 -1.2 2.1
1.0 2 2.4 1.4 -1.2
0.5 1.2 1.2 -1.2
-0.5 0.7 -1.2
-0.5

Q: What is the formula for late mode slack?

SLACK = RT - AT
Slack is calculated on an as needed basis

25

WHAT WE DO IN --STA

• The fundamental idea of STA is to find the critical paths in

the design.
• Critical path: The slowest path on the chip between
flops or flops and pins. The critical path limits the
maximum clock speed.

26

13
 3/13/2015

Critical path??
Gate Delay
Not 2
AND 4
OR 4

27

Critical path??
Gate Delay
Not 2
AND 4
OR 4

28

14
 3/13/2015

What Does Register Bound Mean ?

D Q

QB

D Q
D Q
Combo
QB
QB

D Q
clk
QB

• Register bound implies that the combinational logic is

bounded by registers on the inputs and the outputs.
• Combinational logic is represented by a symbolic blob.
29

What to analyze in STA

• There are Four types of timing paths in static timing analysis.

a) From primary inputs to all flops in the design

b) From flop to flop
c) From flop to primary output of the design
d) From primary i/ps to primary o/ps of the design

30

15
 3/13/2015

Primary Input

A M
D Q
Combo Delay
FF1
B
clk

31

Flop to Flop

A C x z
D Q D Q
Combo Delay
FF1 FF2
B
clk y
clk

32

16
 3/13/2015

Primary Output

Z
C
D Q
Combo Delay
FF2

E
clk

33

Primary Input to Primary Output

X Z

Combo Delay

34

17
 3/13/2015

Types of Timing Paths

35

Timing paths

36

18
 3/13/2015

Three Steps in Static Timing Analysis

Circuit is broken down into sets of timing paths

 Delay of each path is calculated
 Path delays are checked to see if timing constraints
have been met

37

What is a Timing Path?

A Timing Path is a point-to-point path in a design which can

propagate data from one flip-flop to another
Each path has a start point and an endpoint
Start point:
Input ports ,Clock pins of flip-flops
Endpoints:
Output ports, Data input pins of flip-flops
38

19
 3/13/2015

Basic Terminologies

39

Concepts Covered
• Minimum clock • Cause and effect of
period timing violations
• Clock latency • Critical path
• Hold constraint • False path
• Clock jitter • Multicycle path
• Setup time • Ideal and computed
• Hold time clocks
• Clock-to-Q time • Specifying clocks
• Clock skew • Generated clocks

40

20
 3/13/2015

Critical Path
Clk

. . . .
. . . .
. . . .

41

• Maximum Clock Frequency/ Minimum Clock Period

The clock frequency for a synchronous sequential circuit is

limited by the timing parameters of its flip-flops and gates.
This limit is called the maximum clock frequency for the
circuit. The minimum clock period is the reciprocal of this
frequency.

42

21
 3/13/2015

STA – What is Static Timing Analysis?

Data D Q Output

Clk QB OutputBar

What are our circuit timing

requirements?

Clk
0 100 200 300 400 500
Data

Setup Requirement
Data Cannot
Hold Requirement Change Within
These Windows
43

Basic Terminologies
• Setup time:
The amount of time the synchronous input
must be stable before the active edge of clock.

• Hold time:
The amount of time the synchronous input
must be stable after the active edge of clock.

44

22
 3/13/2015

Synchronous System - Detailed

Timing
tffpd tcomb
D Q Combinational D Q
tsetup & thold
logic

CLK

tffpd - CLK to Q, FF propagation delay (min, max)

tcomb - combinational logic delay (min, max)
tsetup - input stable before clock (min)
thold - input stable after clock (min)
45
JAL

Synchronous System - Detailed Timing

• Required: tclk,min > tffpd,max + tcomb,max + tsetup,min

Difference = Setup time margin
>= 0 for guaranteed operation

Required: tffpd, min + tcomb,min > thold,min

Difference = Hold time margin
>= 0 for guaranteed operation

46

23
 3/13/2015

Condition for Hold time

D Q D Q

QB QB

clkbar

To satisfy hold time: Tc2q + Tpd (minimum) > Thold

47

Example Timing Violations: Good Timing

48

24
 3/13/2015

Example Timing Violations: Setup Violation

49

Example Timing Violations: Hold Violation

50

25
 3/13/2015

A Timing Example:

51

Problem 2

• Find the maximum applicable clock frequency for the

circuit shown in figure below

52

26
 3/13/2015

Understanding
And
Describing Clocks

53

Defining Clocks

• A clock is defined by its period, waveform and slew time.

Slew rise Slew fall

waveform rise waveform fall

period

54

27
 3/13/2015

Describing Clock Variations

• Clock skew
• Jitter
• Clock latency (delay)

55

Clock Skew

• Clock Skew: The maximum difference in arrival time of the

clock signal to each register in the design

Clock arrival Clock arrival

time at 1.1ns time at 1.3ns

clock

Skew = 1.3ns - 1.1ns = .2ns

56

28
 3/13/2015

Absolute Clock Skew – A Definition

clock input Time from clock input (at pin) to
clock input at a given flip flop

Your chip

Flip
Flop

57

Relative Clock Skew

clock input Time between 2 flip flops receiving
the clock signal

Your chip

Flip Flip
Flop Flop

delay

58

29
 3/13/2015

Failure / Data loss Due To Large Skew

“A” “B”

Ain Flip Aout Combinational Bin Flip

Flop Logic Flop

clk
δ delay

• If new data (Ain) gets to point

“Bin” before clock does, system
will fail by simply skipping over
old data…

• For this illustration - ignore tsetup

59

Clock arrives at point “A”

“A” “B”

Ain Flip Aout Combinational Bin Flip

Flop Logic Flop

clk
δ delay

T = 0ns

60

30
 3/13/2015

Data arrives at combo logic input

“A” “B”

Ain Aout Combinational Bin

Flip Flip
Flop Logic Flop

clk
δ delay

T = tclk-to-Q

61

Data Exits Comb Logic

“A” “B”
new
Ain Aout Combinational Bin Flip
Flip
Flop Logic Bin
Flop

clk
δ delay

T = tclk-to-Q + tlogic

62

31
 3/13/2015

Clock Reaches “B”

“A” “B”
new
Ain Aout Combinational Bin Flip
Flip
Flop Logic Bin
Flop

clk
δ delay

T = tclk-to-Q + tlogic Tskew = tδ

63

Failure!!!

“A” “B”
new New
Ain Aout Combinational Bin Flip Bin
Flip
Flop Logic Bin
Flop

clk
δ delay

What happened to old Bin???

If tclk-to-Q+tlogic < tδ it fails…

64

32
 3/13/2015

More on Skew

65

Positive & Negative Skew

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic
CLK tCLK1 tCLK2 tCLK3

delay delay
(a) Positive skew

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic
tCLK1 tCLK2 tCLK3

delay delay CLK

(b) Negative skew

66

33
 3/13/2015

Clock Skew
A and C have clock skew
A and D have clock skew Clock Generator
B and C have clock skew (PLL)
B and Dh ave clock skew
A and B have zero clock
skew

A Metal Line B

A and C have clock skew

C Metal Line D

C and D have zero clock

skew

67

Fixes for Clock Skew

A Metal Line B

Clock Generator All delays are equal: No

(PLL) Clock Skew

C Metal Line D

68

34
 3/13/2015

Clock Jitter
• Clock Jitter:

Frequency variation in the clock source / Difference between actual

clock period and ideal clock period.

clock
jitter

69

Clock Jitter

Clock jitter is caused by:

• temperature and voltage variations over time
• temperature and voltage variations across different locations on a chip
• manufacturing variations between different parts
• etc.
70

35
 3/13/2015

Source and Network Latency

71

Source ad Network Latency

•Clock source latency is the time it takes for a clock signal to

propagate from its actual clock origin point to the clock definition
point in the design.

•Clock network latency is the time it takes for a clock signal to

propagate from the clock definition point to a register clock pin.

72

36
 3/13/2015

Summary: Clocks

• A clock is defined by its period, waveform and

slew time
• Clock variations that can be described for timing
calculation include skew, jitter and latency.

73

False Paths

74

37
 3/13/2015

What are False paths?

• Paths that physically exist in a design but are not

logic/functional paths

• These paths never get sensitized under any input

conditions

75

Logically Impossible Example

•A path may exist in the circuit but no combination of
input vectors may ever exercise it

Mux 1 Mux 2

A C C1 C2 OUT
B1 B2
B

Total 4 timing paths

PATH 1 – A-C-C1-C2-OUT
PATH 2 – A-C-OUT
PATH 3 – B-B1-B2-C-C1-C2-OUT
PATH 4 – B-B1-B2-C-OUT
Only path1 and 4 above are valid logic paths as select line for the 2 muxes are the
same 76

38
 3/13/2015

Multicycle Path: Example

U1 U2
D Q D Q
QB QB

CK

200 MHz 50 MHz

TC CE
CLK PRE2 COUT14

Q0 Q1 Q2 Q3 Q4 Q14 Q15

77

Multicycle Path

•Multicycle paths are paths which intentionally

require more than one clock cycle to propagate.
•This information cannot possibly be inferred by the
timing analyzer, so it must be specified by the
designer so the analyzer can mark the path and
correctly compute the timing.
• A start point, end point and/or "through" point is
specified, along with the number of allowed clock
cycles.

78

39
 3/13/2015

Pipelining Concept

79

Pipelining
Concept

80

40
 3/13/2015

Latency in Pipelines

81

Pipelining Example

Original circuit
– Two logic levels between SOURCE_FFS and
DEST_FF
– fMAX = ~207 MHz

82

41
 3/13/2015

Pipelining Example…contd
Pipelined circuit
– One logic level between each set of flip-flops
– fMAX = ~347 MHz

83

Review Question
Given the original circuit, what is wrong with
the pipelined circuit?
How can the problem be corrected?

84

42
 3/13/2015

Retiming Concept

Register balancing in order to balance the timing

85

GLUE LOGIC

86

43
 3/13/2015

AVOID GLUE LOGIC

X
RegA X
clock RegA
GLUE clock

X
RegB
clock

THE AND GATE AT THE TOP LEVEL SERVERS ONLY TO

GLUE THE INSTATIATED CELLS
OPTIMIZATION IS LIMITED BECAUSE THE GLUE

LOGIC CANNOT BE ABSORBED

87

REMOVE GLUE LOGIC BETWEEN BLOCKS

X+GLUE
X
RegA
clock RegA
clock

X
RegB
clock

 The glue logic can now be optimized with other logic

 Top level design is only a structural netlist, doesn’t need to be

compiled 88

44
 3/13/2015

Limitations of STA
• Works best with synchronous (not asynchronous) logic
• Must define timing requirements / exceptions
• Difficulty in handling:

• Multiple clocks
• False paths
• Latches
• Multicycle paths

89

THANK YOU

90

45