UNIT-1

DATA REPRESENTATION-Digital LOGIC CIRCUITS

PART-A PART-B
DATA REPRESENTATION Digital LOGIC Circuits

 BINARY NUMBERS  Basic logic functions

 FIXED POINT REPRESENTATION  Logic gates
 FLOATING POINT REPRESENTATION
 Universal logic gates
 NUMBER BASE CONVERSIONS
 Minimization of logic expressions
 OCTAL AND HEXA DECIMAL NUMBERS
 COMPONENTS
 K-map simplification
 Combinational circuits
 SIGNED BINARY NUMBERS  Decoders
 BINARY CODES  multiplexers

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 BINARY NUMBERS
A binary number system is one of the four types of number system. In computer applications, where binary
numbers are represented by only two symbols or digits, i.e. 0 (zero) and 1(one). The binary numbers here
are expressed in the base-2 numeral system. For example, (101)2 is a binary number

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 Fixed point representation
There are various types of number representation techniques for digital number representation, for
example: Binary number system, octal number system, decimal number system, and hexadecimal
number system etc. But Binary number system is most relevant and popular for representing numbers
in digital computer system.

There are two major approaches to store real numbers (i.e., numbers with fractional component) in
modern computing. These are
(i) Fixed Point Notation and
In fixed point notation, there are a fixed number of digits after the decimal point,
(ii) Floating Point Notation.
whereas floating point number allows for a varying number of digits after the decimal point.

Fixed-Point Representation −
using a fixed notation where the decimal point is fixed and we know that any numbers to the right of the decimal
point are the decimal portion and to the left is the integer part.
E.g. 10.75 10 is the Integer Portion and 0.75 is the decimal portion

There are three parts of a fixed-point number representation: the sign field, integer field, and fractional field.

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  FLOATING point representation
The structure of a floating point(real) number is as follows:
Only the mantissa and the exponent are stored. The base is implied (known already) As it is not stored
this will save memory capacity.

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The advantage of using a fixed-point representation is performance and
disadvantage is relatively limited range of values that they can represent.
So, it is usually inadequate for numerical analysis as it does not allow enough numbers and accuracy.

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 Floating point representation

The floating number representation of a number has two part:

 the first part represents a signed fixed point number called mantissa.
 The second part of designates the position of the decimal (or binary) point and is called the
exponent. T
 he fixed point mantissa may be fraction or an integer. Floating -point is always interpreted to
represent a number in the following form: M x re.
 Only the mantissa M and the exponent e are physically represented in the register (including their
sign).
 A floating-point binary number is represented in a similar manner except that is uses base 2 for
the exponent.
 A floating-point number is said to be normalized if the most significant digit of the mantissa is 1.

So, actual number is (-1)s(1+m)x2(e-Bias), where s is the sign bit, m is the

mantissa, e is the exponent value, and Bias is the bias number.
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 Floating point representation

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NUMBER BASE CONVERSIONS

Example 1. Convert (1101)2 into a decimal number.

Example 2: Convert 228 to decimal number

Example 3: Convert 12116 to decimal number
Example: Convert (89)16 into a binary number. Practice Problems on Number System
8 = 1000 and 9 = 1001 Conversion
Therefore, (89)16 = (10001001)2 1.Convert 14610 into a binary number system
2.Convert 1A716 into the decimal number
Example: Convert (214)8 into a binary number system
2 → 010 3.Convert (110010)2 into octal number
1 → 001 system
4 → 100 4.Convert DA216 into the binary number
Therefore,(214)8 = (010001100)2 system
5.Convert 46528 into the binary number
system

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COMPLIMENTS
The complement of an integer is the integer you get when you flip all the 0 's to 1 's and all the 1 's
to 0 's in its binary representation. For example, The integer 9 is "1001" in binary and its
complement is "0110" which is the integer 6

Binary system complements

As the binary system has base r = 2. So the two types of complements for the binary
system are 2's complement and 1's complement.

1's complement
The 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's.
This is called as taking complement or 1's complement. Example of 1's Complement is
as follows.

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2's complement
The 2's complement of binary number is obtained by
adding 1 to the Least Significant Bit (LSB) of 1's
complement of the number.
2's complement = 1's complement + 1

9's and 10's Complement

If the number is binary, then we use 1's complement
and 2's complement. But in case, when the number is
a decimal number, we will use the 9's and 10's
complement. The 10's complement is obtained from
the 9's complement of the number,

9's Complement
The 9's complement of a number is calculated by subtracting each digit of the number by 9.
For example: find the 9's complement of the number 1423.
For this, we subtract each digit of the number 1423 by 9. So, the 9's complement of the number 1423
is 9999-1423= 8576
10's Complement
The 10's complement is also used to find the subtraction of the decimal numbers.
The 10's complement of a number is calculated by subtracting each digit by 9 and then adding 1 to
the result. Simply, by adding 1 to its 9's complement we can get its 10's complement value.
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 USING 9’S COMPLIMENTS Case 1: When the subtrahend is smaller than the minuend

Case 2: When the subtrahend is greater than the minuend.

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USING 10’S COMPLIMENTS Case 1: When the subtrahend is smaller than the minuend

Case 2: When the subtrahend is greater than the minuend.

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Signed Binary Numbers
Signed Binary Numbers use the MSB as a sign bit to display a range of either positive numbers or
negative numbers
Positive Signed Binary Numbers Negative Signed Binary Numbers

Signed Binary Numbers Example No1

Convert the following decimal values into signed binary numbers using the sign-magnitude format

-1510 as a 6-bit number ⇒ 1011112

+2310 as a 6-bit number ⇒ 0101112

-5610 as a 8-bit number ⇒ 101110002

+8510 as a 8-bit number ⇒ 010101012

-12710 as a 8-bit number ⇒ 111111112

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Signed Numbers:
Signed numbers contain sign flag, this representation distinguish positive and negative
numbers. This technique contains both sign bit and magnitude of a number. For example, in
representation of negative decimal numbers, we need to put negative symbol in front of
given decimal number.
There are three types of representations for signed binary numbers. These are:
a. ) Sign-Magnitude form,
b. ) 1’s complement form, and
c. ) 2’s complement form
(a) Sign-Magnitude form:
For n bit binary number, 1 bit is reserved for sign symbol. If the value of sign bit is 0, then
the given number will be positive, else if the value of sign bit is 1, then the given number
will be negative. Remaining (n-1) bits represent magnitude of the number.

Generally sign bit is a most significant bit (MSB) of representation. The range of Sign-
Magnitude form is from (2(n-1)-1) to (2(n-1)-1).
For example, range of 6 bit Sign-Magnitude form binary number is from (25-1) to (25-1)
which is equal from minimum value -31 (i.e., 1 11111) to maximum value +31 (i.e., 0 11111).
And zero (0) has two representation, -0 (i.e., 1 00000) and +0 (i.e., 0 00000).

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(b) 1’s complement form:
Since, 1’s complement of a number is obtained by inverting each bit of given number. So, we
represent positive numbers in binary form and negative numbers in 1’s complement form.
There is extra bit for sign representation.
1’s complement form is also ambiguous form.
The range of 1’s complement form is from (2(n-1)-1) to (2(n-1)-1) .
For example, range of 6 bit 1’s complement form binary number is from (25-1) to (25-1)
which is equal from minimum value -31 (i.e., 1 00000) to maximum value +31 (i.e., 0
11111). And zero (0) has two representation, -0 (i.e., 1 11111) and +0 (i.e., 0 00000).

(c) 2’s complement form:

Since, 2’s complement of a number is obtained by inverting each bit of given number plus 1
to least significant bit (LSB). So, we represent positive numbers in binary form and negative
numbers in 2’s complement form. There is extra bit for sign representation.
The range of 2’s complement form is from (2(n-1)) to (2(n-1)-1).

For example, range of 6 bit 2’s complement form binary number is from (25) to (25-1) which
is equal from minimum value -32 (i.e., 1 00000) to maximum value +31 (i.e., 0 11111). And
zero (0) has two representation, -0 (i.e., 1 11111) and +0 (i.e., 0 00000).

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 BINARY CODES
the digital data is represented, stored and transmitted as group of binary bits. This group is
also called as binary code. The binary code is represented by the number as well as
alphanumeric letter.
Advantages of Binary Code:Following is the list of advantages that binary code offers.
•Binary codes are suitable for the computer applications.
•Binary codes are suitable for the digital communications.
•Binary codes make the analysis and designing of digital circuits if we use the binary codes.
•Since only 0 & 1 are being used, implementation becomes easy.
Classification of binary codes
The codes are broadly categorized into following four categories.
•Weighted Codes-Non-Weighted Codes
•Binary Coded Decimal Code
•Alphanumeric Codes
•Error Detecting Codes
•Error Correcting Code

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 BINARY CODES

Weighted Codes: 8421- CODE

 Weighted binary codes are those binary codes which obey the positional weight
principle. Each position of the number represents a specific weight.
 Several systems of the codes are used to express the decimal digits 0 through 9.
 In these codes each decimal digit is represented by a group of four bits.

Non-Weighted Codes
In this type of binary codes, the
positional weights are not assigned. The
examples of non-weighted codes are
Excess-3 code and Gray code.

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 BINARY CODES
Gray Code
 It is the non-weighted code and it is not arithmetic codes.
 That means there are no specific weights assigned to the bit position.
 It has a very special feature that, only one bit will change each time the decimal number
is incremented
 As only one bit changes at a time, the gray code is called as a unit distance code.
 The gray code is a cyclic code. Gray code cannot be used for arithmetic operation

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BINARY CODES

Binary Coded Decimal (BCD) code

 In this code each decimal digit is represented by a 4-bit binary number.
 In the BCD, with four bits we can represent sixteen numbers (0000 to 1111).
 But in BCD code only first ten of these are used (0000 to 1001). The remaining six
code combinations i.e. 1010 to 1111 are invalid in BCD.

Advantages of BCD Codes

•It is very similar to decimal system.
•We need to remember binary equivalent of decimal numbers 0 to 9 only.
Disadvantages of BCD Codes
•The addition and subtraction of BCD have different rules.
•The BCD arithmetic is little more complicated.
•BCD needs more number of bits than binary to represent the decimal number. So
BCD is less efficient than binary.

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 BINARY CODES
Alphanumeric codes
 A binary digit or bit can represent only two symbols as it has only two states '0' or '1'.
But this is not enough for communication between two computers because there we
need many more symbols for communication.
 These symbols are required to represent 26 alphabets with capital and small letters,
numbers from 0 to 9, punctuation marks and other symbols.
 An alphanumeric code should at least represent 10 digits and 26 letters of alphabet i.e.
total 36 items.
•American Standard Code for Information Interchange (ASCII).
•Extended Binary Coded Decimal Interchange Code (EBCDIC).
•Five bit Baudot Code.

 ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code.

 ASCII code is more commonly used worldwide while EBCDIC is used primarily in large
IBM computers.
Error Codes
There are binary code techniques available to detect and correct data during data
transmission

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 BINARY CODES
Error Codes
There are binary code techniques available to detect and correct data during data
transmission
Error-Correcting codes
In error-correcting codes, parity check has a simple way to detect errors along with a
sophisticated mechanism to determine the corrupt bit location. Once the corrupt bit is
located, its value is reverted (from 0 to 1 or 1 to 0) to get the original message.
Parity Checking of Error Detection
It is the simplest technique for detecting and correcting
errors. The MSB of an 8-bits word is used as the parity bit
and the remaining 7 bits are used as data or message bits.
The parity of 8-bits transmitted word can be either even
parity or odd parity.

Even parity -- Even parity means the number of 1's in the

given word including the parity bit should be even
(2,4,6,....).
Odd parity -- Odd parity means the number of 1's in the given
word including the parity bit should be odd (1,3,5,....).
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 PART-B-Digital LOGIC Circuits

There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR and XNOR.

Logic gates are the fundamental components of all digital circuits and systems. In digital electronics,
there are seven main types of logic gates used to perform various logical operations. A logic gate is
basically an electronic circuit designed by using components like diodes, transistors, resistors,
capacitors, etc., and capable of performing logical operations

AND Gate
The AND gate is a digital logic gate with ‘n’ i/ps one o/p, which
performs logical conjunction based on the combinations of its inputs.
The output of this gate is true only when all the inputs are true. When
one or more inputs of the AND gate’s i/ps are false, then only the
output of the AND gate is false. The symbol and truth table of an AND
gate with two inputs is shown below.

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 PART-B-Digital LOGIC Circuits

OR Gate
The OR gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs logical conjunction based on the
combinations of its inputs.
The output of the OR gate is true only when one or more inputs are true. If all the i/ps of the gate are false,
then only the output of the OR gate is false. The symbol and truth table of an OR gate with two inputs is
shown below.

NOT Gate
The NOT gate is a digital logic gate with one input and one output that operates an inverter operation of the
input. The output of the NOT gate is the reverse of the input. When the input of the NOT gate is true then the
output will be false and vice versa. The symbol and truth table of a NOT gate with one input is shown below.
By using this gate, we can implement NOR and NAND gates

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 PART-B-Digital LOGIC Circuits
NAND Gate
The NAND gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs the operation of the AND gate
followed by the operation of the NOT gate. NAND gate is designed by combining the AND and NOT gates. If the
input of the NAND gate high, then the output of the gate will be low.The symbol and truth table of the NAND
gate with two inputs is shown below

NOR Gate
NOR gate is designed by combining the OR and NOT gate. When any one of the i/ps of the NOR gate is true,
then the output of the NOR gate will be false. The symbol and truth table of the NOR gate with the truth table
is shown below.

Exclusive-OR Gate
The Exclusive-OR gate is a digital logic gate with two inputs and one output. The short form of this gate is Ex-
OR.. If any one of the inputs of this gate is high, then the output of the EX-OR gate will be high.
 PART-B-Digital LOGIC Circuits
Exclusive-OR Gate
The Exclusive-OR gate is a digital logic gate with two inputs and one output. The short form of this gate is Ex-
OR.. If any one of the inputs of this gate is high, then the output of the EX-OR gate will be high.

Exclusive-NOR Gate
The Exclusive-NOR gate is a digital logic gate with two inputs and one output. The short form of this gate is Ex-
NOR. When both the inputs of this gate are high, then the output of the EX-NOR gate will be high. But, if any one of
the inputs is high (but not both), then the output will be low.

De Morgan’s Theorem
The first theorem of DeMorgan states that the logic gate like NAND is equal to an OR gate with a
bubble. The logic function of the NAND gate is
A’B = A’+B’
The second theorem of DeMorgan states that the NOR logic gate is equal to an AND gate with a bubble.
The logic function of NOR gate is
(A+B)’= A’. B’
 PART-B-Digital LOGIC Circuits
De Morgan’s Theorem
The first theorem of DeMorgan states that the logic gate like NAND is equal to an OR gate with a bubble. The
logic function of the NAND gate is
A’B = A’+B’
The second theorem of DeMorgan states that the NOR logic gate is equal to an AND gate with a bubble. The
logic function of NOR gate is
(A+B)’= A’. B’

The seven basic logic gates are:

•AND produces a 0 output unless both the X and Y inputs are both 1, when the output is 1.
•NAND is the negation of AND, it produces a 1 output unless both the X and Y inputs are both 1, when the
output is 0.
•OR produces a 0 output only when both the X and Y inputs are 0, otherwise the output is 1.
•NOR is the negation of OR and produces a 1 output when both inputs are 0, otherwise the output is 0.
•XOR is an exclusive OR and outputs 1 if there is only a single 1 input between X and Y, inputs of two 0s or two
1s produce an output of 0.
•XNOR is the inverse of XOR and inputs of two 0s and two 1s will produce an output of 1, it produces an output
of 0 if there is a single 1 input between X and Y.
•NOT is also called an inverter; if the input is 1, the output is 0, and if the input is a 0 the output is 1
PART-B-Digital LOGIC Circuits
 PART-B-Digital LOGIC Circuits

K-map simplification:
In many digital circuits and practical problems, we need to find expressions with minimum
variables. We can minimize Boolean expressions of 3, 4 variables very easily using K-map without
using any Boolean algebra theorems.
K-map can take two forms:
1.Sum of product (SOP)
2.Product of Sum (POS)
According to the need of problem. K-map is a table-like representation, but it gives more
information than the TABLE. We fill a grid of the K-map with 0’s and 1’s then solve it by making
groups.
Steps to Solve Expression using K-map
1.Select the K-map according to the number of variables.
2.Identify minterms or maxterms as given in the problem.
3.For SOP put 1’s in blocks of K-map respective to the minterms (0’s elsewhere).
4.For POS put 0’s in blocks of K-map respective to the max terms (1’s elsewhere).
5.Make rectangular groups containing total terms in power of two like 2,4,8 ..(except 1) and try to
cover as many elements as you can in one group.
6.From the groups made in step 5 find the product terms and sum them up for SOP form.
 K-map simplification: PART-B-Digital LOGIC Circuits

The Karnaugh map uses the following rules for the simplification of expressions
by grouping together adjacent cells containing ones.

•Groups may not include any cell containing a zero Groups may overlap

Groups may be horizontal or vertical, but not diagonal

 PART-B-Digital LOGIC Circuits
K-map simplification:
Groups may be horizontal or vertical, but not diagonal

Each group should be as large as possible

Each cell containing a one must be in at least one group.

 PART-B-Digital LOGIC Circuits

Groups must contain 1, 2, 4, 8, or in general 2n cells.That is if n = 1, a group will contain two 1's since 21 = 2.
If n = 2, a group will contain four 1's since 22 = 4.

Each group should be as large as possible.

 PART-B-Digital LOGIC Circuits
Groups may wrap around the table. The leftmost cell in a row may be grouped with the rightmost cell and the top
cell in a column may be grouped with the bottom cell

There should be as few groups as possible, as long as this does not contradict any of the previous rules
 PART-B-Digital LOGIC Circuits

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example
encoder, decoder, multiplexer and demultiplexer.
Some of the characteristics of combinational circuits are following −
•The output of combinational circuit at any instant of time, depends only on the levels present at input
terminals.
•The combinational circuit do not use any memory. The previous state of input does not have any effect on
the present state of the circuit.
•A combinational circuit can have an n number of inputs and m number of outputs.

Block diagram
 PART-B-Digital LOGIC Circuits
Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is
designed to add two single bit binary number A and B. It is the basic building block for addition of
two single bit numbers. This circuit has two outputs carry and sum.

Half Subtractors:
Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It produces the
difference between the two binary bits at the input and also produces an output (Borrow) to indicate if a 1 has
been borrowed. In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit.
Full Adder PART-B-Digital LOGIC Circuits
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit numbers A
and B, and carry c. The full adder is a three input and two output combinational circuit

Full Subtractors
 The disadvantage of a half subtractor is
overcome by full subtractor.
 The full subtractor is a combinational circuit
with three inputs A,B,C and two output D and C'.
 A is the 'minuend', B is 'subtrahend', C is the
'borrow' produced by the previous stage, D is
the difference output and C' is the borrow
output.
 PART-B-Digital LOGIC Circuits

Multiplexers
 Multiplexer is a special type of combinational
circuit. There are n-data inputs, one output and
m select inputs with 2𝑚 = 𝑛
 It is a digital circuit which selects one of the n
data inputs and routes it to the output.
 The selection of one of the n inputs is done by the
selected inputs.
 Depending on the digital code applied at the
selected inputs, one out of n data sources is
selected and transmitted to the single output Y. E
is called the strobe or enable input which is
useful for the cascading.
 It is generally an active low terminal that means
it will perform the required operation when it is Multiplexers come in multiple variations
low. •2 : 1 multiplexer
•4 : 1 multiplexer
•16 : 1 multiplexer
•32 : 1 multiplexer
 PART-B-Digital LOGIC Circuits

Demultiplexers
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and distributes it
over several outputs. It has only one input, n outputs, m select input. At a time only one output line is selected
by the select lines and the input is transmitted to the selected output line.

Demultiplexers comes in multiple variations.

•1 : 2 demultiplexer
•1 : 4 demultiplexer
•1 : 16 demultiplexer
•1 : 32 demultiplexer
 PART-B-Digital LOGIC Circuits
2 to 4 Line DecoderThe block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs
where D through D are the four outputs. Truth table explains the operations of a decoder. It shows that each
output is 1 for only a specific combination of inputs.

2 to 4 Line Decoder
Encoder
 Encoder is a combinational circuit which is
designed to perform the inverse operation of
the decoder.
 An encoder has n number of input lines and m
number of output lines.
 An encoder produces an m bit binary code
corresponding to the digital input number.
 The encoder accepts an n input digital word and
converts it into an m bit another digital word.

Examples of Encoders are following.

• Priority encoders
• Decimal to BCD encoder
• Octal to binary encoder
• Hexadecimal to binary encoder