Challenges for Waveform Sampling and Related Technologies

Haruo Kobayashi a, Kentaroh Katoh, Shuhei Yamamoto, Yujie Zhao, Shogo Katayama
2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) | 978-1-6654-6906-7/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICSICT55466.2022.9963176

Jianglin Wei2, Yonglun Yan, Dan Yao, Xueyan Bai, Anna Kuwana

Division of Electronics and Informatics, Gunma University, 1-5-1 Tenjin-cho, Kiryu, 376-8515 Japan
2
Faculty of Intelligence Manufacturing, Yibin University, Yibin, Sichuan, 64400 China
E-mail: [email protected]

Abstract - Waveform sampling and their related

technologies are important for electronic appliances, IoT,
automotive, social infrastructure and 5G, 6G devices as
well as their testing systems. This paper reviews them
mainly based on the authors’ laboratory research results,
and discusses their challenges.

Keywords: Waveform Sampling, Track/Hold Circuit, Fig. 1 Analog signal waveform and its sampled points.
ADC, DAC, Clock Jitter,
Proactive usage of clock jitter:
1. Introduction Clock jitter can be used proactively in switching
Electronic systems are getting to be digitalized, but the regulators for EMI reduction by noise spread spectrum as
natural signals are analog, so that ADC/DAC are shown in [8]. Especially the band selection technique was
becoming more important. The ADC consists of the proposed which uses delta-sigma digital-to-time
waveform sampling and quantization operations. This converter (DTC) technique and the noise spectrum band
paper focuses on the waveform sampling and reviews can be selected [9].
their related technologies with some suggestions of future
challenges. Sampling finite aperture time:
Finite aperture time gives low-pass filter effect to the
2. Wide Range of Waveform Sampling Technologies sampling circuit and its explicit transfer function is shown
Fig.1 explains the waveform sampling. in [10]. It is harmful to high frequency waveform
acquisition. However, it can be used proactively for low
Fundamental design tradeoff of the sampling circuit: frequency signal acquisition such as in sensor interface
Noise, bandwidth and SNR tradeoff of the sampling circuit; the long aperture time reduces the pedestal output
circuit is clarified in [1]. There the track/hold circuit and voltage error of the sampling circuit due to the MOS
the impulse sampling circuit are discussed and the strobe switch charge injection and clock feedthrough and also
sampling circuit is proposed as a good design compromise. filters out the high frequency noises [11].

Sampling clock jitter: Time-interleaved ADC:

Sampling clock jitter deteriorates the ADC SNR and it is The time-interleaved ADC can realize a high frequency
analyzed in [2, 3]. Input signal level dependent sampling sampling rate with relatively slow channel ADCs. There,
timing (or effective sampling jitter) in the MOS sampling clock timing skew among the channel ADCs degrades the
circuit is analyzed in [4]. overall SNDR of the time-interleaved ADC, especially for
high frequency signal acquisition. Its effect is analyzed in
Jitter and phase noise measurement circuits: theory and simulation [12]. Also, the timing skew
On-chip jitter measurement is developed in [5], which compensation method using cross-correlation method and
used a self-reference clock technique, and did not a jitter- a factional-delay digital filter was proposed in [13, 14, 15].
free reference clock. Also the phase noise power spectrum
measurement circuit using the delta-sigma TDC with the Oversampling:
self-reference clock technique is proposed in [6]; this can Oversampling technique is used in delta-sigma AD/DA
avoid the usage of a spectrum analyzer with several time modulators with fine CMOS, thanks to its high speed
averaging of the measurement results. On the other hand, sampling capability. This technique converts the high
jitter reduction circuit is developed in [7]. speed to the voltage accuracy and associated analog filter
requirements can be relaxed [16, 17].

978-1-6654-6906-7/22/$31.00 © 2022 IEEE

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Undersampling: verified in [26] that it is efficient when the ratio of two
High throughput equivalent-time sampling (or frequencies is the golden ratio; otherwise it may not be
undersampling) systems have been investigated to acquire effective.
wideband repetitive signals, such as using Farey sequence
or Brocot space theory [18, 19]. Sampling method for ADC test:
It is shown in [30] that the golden-ratio sampling is
Subsampling bandpass delta-sigma ADC: effective for the histogram test of the ADC linearity. Also
The subsampling technique can be used for very high- the ratio of the sampling frequency and input frequency is
frequency signal band ADC conversion in a continuous- investigated for FFT method in coherent sampling was
time bandpass delta-sigma ADC [20]. However, notice investigated [31].
that the subsampling has to pay other performance penalty.
Pseudo random number generation:
Non-uniform sampling: Pseudo random number for Monte-Carlo simulation can
The time-domain ADC architecture was proposed in [21]; be generated based on the golden ratio sampling, and the
it is composed of a comparator and a TDC as well as a multi-dimensional pseudo random number generation
cosine wave generator with a delta-sigma DA modulator was also investigated [32].
and an LC bandpass filter; they are mostly digital. The
input analog signal and the cosine wave are compared and DAC for signal generation:
the TDC measures the time when they are equal. This The DAC is used for signal generation with sampling
performs the non-uniform sampling (or input signal clock, and its operation is the inverse of the ADC.
dependent sampling timing) and it has to be converted to Sampling clock jitter effect to the DAC was analyzed in
the uniform sampling with digital signal processing. [33]. The simple digital dither method to suppress the
limit cycle was investigated in [34]. Spread spectrum
Residue sampling: method of I, Q DACs mismatches using dynamic element
The residue sampling provides high-frequency signal matching is discussed in [35].
estimation using multiple low-frequency sampling
circuits following an analog Hilbert filter and ADCs; 2D image sampling:
the sampling frequencies are relatively prime. It is Square sampling is often used for 2D image, but
based on aliasing phenomena in the frequency domain hexagonal sampling can be also effective [36].
for waveform sampling and the residue number theory.
Since the high frequency signal is sampled with low Other sampling topics:
frequency clocks, aliasing occurs. However, each Quadrature sampling and frequency conversion by
sampling as well as multi-rate signal processing [37] are
aliased frequency is different because each sampling
also interesting.
clock frequency is different in the sampling circuits.
Based on the Chinese remainder theorem, this
3. Challenges for Waveform Sampling Technologies
difference allows the input frequency to be estimated (1) System level approach would be effective to realize a
[22]. its applications to RF/AMS device testing, such high performance sampling system. For example, a
as two tone testing for high frequency narrow band continuous-time delta-sigma AD modulator can alleviate
devices and wireless communication device testing the clock jitter requirement significantly because the
have been investigated [23]. error caused by the sampling clock jitter for the
comparator is noise-shaped and that for the internal DAC
Metallic ratio sampling: is reduced by using the multi-bit DAC or the DAC output
It is shown in [24, 25, 26] that the metallic ratio of the waveform shape. The wide-band can be obtained by the
sampling frequency and the input frequency can be used bandwidth-interleaving. Also the high-performance
for efficient waveform acquisition in LSI testing where signal generation system using the multiple-DAC
both frequencies are controllable. This method was bandwidth interleave system should be considered.
inspired by from the waveform missing phenomena in a (2) Integer theory is well matched to the sampling
sampling oscilloscope. technology, such as Fibonacci sequence, Farey sequence
and residue number system. Other integer theories may
TDC linearity calibration: be applicable to the sampling system design and analysis
The TDC is a key component for the time-domain signal [38].
processing [27]. TDC linearity self-calibration with the (3) Proactive use of the sampling non-idealities such as
histogram method can be done with two asynchronous the clock jitter, the finite aperture time should be
clocks of different frequencies [28, 29]. It was found and considered.

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(4) Theoretical clarification, design and analysis of the Communication IC Testing and ATE Systems", IEEE
sampling circuits and systems and new sampling International Test Conference (Nov. 2016).
techniques are challenges in this area. [18] M. Kimura, et. al., “A Quasi-Coherent Sampling Method
for Wideband Data Acquisition'', IEICE Trans. Fundamentals,
(April 2002).
4. Conclusion [19] M. Kimura, et. al., “A New Coherent Sampling System with
Waveform sampling and related technologies are a Triggered Time Interpolation'', IEICE Trans. Fundamentals,
reviewed in wide range; their techniques, non-idealities (March 2001).
and design trade-off. Also their challenges are discussed. [20] M. Uemori, et. al., “High-Speed Continuous-Time
Hope that this review article will be useful for researchers Subsampling Bandpass ΔΣAD Modulator Architecture'', IEICE
in related areas. Trans. Fundamentals (April 2006).
Kobayashi laboratory members of Gunma University [21] T. Komuro, et. al., “ADC Architecture Using Time-to-
and our research associates who have contributed these Digital Converter”, IEICE Trans. JC (Feb. 2007).
research results are acknowledged. [22] Y. Abe, et. al., "Frequency Estimation Sampling Circuit
Using Analog Hilbert Filter and Residue Number System",
IEEE ASICON (Oct. 2019).
REFERENCES [23] S. Katayama, et. al., "Application of Residue Sampling to
RF/AMS Device Testing", IEEE ATS (Nov. 2021).
[1] M. Uemori, et. al., Wideband and large Dynamic Range
[24] Y. Sasaki, et. al., "Highly Efficient Waveform Acquisition
Sampling Method, IEICE Trans. JC (Sept. 2007).
Condition in Equivalent-Time Sampling System", IEEE ATS
[2] H. Kobayashi, et. al., “Aperture Jitter Effects on Wideband
(Oct. 2018).
Sampling Systems'', IEEE IMTC (May 1999)
[25] S. Yamamoto, et. al., "Metallic Ratio Equivalent-Time
[3] H. Kobayashi, et. al., “Sampling Jitter and Finite Aperture
Sampling: A Highly Efficient Waveform Acquisition Method",
Time Effects in Wideband Data Acquisition Systems'', IEICE
IEEE IOLTS (June 2021).
Trans. Fundamentals (Feb. 2002).
[26] S. Yamamoto, et. al., "Metallic Ratio Equivalent-Time
[4] N. Hayasaka, H. Kobayashi, “Input-Dependent Sampling- Sampling and Application to TDC Linearity Calibration",
Time Error Effects in MOS Samplers'', IEICE Trans. IEEE Trans. Device and Materials Reliability（March 2022).
Electronics (June 2004).
[27] H. Kobayashi, et. al., "Fine Time Resolution TDC
[5] K. Niitsu, et. al., "CMOS Circuits to Measure Timing Jitter
Architectures-Integral and Delta-Sigma Types", IEEE
Using a Self-Referenced Clock and a Cascaded Time
ASICON (Oct. 2019).
Difference Amplifier with Duty-Cycle Compensation", IEEE
[28] S. Ito, et. al., “Stochastic TDC Architecture with Self-
Journal of Solid-State Circuits (Nov. 2012)
Calibration”, IEEE APCCAS (Dec. 2010).
[6] Y. Osawa, et. al., “Phase Noise Measurement Techniques
[29] T. Chujo, et. al., “Experimental Verification of Timing
Using Delta-Sigma TDC”, IEEE IMS3TW (Sept. 2014).
Measurement Circuit With Self-Calibration”, IEEE IMS3TW
[7] K. Niitsu, et. al., "A Clock Jitter Reduction Circuit Using
(Sept. 2014).
Gated Phase Blending Between Self-Delayed Clock Edges",
[30] Y. Zhao, et. al., "Revisit to Histogram Method for ADC
Symposium on VLSI Circuits (June 2012).
Linearity Test: Examination of Input Signal and Ratio of Input
[8] T. Daimon, et. al., “Spread-Spectrum Clocking in Switching and Sampling Frequencies", Journal of Electronic Testing:
Regulators for EMI Reduction'', IEICE Trans. Fundamentals Theory and Applications, Springer (March 2022).
(Feb. 2003). [31] K. Sato, et. al., "Revisit to Accurate ADC Testing with
[9] Y. Sun, et. al., "Pulse Coding Controlled Switching Incoherent Sampling Using Proper Sinusoidal Signal and
Converter that Generates Notch Frequency to Suit Noise Sampling Frequencies", IEEE International Test Conference
Spectrum", IEICE Trans. Communications (Nov. 2020). (Oct. 2021).
[10] M. Arai, et. al., “Finite Aperture Time Effects in Sampling [32] R. Ohta, et. al., "Pseudo Random Number Generation
Circuit,” IEEE ASICON (Nov. 2015). Algorithms with Fibonacci Sequence", International Workshop
[11] Y. Yan, et. al., "Proactive Use of Finite Aperture Time in on Post-Binary ULSI Systems (May 2022).
Sampling Circuit for Sensor Interface", ICTSS (Dec. 2021). [33] N. Kurosawa, et. al., “Sampling Clock Jitter Effects in
[12] N. Kurosawa, et. al., “Explicit Analysis of Channel Digital-to-Analog Converters'', Measurement (March 2002).
Mismatch Effects in Time-Interleaved ADC Systems'', IEEE [34] J. Kojima, et. al., "Limit Cycle Suppression Technique
Trans. Circuits and Systems I (March 2001). Using Digital Dither in Delta Sigma DA Modulator", IEEE
[13] R. Yi, et. al., “Digital Compensation for Timing ICSICT (Oct. 2016).
Mismatches in Interleaved ADCs”, IEEE ATS (Nov. 2013). [35] J. Otsuki, et. al., "Reducing Spurious Output of Balanced
[14] K. Asami, et. al., “Timing Skew Compensation Technique Modulators by Dynamic Matching of I, Q Quadrature Paths'',
using Digital Filter with Novel Linear Phase Condition”, IEEE IEEE MWSCAS (July 2004).
International Test Conference (Nov. 2010). [36] H. Kobayashi, et. al., “An Active Resistor Network for
[15] K. Asami, et. al., "Digitally-Assisted Compensation Gaussian Filtering of Images'', IEEE Journal of Solid-State
Technique for Timing Skew in ATE Systems", IEEE IMS3TW Circuits (May 1991).
(May 2011). [37] R. E. Crochiere, L. R. Rabiner, Multirate Digital Signal
[16] H. San, et. al., “A Second-Order Multi-bit Complex Processing, Prentice Hall (1996).
Bandpass ΔΣAD Modulator With I, Q Dynamic Matching and [38] M. L. E. Dickson, History of the Theory of Numbers,
DWA algorithm”, IEICE Trans. Electronics (June 2007). Diophantine Analysis, Dover (2005).
[17] M. Murakami, et. al, "I-Q Signal Generation Techniques for

Authorized licensed use limited to: ASELSAN A.S.. Downloaded on December 08,2023 at 13:06:36 UTC from IEEE Xplore. Restrictions apply.