Problems 69

PROBLEMS

(Answers to problems marked with * appear at the end of the text.)

2.1 Demonstrate the validity of the following identities by means of truth tables:
(a) DeMorgan’s theorem for three variables: (x + y + z)⬘ = x⬘y⬘z⬘ and (xyz)⬘ =
x⬘ + y⬘ + z⬘
(b) The distributive law: x + yz = (x + y)(x + z)
(c) The distributive law: x(y + z) = xy + xz
(d) The associative law: x + (y + z) = (x + y) + z
(e) The associative law and x(yz) = (xy)z
2.2 Simplify the following Boolean expressions to a minimum number of literals:
(a) * xy + xy⬘ (b) * (x + y) (x + y⬘)
(c) * xyz + x⬘y + xyz⬘ (d) * (A + B)⬘ (A⬘ + B⬘)⬘
(e) (a + b + c⬘)(a⬘ b⬘ + c) (f) a⬘bc + abc⬘ + abc + a⬘bc⬘
2.3 Simplify the following Boolean expressions to a minimum number of literals:
(a) * ABC + A⬘B + ABC⬘ (b)* x⬘yz + xz
(c) * (x + y)⬘ (x⬘ + y⬘) (d) * xy + x(wz + wz⬘)
(e) * (BC⬘ + A⬘D) (AB⬘ + CD⬘) (f) (a⬘ + c⬘) (a + b⬘ + c⬘)
2.4 Reduce the following Boolean expressions to the indicated number of literals:
(a) * A⬘C⬘ + ABC + AC⬘ to three literals
(b) * (x⬘y⬘ + z)⬘ + z + xy + wz to three literals
(c) * A⬘B(D⬘ + C⬘D) + B(A + A⬘CD) to one literal
(d) * (A⬘ + C) (A⬘ + C⬘) (A + B + C⬘D) to four literals
(e) ABC'D + A'BD + ABCD to two literals
2.5 Draw logic diagrams of the circuits that implement the original and simplified expressions
in Problem 2.2.
2.6 Draw logic diagrams of the circuits that implement the original and simplified expressions
in Problem 2.3.
2.7 Draw logic diagrams of the circuits that implement the original and simplified expressions
in Problem 2.4.
2.8 Find the complement of F = wx + yz; then show that FF⬘ = 0 and F + F⬘ = 1.
2.9 Find the complement of the following expressions:
(a) * xy⬘ + x⬘y (b) (a + c) (a + b⬘) (a⬘ + b + c⬘)
(c) z + z⬘(v⬘w + xy)
2.10 Given the Boolean functions F1 and F2 , show that
(a) The Boolean function E = F1 + F2 contains the sum of the minterms of F1 and F2.
(b) The Boolean function G = F1F2 contains only the minterms that are common to F1
and F2.
2.11 List the truth table of the function:
(a) * F = xy + xy⬘ + y⬘z (b) F = bc + a⬘c⬘
2.12 We can perform logical operations on strings of bits by considering each pair of correspond-
ing bits separately (called bitwise operation). Given two eight‐bit strings A = 10110001
and B = 10101100, evaluate the eight‐bit result after the following logical operations:
(a)* AND (b) OR (c)* XOR (d)* NOT A (e) NOT B
70 Chapter 2 Boolean Algebra and Logic Gates

2.13 Draw logic diagrams to implement the following Boolean expressions:

(a) y = [(u + x⬘) (y⬘ + z)]
(b) y = (u 䊝 y)⬘ + x
(c) y = (u⬘ + x⬘) (y + z⬘)
(d) y = u(x 䊝 z) + y⬘
(e) y = u + yz + uxy
(f) y = u + x + x⬘(u + y⬘)
2.14 Implement the Boolean function
F = xy + x⬘y⬘ + y⬘z
(a) With AND, OR, and inverter gates
(b) * With OR and inverter gates
(c) With AND and inverter gates
(d) With NAND and inverter gates
(e) With NOR and inverter gates
2.15* Simplify the following Boolean functions T1 and T2 to a minimum number of literals:

A B C T1 T2

0 0 0 1 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1

2.16 The logical sum of all minterms of a Boolean function of n variables is 1.

(a) Prove the previous statement for n = 3.
(b) Suggest a procedure for a general proof.
2.17 Obtain the truth table of the following functions, and express each function in sum‐of‐min-
terms and product‐of‐maxterms form:
(a) * (b + cd)(c + bd) (b) (cd + b⬘c + bd⬘)(b + d)
(c) (c⬘ + d)(b + c⬘) (d) bd⬘ + acd⬘ + ab⬘c + a⬘c⬘
2.18 For the Boolean function
F = xy⬘z + x⬘y⬘z + w⬘xy + wx⬘y + wxy
(a) Obtain the truth table of F.
(b) Draw the logic diagram, using the original Boolean expression.
(c) * Use Boolean algebra to simplify the function to a minimum number of literals.
(d) Obtain the truth table of the function from the simplified expression and show that
it is the same as the one in part (a).
(e) Draw the logic diagram from the simplified expression, and compare the total number
of gates with the diagram of part (b).
 Problems 71

2.19* Express the following function as a sum of minterms and as a product of maxterms:
F(A, B, C, D) = B⬘D + A⬘D + BD
2.20 Express the complement of the following functions in sum‐of‐minterms form:
(a) F(A,B ,C, D) = g (2, 4, 7, 10, 12, 14)
(b) F(x, y, z) = w (3, 5, 7)
2.21 Convert each of the following to the other canonical form:
(a) F(x, y, z) = g (1, 3, 5)
(b) F(A, B, C, D) = w (3, 5, 8, 11)
2.22* Convert each of the following expressions into sum of products and product of sums:
(a) (u + xw)(x + u⬘v)
(b) x⬘ + x(x + y⬘)(y + z⬘)
2.23 Draw the logic diagram corresponding to the following Boolean expressions without sim-
plifying them:
(a) BC⬘ + AB + ACD
(b) (A + B)(C + D)(A⬘ + B + D)
(c) (AB + A⬘B⬘)(CD⬘ + C⬘D)
(d) A + CD + (A + D')(C' + D)
2.24 Show that the dual of the exclusive‐OR is equal to its complement.
2.25 By substituting the Boolean expression equivalent of the binary operations as defined in
Table 2.8, show the following:
(a) The inhibition operation is neither commutative nor associative.
(b) The exclusive‐OR operation is commutative and associative.
2.26 Show that a positive logic NAND gate is a negative logic NOR gate and vice versa.
2.27 Write the Boolean equations and draw the logic diagram of the circuit whose outputs are
defined by the following truth table:

Table P2.27
f1 f2 a b c

1 1 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
1 0 1 0 0
0 1 1 0 1
1 0 1 1 1

2.28 Write Boolean expressions and construct the truth tables describing the outputs of the
circuits described by the logic diagrams in Fig. P2.28.
2.29 Determine whether the following Boolean equation is true or false.
x⬘y⬘ + x⬘z + x⬘z⬘ = x⬘z⬘ + y⬘z⬘ + x⬘z
72 Chapter 2 Boolean Algebra and Logic Gates

a
y1
a
b
b
c
c y
d y2
d
e
e
f
(a) (b)

FIGURE P2.28

2.30 Write the following Boolean expressions in sum of products form:

(b + d)(a⬘ + b⬘ + c)
2.31 Write the following Boolean expression in product of sums form:
a⬘b + a⬘c⬘ + abc

REFERENCES
1. Boole, G. 1854. An Investigation of the Laws of Thought. New York: Dover.
2. Dietmeyer, D. L. 1988. Logic Design of Digital Systems, 3rd ed. Boston: Allyn and Bacon.
3. Huntington, E. V. Sets of independent postulates for the algebra of logic. Trans. Am. Math.
Soc., 5 (1904): 288–309.
4. IEEE Standard Hardware Description Language Based on the Verilog Hardware Descrip-
tion Language, Language Reference Manual (LRM), IEEE Std.1364‐1995, 1996, 2001,
2005, The Institute of Electrical and Electronics Engineers, Piscataway, NJ.
5. IEEE Standard VHDL Language Reference Manual (LRM), IEEE Std. 1076‐1987, 1988,
The Institute of Electrical and Electronics Engineers, Piscataway, NJ.
6. Mano, M. M. and C. R. Kime. 2000. Logic and Computer Design Fundamentals, 2nd ed.
Upper Saddle River, NJ: Prentice Hall.
7. Shannon, C. E. A symbolic analysis of relay and switching circuits. Trans. AIEE, 57 (1938):
713–723.

WEB SEARCH TOPICS

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   9  

CHAPTER 2
 
2.1 (a)

 
xyz x+y+z (x + y + z)' x' y' z' x' y' z' xyz (xyz) (xyz)' x' y' z' x' + y' + z'

000 0 1 1 1 1 1 000 0 1 1 1 1 1
001 1 0 1 1 0 0 001 0 1 1 1 0 1
010 1 0 1 0 1 0 010 0 1 1 0 1 1
011 1 0 1 0 0 0 011 0 1 1 0 0 1
100 1 0 0 1 1 0 100 0 1 0 1 1 1
101 1 0 0 1 0 0 101 0 1 0 1 0 1
110 1 0 0 0 1 0 110 0 1 0 0 1 1
111 1 0 0 0 0 0 111 1 0 0 0 0 0

(b) (c)

xyz x + yz (x + y) (x + z) (x + y)(x + z) xyz x(y + z) xy xz xy + xz

000 0 0 0 0 000 0 0 0 0
001 0 0 1 0 001 0 0 0 0
010 0 1 0 0 010 0 0 0 0
011 1 1 1 1 011 0 0 0 0
100 1 1 1 1 100 0 0 0 0
101 1 1 1 1 101 1 0 1 1
110 1 1 1 1 110 1 1 0 1
111 1 1 1 1 111 1 1 1 1

(c) (d)

xyz x y+z x + (y + z) (x + y) (x + y) + z xyz yz x(yz) xy (xy)z

000 0 0 0 0 0 000 0 0 0 0
001 0 1 1 0 1 001 0 0 0 0
010 0 1 1 1 1 010 0 0 0 0
011 0 1 1 1 1 011 1 0 0 0
100 1 0 1 1 1 100 0 0 0 0
101 1 1 1 1 1 101 0 0 0 0
110 1 1 1 1 1 110 0 0 1 0
111 1 1 1 1 1 111 1 1 1 1  
 
2.2 (a) xy + xy' = x(y + y') = x

(b) (x + y)(x + y') = x + yy' = x(x +y') + y(x + y') = xx + xy' + xy + yy' = x

(c) xyz + x'y + xyz' = xy(z + z') + x'y = xy + x'y = y

(d) (A + B)'(A' + B')' = (A'B')(A B) = (A'B')(BA) = A'(B'B)A = 0

(e) (a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c'c = ac + bc +a'b'c'

(f) a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c') = a'b + ab = (a' + a)b = b
 
2.3 (a) ABC + A'B + ABC' = AB + A'B = B

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(b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y)

(c) (x + y)'(x' + y') = x'y'(x' + y') = x'y'

(d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y)

(e) (BC' + A'D)(AB' + CD') = BC'AB' + BC'CD' + A'DAB' + A'DCD' = 0

(f) (a' + c')(a + b' + c') = a'a + a'b' + a'c' + c'a + c'b' + c'c' = a'b' + a'c' + ac' + b'c' = c' + b'(a' + c')
= c' + b'c' + a'b' = c' + a'b'
 
2.4 (a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C'

(b) (x'y' + z)' + z + xy + wz = (x'y')'z' + z + xy + wz =[ (x + y)z' + z] + xy + wz =

= (z + z')(z + x + y) + xy + wz = z + wz + x + xy + y = z(1 + w) + x(1 + y) + y = x + y + z
 
(c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD)
= B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B

(d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D)
= AA' + A'B + A'C'D = A'(B + C'D)
 
(e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD

2.5 (a)
x y Fsimplified

(b)
x y
Fsimplified

      (c)

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x y z
Fsimplified

(d)
A B 0
Fsimplified

(e)

x y z
Fsimplified

(f)

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x y z

Fsimplified

2.6 (a)
A B C

Fsimplified

(b)
x y z

Fsimplified

(c)
x y

Fsimplified

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   13  

(d)
w x y z

Fsimplified

(e)
A B C D

Fsimplified = 0

(f)
w x y z

Fsimplified

 
2.7 (a)
A B C D

Fsimplified

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(b)
w x y z

Fsimplified

(c)
A B C D

Fsimplified

(d)
A B C D

Fsimplified

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(e)
A B C D

Fsimplified

 
 
2.8 F' = (wx + yz)' = (wx)'(yz)' = (w' + x')(y' + z')

FF' = wx(w' + x')(y' + z') + yz(w' + x')(y' + z') = 0

F + F' = wx + yz + (wx + yz)' = A + A' = 1 with A = wx + yz
 
2.9 (a) F' = (xy' + x'y)' = (xy')'(x'y)' = (x' + y)(x + y') = xy + x'y'

(b) F' = [(a + c) (a + b')(a' + b + c')]' = (a + c)' + (a + b')' + (a' + b + c')'

=a'c' + a'b + ab'c

(c) F' = [z + z'(v'w + xy)]' = z'[z'(v'w + xy)]' = z'[z'v'w + xyz']'

= z'[(z'v'w)'(xyz')'] = z'[(z + v + w') +( x' + y' + z)]
= z'z + z'v + z'w' + z'x' + z'y' +z' z = z'(v + w' + x' + y')
 
2.10 (a) F1 + F2 = Σ m1i + Σm2i = Σ (m1i + m2i)

(b) F1 F2 = Σ mi Σmj where mi mj = 0 if i ≠ j and mi mj = 1 if i = j

 
2.11 (a) F(x, y, z) = Σ(1, 4, 5, 6, 7)

(b) F(a, b, c) = Σ(0, 2, 3, 7)  

 
 
F = xy + xy' + y'z F = bc + a'c'
xyz F abc F

000 0 000 1
001 1 001 0
010 0 010 1
011 0 011 1
100 1 100 0
101 1 101 0
110 1 110 0
111 1 111 1  
 
 
2.12 A = 1011_0001
B = 1010_1100

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(a) A AND B = 1010_0000

(b) A OR B = 1011_1101
(c) A XOR B = 0001_1101
(d) NOT A = 0100_1110
(e) NOT B = 0101_0011
 
2.13 (a)
u x y z

(u + x')
Y = [(u + x')(y' + z)]

(y' + z)
 
 
      (b)
u x y

x
Y = (u xor y)' + x

(u xor y)'
(c)
u x y z

(u'+ x')
Y = (u'+ x')(y + z')

(y + z')
(d)
u x y z

u(x xor z)
Y = u(x xor z) + y'

y'
(e)
u x y z
u
yz
Y = u + yz +uxy

uxy

(f)

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   17  

u x y

Y = u + x + x'(u + y')

x'(u + y')
(u + y')

2.14 (a)

x y z

F =xy + x'y' + y'z

(b)

x y z

F = xy + x'y' + y'z

= (x' + y')' + (x + y)' + (y + z')'

 
(c)
x y z

F = xy + x'y' + y'z

= [(xy)' (x'y')' (y'z)']'

(d)
x y z

F = xy + x'y' + y'z

= [(xy)' (x'y')' (y'z)']'

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   18  

(e)
x y z

F = xy + x'y' + y'z

= (x' + y')' + (x + y)' + (y + z')'

 
2.15 (a) T1 = A'B'C' + A'B'C + A'BC' = A'B'(C' + C) +A'C'(B' + B) = A'B' +A'C' = A'(B' + C')

(b) T2 =T1' = A'BC + AB'C' + AB'C + ABC' + ABC

= BC(A' + A) + AB'(C' + C) + AB(C' + C)
= BC + AB' + AB = BC + A(B' + B) = A + BC

∑ (3, 5, 6, 7) = Π (0,1, 2, 4)
T1 = A'B'C' + A'B'C + A'BC' T2 = A'BC + AB'C' + AB'C + ABC' + ABC

A'B' A'C' AC' AC

T1 = A'B' A'C' = A'(B' + C')
BC
T2 =AC' + BC + AC = A+ BC

2.16 (a) F(A, B, C) = A'B'C' + A'B'C + A'BC' + A'BC + AB'C' + AB'C + ABC' + ABC
= A'(B'C' + B'C + BC' + BC) + A((B'C' + B'C + BC' + BC)
= (A' + A)(B'C' + B'C + BC' + BC) = B'C' + B'C + BC' + BC
= B'(C' + C) + B(C' + C) = B' + B = 1  

(b) F(x1, x2, x3, ..., xn) = Σmi has 2n/2 minterms with x1 and 2n/2 minterms with x'1, which can be factored
and removed as in (a). The remaining 2n-1 product terms will have 2n-1/2 minterms with x2 and 2n-1/2
minterms with x'2, which and be factored to remove x2 and x'2. continue this process until the last term is
left and xn + x'n = 1. Alternatively, by induction, F can be written as F = xnG + x'nG with G = 1. So F =
(xn + x'n)G = 1.

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   19  

2.17 (a) F = (b + cd)(c + bd) bc + bd + cd + bcd = Σ(3, 5, 6, 7, 11, 14, 15)

        F'  =   Σ(0, 1, 2, 4, 8, 9, 10, 12, 13)
F = Π(0, 1, 2, 4, 8, 9, 10, 12, 13)
 
abcd F
0000 0
0001 0
0010 0
0011 1
0100 0
0101 1
0110 1
0111 1
1000 0
1001 0
1010 0
1011 1
1100 0
1101 1
1110 1
1111 1  

      (b) (cd + b'c + bd')(b + d) = bcd + bd' + cd + b'cd = cd + bd'

= Σ (3, 4, 7, 11, 12,14, 15)
= Π (0, 1, 2, 5, 6, 8, 9, 10, 13)

abcd F
0000 0
0001 0
0010 0
0011 1
0100 1
0101 0
0110 0
0111 1
1000 0
1001 0
1010 0
1011 1
1100 1
1101 0
1110 1
1111 1

(c) (c' + d)(b + c') = bc' + c' + bd + c'd = (c' + bd)

= Σ (0, 1, 4, 5, 7, 8, 12, 13, 15)
F = Π (2, 3, 6, 9, 10, 11, 14)

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(d) bd' + acd' + ab'c + a'c' = Σ (0, 1, 4, 5, 10, 11, 14)

F' = Σ (2, 3, 6, 7, 8, 9, 12, 13, 15)
F = Π (02, 3, 6, 7, 8, 12, 13, 15)

abcd F
0000 1
0001 1
0010 0
0011 0
0100 1
0101 1
0110 0
0111 0
1000 0
1001 0
1010 1
1011 1
1100 1
1101 0
1110 1
1111 0

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   21  

2.18   (a)      
wx y z F F = xy'z + x'y'z + w'xy + wx'y + wxy
F = Σ(1, 5, 6, 7, 9, 10 11, 13, 14, 15 )
00 0 0 0
00 0 1 1
00 1 0 0
00 1 1 0
01 0 0 0
01 0 1 1
01 1 0 1
01 1 1 1
10 0 0 0
10 0 1 1
10 1 0 1
10 1 1 1
11 0 0 0
11 0 1 1
11 1 0 1
      11 1 1 1  
 
      (b)
x
y' 5 - Three-input AND gates
z 2 - Three-input OR gates
x' Alternative: 1 - Five-input OR gate
y' 4 - Inverters
z
w'
x
y
w
x'
y
w
x F
y

  (c) F = xy'z + x'y'z + w'xy + wx'y + wxy = y'z + xy + wy = yʹ′z + y(w + x)

(d) F = y'z + yw + yx) = Σ(1, 5, 9, 13 , 10, 11, 13, 15, 6, 7, 14, 15)
= Σ(1, 5, 6, 7, 9, 10, 11, 13, 14, 15)

(e)
y'
z F
y
x
w

1 – Inverter, 2 – Two-input AND gates, 2 – Two-input OR gates

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   22  

2.19 F = B'D + A'D + BD

ABCD ABCD ABCD

-B'-D A'--D -B-D

0001 = 1 0001 = 1 0101 = 5
0011 = 3 0011 = 3 0111 = 7
1001 = 9 0101 = 5 1101 = 13
1011 = 11 0111 = 7 1111 = 15  
 
    F = Σ(1, 3, 5, 7, 9, 11,13, 15) = Π(0, 2, 4, 6, 8, 10, 12, 14)

2.20 (a) F(A, B, C, D) = Σ(2, 4, 7, 10, 12, 14)

F'(A, B, C, D) = Σ(0, 1, 3, 5, 6, 8, 9, 11, 13, 15)

(b) F(x, y, z) = Π(3, 5, 7)

F' = Σ(3, 5, 7)

2.21 (a) F(x, y, z) = Σ(1, 3, 5) = Π(0, 2, 4, 6, 7)

(b) F(A, B, C, D) = Π(3, 5, 8, 11) = Σ(0, 1, 2, 4, 6, 7, 9, 10, 12, 13, 14, 15)
 
2.22 (a) (u + xw)(x + u'v) = ux + uu'v + xxw + xwu'v = ux + xw + xwu'v
= ux + xw = x(u + w)  
= ux + xw (SOP form)
= x(u + w) (POS form)

(b) x' + x(x + y')(y + z') = x' + x(xy + xz' + y'y + y'z')
= x' + xy + xz' + xy'z' = x' + xy +xz' (SOP form)
= (x' + y + z') (POS form)

2.23 (a) B'C +AB + ACD

A B C D

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   23  

(b) (A + B)(C + D)(A' + B + D)

A B C D

(c) (AB + A'B')(CD' + C'D)

A B C D

(d) A + CD + (A + D')(C' + D)

A B C D

2.24 x ⊕ y = x'y + xy' and (x ⊕ y)' = (x + y')(x' + y)

Dual of x'y + xy' = (x' + y)(x + y') = (x ⊕ y)'

2.25 (a) x| y = xy' ≠ y | x = x'y Not commutative

(x | y) | z = xy'z' ≠ x | (y | z) = x(yz')' = xy' + xz Not associative

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   24  

(b) (x ⊕ y) = xy' + x'y = y ⊕ x = yx' + y'x Commutative

(x ⊕ y) ⊕ z = ∑(1, 2, 4, 7) = x ⊕ (y ⊕ z) Associative

2.26

NAND NOR
Gate (Positive logic) (Negative logic)
xy z xy z xy z

LL H 00 1 11 0
LH H 01 1 10 0
HL H 10 1 01 0
HH L 11 0 00 1

NOR NAND
Gate (Positive logic) (Negative logic)
xy z xy z xy z

LL H 00 1 11 0
LH L 01 0 10 1
HL L 10 0 01 1
HH L 11 0 00 1

2.27 f1 = a'b'c' + a'bc' + a'bc + ab'c' + abc = a'c' + bc + a'bc' + ab'c'

f2 = a'b'c' + a'b'c + a'bc + ab'c' + abc = a'b' + bc + ab'c'

a' a'
b'
a' c'
a' b
b
c' c f1
a' a'
b b
c c'
a' a
b f1 b'
c c'
a
b
c
a'
b' a'
f2
b'
c
a' b
b f2
c c
a a
b' b'
c c'

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   25  

2.28 (a) y = a(bcd)'e = a(b' + c' + d')e

y = a(b' + c' + d')e = ab’e + ac’e + ad’e

= Σ( 17, 19, 21, 23, 25, 27, 29)
a bcde y a bcde y

0 0000 0 1 0000 0
0 0001 0 1 0001 1
0 0010 0 1 0010 0
0 0011 0 1 0011 1
0 0100 0 1 0100 0
0 0101 0 1 0101 1
0 0110 0 1 0110 0
0 0111 0 1 0111 1
0 0
0 1000 0 1 1000 0
0 1001 0 1 1001 1
0 1010 0 1 1010 0
0 1011 0 1 1011 1
0 1100 0 1 1100 0
0 1101 0 1 1101 1
0 1110 0 1 1110 0
0 1111 0 1 1111 0

(b) y1 = a ⊕ (c + d + e)= a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e'

y2 = b'(c + d + e)f = b'cf + b'df + b'ef

y1 = a (c + d + e) = a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e'

y2 = b'(c + d + e)f = b'cf + b'df + b'ef

a'-c--- a'--d-- a'---e- a-c'd'e'-

001000 = 8 000100 = 8 000010 = 2 100000 = 32
001001 = 9 000101 = 9 000011 = 3 100001 = 33
001010 = 10 000110 = 10 000110 = 6 110000 = 34
001011 = 11 000111 = 11 000111 = 7 110001 = 35
001100 = 12 001100 = 12 001010 = 10
001101 = 13 001101 = 13 001011 = 11
001110 = 14 001110 = 14 001110 = 14
001111 = 15 001111 = 15 001111 = 15 -b' c--f -b' -d-f -b' --ef

011000 = 24 010100 = 20 010010 = 18 001001 = 9 001001 = 9 000011 = 3

011001 = 25 010101 = 21 010011 = 19 001011 = 11 001011 = 11 000111 = 7
011010 = 26 010110 = 22 010110 = 22 001101 = 13 001101 = 13 001011 = 11
011011 = 27 010111 = 23 010111 = 23 001111 = 15 001111 = 15 001111 = 15
101001 = 41 101001 = 41 100011 = 35
011100 = 28 011100 = 28 011010 = 26 101011 = 43 101011 = 43 100111 = 39
011101 = 29 011101 = 29 011001 = 27
011110 = 30 011110 = 30 011110 = 30 101101 = 45 101101 = 45 101011 = 51
011111 = 31 011111 = 31 011111 = 31 101111 = 47 101111 = 47 101111 = 55

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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   26  

y1 = Σ (2, 3, 6, 7, 8, 9, 10 ,11, 12, 13, 14, 15, 18, 19, 22, 23, 24, 25, 26, 27, 28,
29, 30, 31, 32, 33, 34, 35 )

y2 = Σ (3, 7, 9, 13, 15, 35, 39, 41, 43, 45, 47, 51, 55)
ab cdef y1 y2 ab cdef y1 y2 ab cdef y1 y2 ab cdef y1 y2

00 0000 0 0 01 0000 0 0 10 0000 1 0 11 0000 0 0

00 0001 0 0 01 0001 0 0 10 0001 1 0 11 0001 0 0
00 0010 1 0 01 0010 1 0 10 0010 1 0 11 0010 0 0
00 0011 1 1 01 0011 1 0 10 0011 1 1 11 0011 0 1
00 0100 0 0 01 0100 0 0 10 0100 0 0 11 0100 0 0
00 0101 0 0 01 0101 0 0 10 0101 0 0 11 0101 0 0
00 0110 1 0 01 0110 1 0 10 0110 0 0 11 0110 0 0
00 0111 1 1 01 0111 1 0 10 0111 0 1 11 0111 0 1

00 1000 1 0 01 1000 1 0 10 1000 0 0 11 1000 0 0

00 1001 1 1 01 1001 1 0 10 1001 0 1 11 1001 0 0
00 1010 1 0 01 1010 1 0 10 1010 0 0 11 1010 0 0
00 1011 1 0 01 1011 1 0 10 1011 0 1 11 1011 0 0
00 1100 1 0 01 1100 1 0 10 1100 0 0 11 1100 0 0
00 1101 1 1 01 1101 1 0 10 1101 0 1 11 1101 0 0
00 1110 1 0 01 1110 1 0 10 1110 0 0 11 1110 0 0
00 1111 1 1 01 1111 1 0 10 1111 0 1 11 1111 0 0

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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