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Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design
Article in International Journal of Computer Applications · November 2013
DOI: 10.5120/14264-2408
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International Journal of Computer Applications (0975 – 8887)
Volume 82 – No 18, November 2013
Analysis of Leakage Power Reduction Techniques for
Low Power VLSI Design
K.Sailaja V. Leela Rani Sk.Mahammad Akram
Department of ECE Department of ECE Department of ECE
G.V.P.College of Engineering G.V.P.College of Engineering G.V.P.College of Engineering
Visakhapatnam, AP, India Visakhapatnam, AP, India Visakhapatnam, AP, India
ABSTRACT 2. 8 BIT CARRY-SAVE MULTIPLIER
Power dissipation has become one of the major concerns of The basic principle involved in multiplication is the
VLSI circuit design with the rapid launching of battery evaluation of partial products and accumulation of shifted
operated applications. In high performance designs, the partial products. In order to perform this operation, numbers
leakage component of power consumption is comparable to of successive addition operations are required. Therefore one
the switching component. This percentage will increase with of the major components required to design a multiplier is
technology scaling unless effective techniques are introduced Adder. Variety of adders can be used like Ripple Carry, Carry
to bring leakage under control. In this paper, an 8X8 Look Ahead, Carry Select, Carry Skip and Carry Save. A
multiplier is designed using different leakage power reduction parallel multiplier is for unsigned operands. It is composed of
techniques like MTCMOS, DUAL-Vt and LECTOR. All the 2-input AND gates for producing the partial products, a series
above mentioned techniques are simulated using Cadence of carry save adders for adding them and a ripple-carry adder
virtuoso tool in 90nm technology. for producing the final product. The multiplier architecture
with CSA gives better performance in terms of area, speed
Keywords and power consumption as compared to the architecture with
8X8 multiplier, MTCMOS, DUAL-Vt, LECTOR, Proposed RCA. Basically, sum of three or more n-bit binary numbers
methods can be computed using this carry save adder. Carry save adder
is same as a full adder.
1. INTRODUCTION
The rapid increase in semiconductor technology led the
feature sizes to be shrinking by using deep-submicron
processes. System on a chip (SoC) is an integrated circuit that
integrates complex functions on a single chip. In the growing
market of mobile hand-held devices used all over the world
today, the battery-powered electronic system forms the
backbone. To maximize the battery life, the tremendous
computational capacity of portable devices such as notebook
computers, personal communication devices (mobile phones,
pocket PCs, PDAs), hearing aids and implantable pacemakers
has to be realized with very low power requirements. With
miniaturization and the growing trend towards wireless
communication, power dissipation has become a very critical
design metric. The longer the battery lasts, the better is the
device.
With the advancement in technology, static power dominates
dynamic power. Leakage currents are especially important in
burst mode type integrated circuits where most of the time the
system is in an idle, or sleep mode. No computation takes
place during sleep mode [1]. For example, a cell phone will be
in the standby mode for most of the time where the processor
is in idle state. With the large leakage currents during the idle
mode power will be continuously drained with no useful work Fig 1: General architecture of 4X4 Carry-save
being done. multiplier[1]
Many techniques have been proposed [2] to minimize these
leakage currents in nanometer technology. Excessive power Carry unit consists of series of full adders, each of which
dissipation in portable devices causes overheating, reduces computes single sum and carry bit based on the
chip life, functionality and degrades performance. Minimizing corresponding bits of the two input numbers.
power consumption is therefore important and necessary, both The final addition is then computed as:
for increasing levels of integration and to improve reliability,
1. Shifting the carry sequence C left by one place.
feasibility and cost.
2. Placing a 0 to the front (MSB) of the partial sum sequence
S.
20
International Journal of Computer Applications (0975 – 8887)
Volume 82 – No 18, November 2013
3. Finally, a ripple carry adder is used to add these two additional transistors are required as in the case of multi-
together and computing the resulting sum. threshold voltage technique. Reduction of static power is
Because of size limitations, a 4X4 version with a critical path achieved while maintaining the same performance as single
highlighted [3] is shown in above Fig 1. threshold voltage circuit [6], [7]. Care should be taken while
designing, is that if all the transistors in the non-critical paths
3. LEAKAGE REDUCTION are assigned with HVT, non-critical path may become a new
TECHNIQUES critical path with a larger path delay than the original one,
deteriorating the speed of the circuit.
3.1 MTCMOS
The low-power and high performance design requirements of
modern VLSI technology can be achieved by using 3.3 LEAKAGE CONTROL
MTCMOS technology. Low, normal and high threshold TRANSISTOR (LECTOR) Technique
voltage transistors are used to design a CMOS circuit in this The effective stacking of transistors in the path from supply
technique. With the scaling of CMOS technology, Supply and voltage to ground is the basic idea behind the LECTOR
threshold voltages are reduced. Sub threshold leakage current technique for the leakage power reduction. This states that “a
increases exponentially with lowering of threshold voltage. state is far less leaky with more than one OFF transistor in a
path from supply voltage to ground compared to a state with
Vdd
Vdd
SLEEP
Virtual Vdd
In1
INPUTS Low-Vt CMOS logic
OUTPUTS PUN
Maintain High Performance Inn
during Active Mode
N1
Virtual GND LCT1
out
SLEEP LCT2
Gnd
N2
Fig 2: General MTCMOS circuit architecture
Multi-threshold CMOS (MTCMOS) is a design technique in PDN
which high threshold sleep transistors are connected between
the logic circuit and power or ground, thus creating a virtual Gnd
supply rail or virtual ground rail, respectively. The low-
threshold voltage transistors which have high performance are only one OFF transistor in the path”
used to reduce the propagation delay time in the critical path.
The high-threshold voltage transistors which have less power
consumption are used to reduce the power consumption in the
shortest path [4],[5]. Fig 3: LECTOR CMOS GATE
Fig.2 shows MTCMOS circuit technology which satisfies The LECTOR implementation involves the addition of two
both the requirements of lowering the threshold voltage to LCTS for each gate between the supply and ground path [8].
obtain high speed and reducing standby current to have low The general architecture of the LECTOR technique is shown
power. The two main features of this technique are employing in Fig.3.
two different threshold voltages on a single circuit and having
two operational modes active & sleep for efficient power
4. PROPOSED METHODS
management. 4.1 PROPOSED METHOD1
This is a modified structure of MTCMOS technique. In this
3.2 DUAL-Vt structure, the NMOS HVT sleep transistor is arranged as a
Dual threshold voltage technique also uses two threshold stack of two transistors with width twice that of original one.
voltages as in the case of MTCMOS. Here, high threshold A state is far less leaky with more than one OFF transistor
voltage (HTV) is assigned to transistors of some gates in the compared to a state with only one OFF transistor in the path.
non-critical paths while specifying the low-threshold voltage This modified method reduces the leakage power to a great
for the gates in the critical path. In this technique, no extent compared to that of existing.
21
International Journal of Computer Applications (0975 – 8887)
Volume 82 – No 18, November 2013
Vdd
Vdd
SLEEP Pin
Virtual Vdd
INPUTS OUTPUTS
Low-Vt CMOS logic
Maintain High Performance INPUTS Multiplier applied OUTPUTS
during Active Mode with LECTOR
technique
Virtual GND
2W Gnd
Fig 6: Logic diagram of proposed method 3
SLEEP
2W 5. EXPERIMENTAL ANALYSIS
In this paper an 8X8 multiplier is designed using leakage
power reduction techniques like MTCMOS, DUAL-Vt,
LECTOR and proposed methods. These designs are simulated
using Cadence virtuoso tool in 90nm technology. Table.1
shows the simulation results of all the above techniques in
Fig 4: Logic diagram of proposed method1 terms of average power, Delay and static power.
Figure [7], [8] and [9] represents the comparison of above
4.2 PROPOSED METHOD2 techniques in terms of average power, delay and static power.
It is an improvised structure of existing dual-Vt technique. An From the simulation results, proposed methods give 99.99%,
NMOS transistor is kept between ground and logic circuit. 99.02% and 99.98% of reduction in static power respectively.
Vdd
Table1. Simulation results of an 8X8 multiplier
INPUTS OUTPUTS Average
Dual-Vt multiplier Delay Static
Method power
(ps) power(w)
(µw)
Basic
62.75 91.84 3.3263 e-6
Sin multiplier
Multi-
28.98 274.76 3.7387 e-11
threshold
Gnd
Dual-
Fig 5: Logic diagram of proposed method2 20.71 119.80 7.1452e-7
threshold
In active mode, NMOS will be kept ON allowing the circuit to
operate normally. In inactive mode NMOS will be kept OFF LECTOR 28.27 130.85 6.3806e-6
which provides high resistance path between power supply
and ground. The NMOS is kept ON/OFF by means of
Proposed
controlling input Sin. 26.89 346.94 8.4968e-12
method1
4.3 PROPOSED METHOD 3
In the proposed design, the critical path blocks in an 8 bit Proposed
19.84 145.15 3.2453e-8
carry-save multiplier are replaced with LCT blocks and other method2
non-critical path blocks are assigned with high threshold
voltage. A PMOS transistor is kept over the developed logic Proposed
16.51 137.50 4.4948e-10
which intern cut-off the power supply to the logic block in method3
inactive mode.
22
International Journal of Computer Applications (0975 – 8887)
Volume 82 – No 18, November 2013
6. CONCLUSIONS
70
average power(uw) In this paper multiplier is designed with different leakage
60 power reduction techniques like Multi-Vt, Dual-Vt, LECTOR
average power and proposed methods. Proposed method1 is an effective
50
40 circuit level technique that enhances the performance and
30 provides low design methodologies by using both low and
20 high threshold voltage transistors. From Simulation results it
10 is concluded that proposed method1 effectively reduces
0 leakage power to an extent of 99%.
7. ACKNOWLEDGMENTS
The CADENCE TOOLS were procured for this project under
Research Promotion Scheme (RPS) from AICTE. We express
our gratitude to AICTE for the RPS funding.
8. REFERENCES
[1] Farzan Fallah, Massoud Pedram “Standby and Active
Fig 7: comparing average power of above techniques Leakage Current Control and Minimization in CMOS
VLSI Circuits” IEICE Transactions, 2005, pp.509-519.
[2] Kaushik Roy, Saibal Mukhopadhyay and Hamid
delay(ps) Mahmoodi-Meimand, “Leakage Current Mechanisms
and Leakage Reduction Techniques in Deep-Sub
micrometer CMOS Circuits,” PROCEEDINGS OF THE
400 delay(ps) IEEE, VOL. 91, NO. 2, FEBRUARY 2003.
350
300 [3] James T. Kao and Anantha P. Chandrakasan, “Dual-
250 Threshold Voltage Techniques for Low-Power Digital
200 Circuits,” IEEE JOURNAL OF SOLID-STATE
150
100 CIRCUITS, VOL. 35, NO. 7, JULY 2000.
50 [4] Shyam Akashe, Nitesh Kumar Tiwari, Jayram Shrivas
0
and Rajeev Sharma, ”A Novel High Speed & Power
Efficient Half Adder Design Using MTCMOS Technique
in 45 Nanometre Regime” IEEE International
Conference on Advanced Communication Control and
Computing Technologies (ICACCCT) 2012.
[5] Milind Gautam and Shyam Akashe, “Reduction of
Leakage Current and Power in Full Subtractor Using
MTCMOS Technique” 2013 International Conference on
Computer Communication and Informatics (ICCCI -
Fig 8: comparing average power of above techniques 2013), Jan. 04 – 06, 2013.
[6] J. Jaffari and A. Afzali-Kusha, “New Dual-Threshold
Voltage Assignment Technique for Low-Power Digital
Static power(Watts) Circuits,” 0-7803-8656-6/04/$20.00, pp.413-416 IEEE
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1.00E-14
1.00E-12 [7] L. Wei. 2. Chen, K. Roy, M. C. Johnson, Y. Ye and V.
1.00E-10 De, “Design and optimization of dual threshold circuits
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Fig 9: comparing static power of above techniques
IJCATM: www.ijcaonline.org 23
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