Syllabus

Syllabus

Department of Electrical Engineering,

Syllabus of Bachelor of Technology in Electrical Engineering, 2010

MICROPROCESSOR & MICRO CONTROLLER THEORY & APPLICATION (3-1-

0)
MODULE-I {10 HOURS)
Microprocessor Architecture: Introduction to Microprocessor and Microcomputer Architecture, Pins
& Signals, Register Organization, Timing & Control Module, 8085 Instruction Timing & Execution,
Instruction Set and Assembly Language Programming of 8085:- Instruction set of 8085, Memory &
0 Addressing, Assembly language programming using 8085 Instruction Set, Use of Stack &
Subroutines, Data transfer techniques, 8085 interrupts
MODULE-IT (10 HOURS)
Interfacing & support chips: Interfacing EPROM & RAM Memories, 2716, 2764, 6116 & 6264
Microprocessor Based System Development Aids, Programmable Peripheral Interface: $233,
Programmable DMA Controller: 8257, Programmable Interrupt Controller: 8259

Application: Delay calculation, square wave generation, Interfacing of ADC & DAC, Data
Acquisition System,

MODULE-HI (10 HOURS)

Advanced Microprocessor: Basic features of Advance Microprocessors, Intel 8086 (16 bit

processors)- 8086 Architecture, Register organization, signal descriptions, Physical Memory

Organization, Addressing Modes, Instruction Formats, Instructions Sets & Simple Assembly
language programmes, 8086 Interrupts.
Simple application: Delay calculation, square wave generation
MODULE-IV (10 HOURS)
Microcontroller:- Introduction for Microcontrollers, Microcontrollers & Microprocessors, Embedded
verses External Memory devices, CISC & RISC Processors, Havard & Von Neumann

Architectures, $051 Microcontrollers, MCS-51 Architecture, Registers, Stack Pointer & Program
Counter. 8051 Pin Description, Connections, Parallel IQ ports, Memory Organization, 8051
Addressing Modes& Instructions, 8031 Assembly Language Programming Tools.
Simple application: Delay calculation, square wave generation, Interfacing of LCD unit,
 Disclaimer
Disclaimer

This document
This document does does not not claim
claim any any originality
originality and and cannot
cannot be be used
used asas a a
substitute
substitute for
for prescribed textbooks. The
prescribed textbooks. The information
information presented
presented here here is
is merely
merely a a
collection by
collection by the the committee
committee membersmembers for their respective
for their respective teaching
teaching
assignments. Various
assignments. Various sources
sources as as mentioned
mentioned at at the
the end
end of of the
the document
document as as well
well
as freely
as available material
freely available material from internet were
from internet were consulted
consulted for for preparing
preparing thisthis
document. The
document. The ownership
ownership of of the
the information
information lies lies with
with the
the respective
respective authors
authors or or
institutions. Further,
institutions. Further, this this document
document is is not
not intended
intended to to be
be used
used for commercial
for commercial
purpose
purpose andand the
the committee
committee members
members are are not
not accountable
accountable for any issues,
for any issues, legal,
legal,
or otherwise,
or otherwise, arising
arising out out of
of this
this document.
document. The The committee
committee membersmembers make make no no
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warranties with with respect
respect to to the
the accuracy
accuracy or or completeness
completeness of of
the contents
the contents of
of this
this document
document and and specially disclaim any
specially disclaim any implied
implied warranties
warranties of of
merchantability or
merchantability or fitness
fitness for
for aa particular
particular purpose.
purpose. The The committee
committee members
members
shall not be
shall not be liable
liable for any loss
for any loss oror profit
profit oror any
any other
other commercial
commercial damages,
damages,
including but
including but notnot limited
limited to to special, incidental, consequential,
special, incidental, consequential, or or other
other
damages.
damages.
MODULE: 11
MODULE:

1. INTRODUCTION
1. INTRODUCTION TO
TO MICROPROCESSOR
MICROPROCESSOR AND
AND MICROCOMPUTER
MICROCOMPUTER
ARCHITECTURE:
ARCHITECTURE:

AA microprocessor
microprocessor is is aa programmable electronics chip
programmable electronics chip that
that has
has computing
computing and and decision
decision
making capabilities
making capabilities similar
similar to to central
central processing
processing unitunit ofof aa computer.
computer. AnyAny microprocessor-
microprocessor-
based systems having
based systems having limited
limited number
number of of resources
resources are are called
called microcomputers.
microcomputers. Nowadays,
Nowadays,
microprocessor can
microprocessor can bebe seen
seen inin almost
almost allall types
types of
of electronics
electronics devices
devices like
like mobile
mobile phones,
phones,
printers, washing machines
printers, washing machines etc. etc. Microprocessors
Microprocessors are are also
also used
used inin advanced
advanced applications
applications like
like
radars, satellites and
radars, satellites and flights.
flights. Due
Due toto the
the rapid
rapid advancements
advancements in in electronic
electronic industry
industry and
and large
large
scale integration
scale integration ofof devices
devices results
results inin aa significant
significant cost
cost reduction
reduction andand increase
increase application
application ofof
microprocessors and
microprocessors and their
their derivatives.
derivatives.

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Fig.1 Microprocessor-based
Fig.1 Microprocessor-based system
system

e Bit: A
Bit: A bit
bit is
is aa single
single binary
binary digit.digit.
eo Word:
Word: A A word
word refers
refers toto thethe basic
basic data
data sizesize oror bit
bit size
size that
that can
can bebe processed
processed by by the
the
arithmetic and
arithmetic and logic
logic unit
unit of of the
the processor.
processor. A A 16-bit
16-bit binary number is
binary number is called
called aa word
word in in
aa 16-bit
16-bit processor.
processor.
e Bus: A
Bus: A bus
bus is is aa group
group ofof wires/lines
wires/lines that that carry
carry similar
similar information.
information.
oe System Bus:
System Bus: The The system
system bus bus is is aa group
group of of wires/lines
wires/lines used used for for communication
communication
between
between the the microprocessor
microprocessor and and peripherals.
peripherals.
e Memory Word:
Memory Word: The The number
number of of bits
bits that
that can
can be be stored
stored in in aa register
register or or memory
memory
element is
element is called
called aa memory
memory word. word.
e Address
Address Bus: Bus: It It carries
carries thethe address,
address, which which is is aa unique
unique binary
binary pattern
pattern usedused toto identify
identify
aa memory
memory location
location or or anan I/O I/O port.
port. For For example,
example, an an eight
eight bitbit address
address busbus hashas eight
eight
8
lines and
lines and thusthus it it can
can address
address 2 2° = = 256
256 different
different locations.
locations. The The locations
locations in in
hexadecimal format
hexadecimal format can can be be written
written as as 00H00H —– FFH.
FFH.
e Data Bus:
Data Bus: TheThe datadata bus
bus is is used
used to to transfer
transfer datadata between
between memory
memory and and processor
processor or or
between
between I/O I/O device
device and and processor.
processor. For For example,
example, an an 8-bit
8-bit processor
processor will generally
will generally
have an
have an 8-bit
8-bit data
data bus
bus and
and aa 16-bit
16-bit processor
processor will will have
have 16-bit
16-bit data
data bus.
bus.
e Control Bus:
Control Bus: The The control
control bus bus carry
carry control
control signals,
signals, which
which consists
consists of of signals
signals for for
selection of
selection of memory
memory or or I/O
I/O device
device from from the the given
given address,
address, direction
direction of of data
data transfer
transfer
and synchronization
and synchronization of of data
data transfer
transfer in in case
case ofof slow
slow devices.
devices.
AA typical
typical microprocessor
microprocessor consists
consists of of arithmetic
arithmetic andand logic
logic unit (ALU) in
unit (ALU) in association
association withwith
control unit
control unit to
to process the instruction
process the instruction execution.
execution. Almost
Almost all all the
the microprocessors
microprocessors are are based
based
on the
on the principle
principle of of store-program
store-program concept.concept. In In store-program
store-program concept, concept, programs
programs or or
instructions are
instructions are sequentially
sequentially stored
stored in in the
the memory
memory locations
locations thatthat are
are to
to be
be executed.
executed. To To dodo
any task
any task using
using aa microprocessor,
microprocessor, it it isis to
to be
be programmed
programmed by by the
the user.
user. SoSo the
the programmer
programmer
must have
must have idea
idea about
about its
its internal
internal resources,
resources, features
features and and supported
supported instructions.
instructions. Each
Each
microprocessor has
microprocessor has aa set
set of
of instructions,
instructions, aa listlist which
which is is provided
provided by by the
the microprocessor
microprocessor
manufacturer. The
manufacturer. The instruction
instruction set
set ofof aa microprocessor
microprocessor is is provided
provided in in two
two forms:
forms: binary
binary
machine code
machine code and
and mnemonics.
mnemonics.

Microprocessor communicates
Microprocessor communicates and and operates
operates in in binary
binary numbers
numbers 0 0 and
and 1. 1. The
The setset ofof
instructions in
instructions in the
the form
form ofof binary
binary patterns is called
patterns is called aa machine
machine language
language and
and it
it is
is difficult
difficult for
for
us to understand.
us to understand. Therefore,
Therefore, thethe binary
binary patterns
patterns areare given
given abbreviated
abbreviated names,
names, called
called
mnemonics, which
mnemonics, forms the
which forms the assembly
assembly language.
language. The The conversion
conversion of of assembly-level
assembly-level
language into
language into binary
binary machine-level
machine-level language
language is is done
done byby using
using anan application
application calledcalled
assembler.
assembler.

Technology Used:
Technology Used:

The semiconductor
The semiconductor manufacturing
manufacturing technologies
technologies used for chips
used for chips are:
are:

e Transistor-Transistor Logic
Transistor-Transistor Logic (TTL)
(TTL)
e Emitter Coupled
Emitter Coupled Logic
Logic (ECL)
(ECL)
eo Complementary Metal-Oxide
Complementary Metal-Oxide Semiconductor
Semiconductor (CMOS)
(CMOS)

Classification of
Classification of Microprocessors:
Microprocessors:

Based on
Based on their
their specification,
specification, application
application and
and architecture
architecture microprocessors
microprocessors are
are classified.
classified.

Based on size
Based on of data
size of data bus:
bus:

e 4-bit microprocessor
4-bit microprocessor
e 8-bit microprocessor
8-bit microprocessor
e 16-bit microprocessor
16-bit microprocessor
e 32-bit microprocessor
32-bit microprocessor

Based on application:
Based on application:

e General-purpose microprocessor-
General-purpose microprocessor- usedused inin general
general computer
computer system
system and
and can
can be
be used
used
by
by programmer for any
programmer for any application.
application. Examples,
Examples, 80858085 toto Intel
Intel Pentium.
Pentium.
e Microcontroller- microprocessor
Microcontroller- microprocessor with with built-in
built-in memory
memory and and ports and can
ports and can be
be
programmed
programmed forfor any
any generic
generic control
control application.
application. Example,
Example, 8051.
8051.
e Special-purpose processors-
Special-purpose designed to
processors- designed to handle
handle special
special functions
functions required
required for
for an
an
application. Examples,
application. Examples, digital
digital signal
signal processors
processors andand application-specific
application-specific integrated
integrated
circuit (ASIC)
circuit (ASIC) chips.
chips.
Based on architecture:
Based on architecture:

e Reduced Instruction
Reduced Instruction Set
Set Computer
Computer (RISC)
(RISC) processors
processors
e Complex Instruction
Complex Instruction Set
Set Computer
Computer (CISC)
(CISC) processors
processors

2. 8085
2. 8085 MICROPROCESSOR
MICROPROCESSOR ARCHITECTURE
ARCHITECTURE

The 8085
The 8085 microprocessor
microprocessor is is an
an 8-bit
8-bit processor available as
processor available as aa 40-pin
40-pin ICIC package and uses
package and uses +5
+5
VV for
for power.
power. ItIt can
can run
run at
at aa maximum
maximum frequency
frequency ofof 33 MHz.
MHz. ItsIts data
data bus
bus width
width is
is 8-bit
8-bit and
and
16
address bus
address bus width
width isis 16-bit,
16-bit, thus
thus it
it can
can address
address 2 2'® == 64
64 KBKB ofof memory.
memory. The
The internal
internal
architecture of
architecture of 8085
8085 is
is shown
shown is is Fig.
Fig. 2.
2.

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Fig. 2
Fig. 2 Internal
Internal Architecture
Architecture of
of 8085
8085

Arithmetic and Logic

Arithmetic and Logic Unit
Unit

The ALU
The ALU performs the actual
performs the actual numerical
numerical and and logical
logical operations
operations such
such as
as Addition
Addition (ADD),
(ADD),
Subtraction (SUB),
Subtraction (SUB), AND,
AND, OR OR etc.
etc. It
It uses data from
uses data from memory
memory and and from
from Accumulator
Accumulator to to
perform operations. The
perform operations. The results
results of
of the
the arithmetic
arithmetic andand logical
logical operations
operations are
are stored
stored in
in the
the
accumulator.
accumulator.

Registers
Registers

The 8085
The 8085 includes
includes sixsix registers,
registers, one
one accumulator
accumulator and
and one
one flag
flag register,
register, as
as shown
shown in
in Fig.
Fig. 3.
3.
In addition,
In addition, itit has
has two
two 16-bit
16-bit registers:
registers: stack
stack pointer and program
pointer and counter. They
program counter. They are
are briefly
briefly
described as
described as follows.
follows.

The 8085
The 8085 has
has six
six general-purpose
general-purpose registers
registers toto store
store 8-bit
8-bit data;
data; these
these are
are identified
identified as
as B,
B, C,
C,
D, E,
D, E, HH and
and L.
L. they
they can
can be
be combined
combined asas register
register pairs
pairs -- BC,
BC, DE
DE and
and HL
HL to
to perform
perform some
some
16-bit operations.
16-bit operations. The
The programmer
programmer cancan use these registers
use these registers to
to store
store or
or copy
copy data
data into
into the
the
register by using
register by data copy
using data copy instructions.
instructions.

ER R= [TTTT 1

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

8 Lines Bidirectional 16 Lines unidirectional

Fig. 33 Register
Fig. Register organisation
organisation

Accumulator
Accumulator

The accumulator
The accumulator isis an
an 8-bit
8-bit register
register that
that is
is aa part of ALU.
part of ALU. This
This register
register is
is used
used to
to store
store 8-bit
8-bit
data and
data and to
to perform arithmetic and
perform arithmetic and logical
logical operations.
operations. The
The result
result of
of an
an operation
operation is
is stored
stored in
in
the accumulator.
the accumulator. The
The accumulator
accumulator is is also
also identified
identified as
as register
register A.
A.

Flag register
Flag register

The ALU
The ALU includes
includes five
five flip-flops,
flip-flops, which
which are
are set
set or
or reset
reset after
after an
an operation
operation according
according toto data
data
condition of
condition of the
the result
result in
in the
the accumulator
accumulator and
and other
other registers.
registers. They
They areare called
called Zero
Zero (Z),
(Z),
Carry (CY),
Carry (CY), Sign
Sign (S),
(S), Parity
Parity (P)
(P) and
and Auxiliary
Auxiliary Carry
Carry (AC)
(AC) flags.
flags. Their
Their bit
bit positions
positions inin the
the
flag register
flag register are
are shown
shown inin Fig.
Fig. 4.
4. The
The microprocessor
microprocessor uses these flags
uses these flags to
to test
test data
data conditions.
conditions.

D~ Ds Ds Da Ds D2 D1 Do

S Z AC Pp CY

Fig. 4
Fig. 4 Flag
Flag register
register

For example,
For example, after
after anan addition
addition of of two
two numbers,
numbers, if if the
the result
result inin the
the accumulator
accumulator is is larger
larger than
than
8-bit, the
8-bit, the flip-flop
flip-flop usesuses toto indicate
indicate aa carry
carry byby setting
setting CY CY flagflag to
to 1.
1. When
When an an arithmetic
arithmetic
operation results
operation results in in zero,
zero, Z Z flag
flag is
is set
set to
to 1.
1. The
The S S flag
flag isis just
just aa copy
copy ofof the
the bit
bit D7 D7 ofof the
the
accumulator. A
accumulator. A negative
negative number
number has has aa 11 in
in bit
bit D7D7 and and aa positive number has
positive number has aa 00 in in 2’s
2’s
complement representation.
complement representation. The The ACAC flagflag is
is set
set toto 1,1, when
when aa carrycarry result
result from
from bitbit D3
D3 and
and
passes
passes toto bit
bit D4.
D4. TheThe P P flag
flag is
is set
set to
to 1,
1, when the result
when the result in in accumulator
accumulator contains
contains even
even number
number
of 1s.
of 1s.
Program Counter
Program Counter (PC)
(PC)

This 16-bit
This 16-bit register
register deals
deals with
with sequencing
sequencing the
the execution
execution ofof instructions.
instructions. This
This register
register is
is aa
memory pointer.
memory pointer. The
The microprocessor
microprocessor uses this register
uses this register to
to sequence
sequence the the execution
execution ofof the
the
instructions. The
instructions. The function
function ofof the
the program
program counter
counter is is to
to point
point toto the
the memory
memory address
address from
from
which the next
which the next byte
byte is
is to
to be
be fetched.
fetched. When
When aa byte
byte is
is being
being fetched,
fetched, the
the program counter is
program counter is
automatically incremented
automatically incremented by by one
one to
to point to the
point to the next
next memory
memory location.
location.

Stack Pointer
Stack Pointer (SP)
(SP)

The stack
The stack pointer is also
pointer is also aa 16-bit
16-bit register,
register, used
used as
as aa memory
memory pointer.
pointer. It
It points to aa memory
points to memory
location in
location in R/W
R/W memory,
memory, called
called stack.
stack. The
The beginning
beginning ofof the
the stack
stack is
is defined
defined byby loading
loading 16-
16-
bit address in
bit address in the
the stack
stack pointer.
pointer.

Instruction Register/Decoder
Instruction Register/Decoder

It is
It is an
an 8-bit
8-bit register
register that
that temporarily
temporarily stores
stores the
the current
current instruction
instruction ofof aa program.
program. Latest
Latest
instruction sent
instruction sent here
here from
from memory
memory prior to execution.
prior to execution. Decoder
Decoder then
then takes
takes instruction
instruction and
and
decodes or
decodes or interprets
interprets the
the instruction.
instruction. Decoded
Decoded instruction
instruction then
then passed to next
passed to next stage.
stage.

Control Unit
Control Unit

Generates signals
Generates signals on
on data
data bus,
bus, address
address bus
bus and
and control
control bus
bus within
within microprocessor
microprocessor toto carry
carry
out the
out the instruction,
instruction, which
which has
has been
been decoded.
decoded. Typical
Typical buses
buses and
and their
their timing
timing are
are described
described asas
follows:
follows:

e Data
Data Bus: Data bus
Bus: Data bus carries
carries data
data inin binary
binary formform between
between microprocessor
microprocessor and and other
other
external units
external such as
units such as memory.
memory. It It is
is used
used toto transmit
transmit data
data i.e.
i.e. information,
information, results
results ofof
arithmetic etc
arithmetic etc between
between memory
memory and and thethe microprocessor.
microprocessor. Data Data busbus isis bidirectional
bidirectional in in
8
nature. The
nature. The data
data bus
bus width
width ofof 8085
8085 microprocessor
microprocessor is is 8-bit
8-bit i.e.
i.e. 22° combination
combination of of
binary digits and
binary digits and are
are typically
typically identified
identified as as D0DO —– D7.
D7. Thus
Thus size size ofof the
the data
data bus
bus
determines what
determines what arithmetic
arithmetic can
can bebe done.
done. If If only
only 8-bit
8-bit wide
wide then
then largest
largest number
number is is
11111111 (255
11111111 (255 in in decimal).
decimal). Therefore,
Therefore, larger
larger numbers
numbers havehave to to bebe broken
broken down
down into
into
chunks of
chunks of 255.
255. This
This slows
slows microprocessor.
microprocessor.
eo Address
Address Bus: Bus: TheThe address
address bus bus carries
carries addresses
addresses and and is is oneone way
way bus bus from
from
microprocessor to
microprocessor to the
the memory
memory or or other
other devices.
devices. 80858085 microprocessor
microprocessor containcontain 16-bit
16-bit
address bus
address bus and
and are
are generally
generally identified
identified as as A0
AO -- A15.
A15. TheThe higher
higher order
order address
address lines
lines
(A8 —– A15)
(A8 A15) areare unidirectional
unidirectional and and thethe lower
lower order
order lines
lines (A0
(AO —– A7) A7) are
are multiplexed
multiplexed
(time-shared) with
(time-shared) with the
the eight
eight data
data bits
bits (D0
(DO —– D7)
D7) andand hence,
hence, they
they areare bidirectional.
bidirectional.
eo Control
(Control Bus: Control bus
Bus: Control are various
bus are various lineslines which
which havehave specific
specific functions
functions for for
coordinating and
coordinating and controlling
controlling microprocessor
microprocessor operations.
operations. The The control
control bus carries
bus carries
control signals
control signals partly unidirectional and
partly unidirectional and partly bidirectional. The
partly bidirectional. The following
following control
control
and status
and status signals
signals are
are used
used byby 8085
8085 processor:
processor:
I.
I. ALE (output): Address
ALE (output): Address LatchLatch Enable
Enable is is aa pulse
pulse that
that is is provided
provided whenwhen an an
address appears
address appears onon the
the AD0
ADO —– AD7 AD7 lines,
lines, after
after which
which it it becomes
becomes 0. 0.
 II.
II. RD (active
RD (active low
low output):
output): The
The Read
Read signal
signal indicates
indicates that
that data
data are
are being
being read
read
from the
from the selected
selected I/O
I/O or
or memory
memory device
device and
and that
that they
they are
are available
available on
on the
the
data bus.
data bus.
III.
III. WR (active low
WR (active low output):
output): The
The Write
Write signal
signal indicates
indicates that
that data
data on
on the
the data
data bus
bus
are to be written into a selected memory or I/O location.
are to be written into a selected memory or I/O location.
IV.
IV. IO/M
IO/ (output): It
M (output): It is
is aa signal
signal that
that distinguished
distinguished between
between aa memory
memory operation
operation
and an
and an I/O
I/O operation.
operation. When
When IO/
10/MM == 00 it
it is
is aa memory
memory operation
operation and
and IO/
10/MM =
=
11 it
it is
is an
an I/O
I/O operation.
operation.
V.
V. SI and
S1 and S0SO (output):
(output): These
These are
are status
status signals
signals used to specify
used to specify the
the type
type of
of
operation being
operation being performed; they are
performed; they are listed
listed in in Table
Table 1.
1.

Table 11 Status
Table Status signals
signals and
and associated
associated operations
operations

S1 S0 States
0 0 0 0 | Hat
Halt |
0 0 0 ov1 Wite
Write |
to 1 0 | Read
Read |
1 1 Fetch

The schematic
The schematic representation
representation of
of the
the 8085
8085 bus
bus structure
structure is
is as
as shown
shown in
in Fig.
Fig. 5.
5. The
The
microprocessor performs
microprocessor performs primarily four operations:
primarily four operations:

I.
I. Memory Read:
Memory Read: Reads
Reads data
data (or
(or instruction)
instruction) from
from memory.
memory.
II.
II. Memory Write:
Memory Write: Writes
Writes data
data (or
(or instruction)
instruction) into
into memory.
memory.
III.
III. I/O Read:
I/O Read: Accepts
Accepts data
data from
from input
input device.
device.
IV.
IV. I/O Write:
I/O Write: Sends
Sends data
data to
to output
output device.
device.

The 8085
The 8085 processor
processor performs these functions
performs these functions using
using address
address bus,
bus, data
data bus
bus and
and control
control bus
bus as
as
shown in
shown in Fig.
Fig. 5.
5.

) Ava
ho mt Address Bus

=) Real

" A
D, -—
3: 5A] A]
Dita Bus
Va -

I ER E—
— Control Bus

Fig. 55 The
Fig. The 8085
8085 bus structure
bus structure
3. 8085
3. 8085 PIN
PIN DESCRIPTION
DESCRIPTION

Properties:
Properties:

e [tisis aa 8-bit
It 8-bit microprocessor
microprocessor
e Manufactured with
Manufactured with N-MOS technology
N-MOS technology
e 40 pin
40 pin IC IC package
package
e It has
It has 16-bit
16-bit address
address bus
bus and
and thus
thus has
has 2
16
2'® == 64
64 KB
KB addressing
addressing capability.
capability.
e Operate with
Operate with 33 MHz
MHz single-phase
single-phase clock
clock
e +5 V
+5 V single
single power supply
power supply

The logic
The logic pin
pin layout
layout and
and signal
signal groups
groups ofof the
the 8085nmicroprocessor
808 Snmicroprocessor are
are shown
shown in
in Fig.
Fig. 6.
6. All
All
the signals
the signals are
are classified
classified into
into six
six groups:
groups:

e Address bus
Address bus
e Data bus
Data bus
e Control &
Control & status
status signals
signals
e Power supply
Power supply and
and frequency
frequency signals
signals
e Externally initiated
Externally initiated signals
signals
e Serial I/O
Serial I/O signals
signals

xX 1 40 Vee
x 3 3 HOLD DMA
RESE QUT 3 38 HLDA
Serial ip, o/p signals—| joy : . CLR(OD RESET IN
TRAP 6 33 READY =
RST 73 7 3 10/M
RST63
Ror: 8
«|. 8085A MJT Si
INTR . XD
— - 31 WR
Fo 12 0 AE
2 0
AD: 13 15 ESE
AD: 14 . Au
ADs 15 2% Ai
ADy 16 25 Ap
ADs 17 M4 Ap
AD; 18 23 Ap
AD, 19 2 A
Vis 20) 2 A

Fig. 66 8085
Fig. 8085 microprocessor
microprocessor pin
pin layout
layout and
and signal
signal groups
groups

Address and Data

Address and Data Buses:
Buses:

eo AS8— AlS5 (output,

A8 – A15 (output, 3-state):
3-state): Most
Most significant
significant eight
eight bits
bits of
of memory
memory addresses
addresses and
and the
the
eight bits
eight bits of
of the
the I/O
I/O addresses.
addresses. These
These lines
lines enter
enter into
into tri-state
tri-state high
high impedance
impedance state
state
during HOLD
during HOLD and and HALT
HALT modes.
modes.
eo ADO
AD0 —– AD7 (input/output, 3-state):
AD7 (input/output, 3-state): Lower
Lower significant
significant bits
bits of
of memory
memory addresses
addresses and
and
the eight
the eight bits
bits of
of the
the I/O
I/O addresses
addresses during
during first
first clock
clock cycle.
cycle. Behaves
Behaves as
as data
data bus
bus
 during third
during third and
and fourth
fourth clock
clock cycle.
cycle. These
These lines
lines enter
enter into
into tri-state
tri-state high
high impedance
impedance
state during
state during HOLD
HOLD and
and HALT
HALT modes.
modes.

Control &
Control & Status
Status Signals:
Signals:

eo ALE:
ALE: Address latch enable
Address latch enable
e RD: : Read
RD Read control
control signal.
signal.
e WR: Write control
WR : Write control signal.
signal.
e IO/M,
IO/ SI and
M , S1 and S0
SO : : Status
Status signals.
signals.

Power Supply
Power Supply &
& Clock
Clock Frequency:
Frequency:

eo Vcc: +5 V
Vcc: +5 V power
power supply
supply
e Vss: Ground reference
Vss: Ground reference
eo Xl, X2: A
X1, X2: A crystal
crystal having
having frequency
frequency of
of 6
6 MHz
MHz is
is connected
connected at
at these
these two
two pins
pins
oe CLK: Clock
CLK: Clock output
output

Externally Initiated
Externally Initiated and
and Interrupt
Interrupt Signals:
Signals:

eo RESET
RESET IN: : When
IN When the the signal
signal on on this
this pin
pin isis low,
low, the
the PC
PC is is set
set to
to 0,
0, the
the buses
buses areare tri-
tri-
stated and
stated and the
the processor
processor is is reset.
reset.
eo RESET OUT:
RESET OUT: This This signal
signal indicates
indicates thatthat the
the processor
processor is is being
being reset.
reset. The
The signal
signal can
can
be
be used to reset
used to reset other
other devices.
devices.
e READY: When
READY: When this this signal
signal is is low,
low, thethe processor waits for
processor waits for anan integral
integral number
number of of
clock cycles
clock cycles until
until itit goes
goes high.
high.
eo HOLD: This
HOLD: This signal
signal indicates
indicates that that aa peripheral
peripheral likelike DMA
DMA (direct
(direct memory
memory access)
access)
controller is
controller is requesting
requesting the the use
use ofof address
address and and data
data bus.
bus.
eo HLDA: This
HLDA: This signal
signal acknowledges
acknowledges the the HOLD
HOLD request.
request.
eo INTR: Interrupt
INTR: Interrupt request
request is is aa general-purpose
general-purpose interrupt.
interrupt.
eo INTA :: This
INTA This isis used
used toto acknowledge
acknowledge an an interrupt.
interrupt.
e RST 7.5,
RST 7.5, RST
RST 6.5, 6.5, RST
RST 5,5 5,5 —– restart
restart interrupt:
interrupt: These
These areare vectored
vectored interrupts
interrupts andand
have highest
have highest priority
priority than
than INTR
INTR interrupt.
interrupt.
eo TRAP: This
TRAP: This isis aa non-maskable
non-maskable interruptinterrupt andand has
has the
the highest
highest priority.
priority.

Serial I/O
Serial I/O Signals:
Signals:

e SID: Serial
SID: Serial input
input signal.
signal. Bit
Bit on
on this
this line
line isis loaded
loaded toto D7
D7 bit
bit of
of register
register AA using RIM
using RIM
instruction.
instruction.
e SOD: Serial
SOD: Serial output
output signal.
signal. Output
Output SOD
SOD is is set
set or
or reset
reset by
by using SIM instruction.
using SIM instruction.
[J
 4. INSTRUCTION
4. INSTRUCTION SET
SET AND
AND EXECUTION
EXECUTION IN
IN 8085
8085

Based on
Based on the
the design
design ofof the
the ALU and decoding
ALU and decoding unit, the microprocessor
unit, the microprocessor manufacturer
manufacturer
provides instruction set
provides instruction set for
for every
every microprocessor.
microprocessor. The
The instruction
instruction set
set consists
consists of
of both
both
machine code
machine code and
and mnemonics.
mnemonics.

An instruction is
An instruction is aa binary
binary pattern designed inside
pattern designed inside aa microprocessor
microprocessor toto perform
perform aa specific
specific
function. The
function. The entire
entire group
group ofof instructions
instructions that
that aa microprocessor
microprocessor supports
supports isis called
called
instruction set.
instruction set. Microprocessor
Microprocessor instructions
instructions can
can be
be classified
classified based
based on
on the
the parameters such
parameters such
functionality, length
functionality, length and
and operand
operand addressing.
addressing.

Classification based
Classification on functionality:
based on functionality:

I.
I. Data transfer
Data transfer operations:
operations: This This group
group of of instructions
instructions copies
copies data
data from
from source
source to to
destination. The
destination. The content
content of of the
the source
source is is not
not altered.
altered.
II.
II. Arithmetic operations: Instructions
Arithmetic operations: Instructions of of this
this group
group perform operations like
perform operations like addition,
addition,
subtraction, increment
subtraction, increment & & decrement.
decrement. One One of of the
the data
data used
used in in arithmetic
arithmetic operation
operation is is
stored in
stored in accumulator
accumulator and and thethe result
result is
is also
also stored
stored inin accumulator.
accumulator.
III.
III. Logical operations:
Logical operations: Logical
Logical operations
operations includeinclude AND, AND, OR, OR, EXOR,
EXOR, NOT. NOT. The The
operations like
operations like AND,
AND, OR OR and and EXOR
EXOR uses uses twotwo operands,
operands, one one is is stored
stored in in
accumulator and
accumulator and other
other can
can be be any
any register
register or or memory
memory location.
location. TheThe result
result isis stored
stored
in accumulator.
in accumulator. NOT operation requires
NOT operation requires single single operand,
operand, whichwhich is is stored
stored in in
accumulator.
accumulator.
IV.
IV. Branching operations:
Branching operations: Instructions
Instructions in in this
this group
group can can bebe used
used to to transfer
transfer program
program
sequence from
sequence from one one memory
memory location to
location to another
another either
either conditionally
conditionally or or
unconditionally.
unconditionally.
V.
V. Machine control
Machine control operations:
operations: Instruction
Instruction in in this
this group
group control
control execution
execution of of other
other
instructions and
instructions and control
control operations
operations likelike interrupt,
interrupt, halthalt etc.
etc.

Classification based
Classification on length:
based on length:

I.
I. One-byte instructions:
One-byte instructions: Instruction
Instruction having
having one
one byte
byte in
in machine
machine code.
code. Examples
Examples are
are
depicted in
depicted in Table
Table 2.
2.
I.
I. Two-byte instructions:
Two-byte instructions: Instruction
Instruction having
having two
two byte
byte in
in machine
machine code.
code. Examples
Examples are
are
depicted in
depicted in Table
Table 33
II.
II. Three-byte instructions:
Three-byte instructions: Instruction
Instruction having
having three
three byte
byte in
in machine
machine code.
code. Examples
Examples
are depicted
are depicted inin Table
Table 4.
4.

Table 2
Table 2 Examples
Examples of
of one
one byte instructions
byte instructions

Opcode Operand Machine code/Hex code

MOV A, B 78
ADD M 86
 Table 33 Examples
Table Examples of
of two
two byte
byte instructions
instructions
Machine code/Hex
Opcode
Machine code/Hex code
Operand code | Byte
Byte description
description
MVI A, 7FH
A,
3E 7FH First byte
7" 7F | Seccondbyte
Second byte
ADI 0FH C6 First byte
[oF 0F | Secondbyte
Second byte

Table 4
Table 4 Examples
Examples of
of three
three byte instructions
byte instructions
Opcode Operand Machine code/Hex
Machine code/Hex code
code | Byte
Byte description
description
JMP C3 9050H
9050H First byte
5 50 | Sccondbyte
Second byte |
9% 90 | Thidbyte
Third byte
LDA 8850H
8850H 3A First byte
50 50 | Sccondbyte
Second byte |
1 8 88 | Thidbyte
Third byte

Addressing Modes in
Addressing Modes in Instructions:
Instructions:

The process
The of specifying
process of specifying the
the data
data to
to be
be operated
operated on
on by the instruction
by the instruction is
is called
called addressing.
addressing.
The various
The various formats
formats for
for specifying
specifying operands
operands are
are called
called addressing
addressing modes.
modes. The
The 8085
8085 has
has the
the
following five
following five types
types of
of addressing:
addressing:

I.
I. Immediate addressing
Immediate addressing
II.
II. Memory direct
Memory direct addressing
addressing
III. ~~ Register
III. Register direct
direct addressing
addressing
IV.
IV. Indirect addressing
Indirect addressing
V.
V. Implicit addressing
Implicit addressing

Immediate Addressing:
Immediate Addressing:

In this
In this mode,
mode, thethe operand
operand given
given inin the
the instruction
instruction -- aa byte
byte or
or word
word —– transfers
transfers to
to the
the
destination register
destination register or
or memory
memory location.
location.

Ex: MVI
Ex: MVI A,
A, 9AH
9AH

e The operand
The operand is
is aa part of the
part of the instruction.
instruction.
e The operand
The operand is
is stored
stored in
in the
the register
register mentioned
mentioned in
in the
the instruction.
instruction.

Memory Direct
Memory Direct Addressing:
Addressing:

Memory direct
Memory direct addressing
addressing moves
moves aa byte
byte or
or word
word between
between aa memory
memory location
location and
and register.
register.
The memory
The memory location
location address
address is
is given
given in
in the
the instruction.
instruction.

Ex: LDA
Ex: LDA 850FH
850FH

This instruction
This instruction is
is used
used to
to load
load the
the content
content of
of memory
memory address
address 850FH
850FH in
in the
the accumulator.
accumulator.
Register Direct
Register Direct Addressing:
Addressing:

Register
Bl
Register dir ect addressing
direct i
addressing transfer copy of
transfer aa copy or word
byte or
of aa byte word from source register
from source to
register to
destination register.
destination register.

Ex: MOV
Ex: MOV B,
B, C
C
It copies
It copies the
the content
content of
of register
register C
C to
to register
register B.
B.

Indirect Addressing:
Indirect Addressing:
. .
Indirect i transfers
Indirect addressing
addressing transfers aa byte
byte or
or word between aa register
word between register and aa memory
and memory location.
location.

Ex: MOV
Ex: MOV A,
A, M
M
ere the
Here the data
data is
is in
in the
the memory
memory location
location pointed
pointed to
to by
by the
the contents
contents of
of HL
HL pair.
pair. The
The data
data is
is
moved to
moved to the
the accumulator.
accumulator.

Implicit Addressing
Implicit Addressing

In this
In this addressing
addressing mode
mode the
the data
data itself
itself specifies
specifies the
the data
data to
to be
be operated
operated upon.
upon.

Ex: CMA
Ex: CMA
: .
The instruction complements
The instruction the content
complements the of the
content of accumulator. No
the accumulator. No specific data or
specific data is
operand is
or operand
mentioned in
mentioned in the
the instruction.
instruction.

5. INSTRUCTION
5. INSTRUCTION SET
SET OF
OF 8085
8085

Data Transfer
Data Transfer Instructions:
Instructions:
Opcode Operand Description

Copy from source to destination of the source

This instruction copies the contents
MOV Rd, Rs of
M. Rs register into the destination register; the contents
the source register are not altered. If one of the operands is a
Rd. M by the contents of
memory location, its location is specified
the HL registers.
Example: MOV B,C or MOV B. M

Move immediate 8-bit register or

The &-bit data is stored in the destination
MMVI Rd. data its location is
memory. If the operand is a memory location.
MM, data of the HL registers.
specified by the contents
MVIB. 57 or MVI M, 57
Example:

Load accumulator by a
16-bit address The contents of a memory location. specified
LDA to the accumulator.
16-bit address in the operand. are copied
The contents of the source are not altered.
Example: LDA 2034 or LDA XYZ

Toad accumulator indirect point to a memory

LDAX B/D Reg. pair The contents of the designated register pair
that memory
location. This instruction copies the contents of
The contents of either the
location into the accumulator.
altered.
register pair or the memory location are not
Example: LDAX B

Load register pair immediate 16-bit data in the register pair

The instruction loads
LXI Reg. pair, 16-bit data
designated in the operand.
Example: LXI H. 2034

I.oad H and IL registers direct location

The instruction copies the contents of the memory
16-bit address
LHL
pointed out by the 16-bit address into register IL and copies
into register IH. The
the contents of the next memory location
of source memory locations are not altered.
contents
Example: LHLD 2040
Store accumulator direct
STA 16-bit address The contents of the accumulator are copied nto the memory
location specified by the operand. This is a 3-byte
struction, the second byte specifies the low-order address
and the third byte specifies the high-order address.
Example: STA 4350 or STA XYZ

Store accumulator indirect

STAX Reg. pair The contents of the accumulator are copied into the memory
location specified by the contents of the operand (register
pair). The contents of the accumulator are not altered.
Example: STAXB

Store H and L registers direct

SHLD 16-bit address The contents of register LL are stored into the memory location
specified by the 16-bit address in the operand and the contents
of H register are stored into the next memory location by
incrementing the operand. The contents of registers HL are
not altered. This is a 3-byte instruction, the second byte
specifies the low-order address and the third byte specifies the
high-order address.
Example: SHLD 2470

Exchange H and L with D and E

XCHG none The contents of register H are exchanged with the contents of
register D, and the contents of register LL are exchanged with
the contents of register E.
Example: XCHG

Copy H and L registers to the stack pointer

SPH. none The instruction loads the contents of the H and L registers
nto the stack pointer register, the contents of the H register
provide the high-order address and the contents of the L
register provide the low-order address. The contents of the H
and L registers are not altered.
Example: SPHL

Exchange H and L with top of stack

XTHL ~~ none The contents of the I. register are exchanged with the stack
location pointed out by the contents of the stack pointer
register. The contents of the H register are exchanged with
the next stack location (SP+1); however, the contents of the
stack pointer register are not altered.
Example: XTHL
 Push register pair onto stack
PUSH Reg. pair The contents of the register pair designated in the operand are
copied onto the stack in the following sequence. The stack
pointer register is decremented and the contents of the high-
order register (B, D, II, A) are copied into that location. The
stack pointer register is decremented again and the contents of
the low-order register (C., E., L, flags) are copied to that
location.
Example: PUSH B or PUSH A

Pop off stack to register pair

POP Reg. pair The contents of the memory location pointed out by the stack
pointer register are copied to the low-order register (C. E, L,
status flags) of the operand. The stack pointer is incremented
by 1 and the contents of that memory location are copied to
the high-order register (B, D, H, A) of the operand. The stack
pointer register is again incremented by 1.
Example: POP H or POP A

Output data from accumulator to a port with 8-bit address

our 8-bit port address The contents of the accumulator are copied into the I/O port
specified by the operand.
Example: OUT 87

Input data to accumulator from a port with 8-bit address

IN 8-bit port address The contents of the input port designated in the operand are
read and loaded into the accumulator.
Example: IN 82

Arithmetic Instructions:
Arithmetic Instructions:

Opcode Operand Description

Add register or memory to accumulator

ADD R The contents of the operand (register or memory) are
M added to the contents of the accumulator and the result is
stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL
registers. All flags are modified to reflect the result of the
addition.
Example: ADD B or ADD M

Add register to accumulator with carry

ADC R The contents of the operand (register or memory) and
M the Carry flag are added to the contents of the accumulator
and the result is stored in the accumulator. If the operand is a
memory location, its location is specified by the contents of
the HL registers. All flags are modified to reflect the result of
the addition.
Example: ADC B or ADC M

Add immediate to accumulator

ADI 8-bit data The 8-bit data (operand) is added to the contents of the
accumulator and the result is stored in the accumulator. All
flags are modified to reflect the result of the addition.
Example: ADI 45

Add immediate to accumulator with carry

ACI 8-bit data The 8-bit data (operand) and the Carry flag are added to the
contents of the accumulator and the result is stored in the
accumulator. All flags are modified to reflect the result of the
addition.
Example: ACI 45

Add register pair to H and L registers

DAD Reg. pair The 16-bit contents of the specified register pair are added to
the contents of the HL register and the sum is stored in the
HL register. The contents of the source register pair are not
altered. If the result is larger than 16 bits, the CY flag is set.
No other flags are affected.
Example: DAD H
Subtract register or memory from accumulator
SUB R The contents of the operand (register or memory ) are
M subtracted from the contents of the accumulator, and the
result 1s stored in the accumulator. If the operand is a
memory location, its location is specified by the contents of
the HL registers. All flags are modified to reflect the result of
the subtraction.
Example: SUBB or SUBM

Subtract source and borrow from accumulator

SBB R The contents of the operand (register or memory ) and
M the Borrow flag are subtracted from the contents of the
accumulator and the result 1s placed in the accumulator. If
the operand is a memory location, its location is specified by
the contents of the HL registers. All flags are modified to
reflect the result of the subtraction.
Example: SBB B or SBBM

Subtract immediate from accumulator

SUI 8-bit data The 8-bit data (operand) is subtracted from the contents of the
accumulator and the result 1s stored in the accumulator. All
flags are modified to reflect the result of the subtraction.
Example: SUI 45

Subtract immediate from accumulator with borrow

SBI 8-bit data The 8-bit data (operand) and the Borrow flag are subtracted
from the contents of the accumulator and the result 1s stored
in the accumulator. All flags are modified to reflect the result
of the subtracion.
Example: SBI 45

Increment register or memory by 1

INR R The contents of the designated register or memory) are
M incremented by 1 and the result 1s stored m the same place. If
the operand is a memory location, its location is specified by
the contents of the HL registers.
Example: INRB or INK M

Increment register pair by 1

INX R The contents of the designated register pair are incremented
by 1 and the result is stored in the same place.
Example: INX H
Decrement register or memory by 1
DCR R The contents of the designated register or memory are
M decremented by 1 and the result is stored in the same place. If
the operand is a memory location, its location is specified by
the contents of the HL registers.
Example: DCR B or DCR M

Decrement register pair by 1

DCX R The contents of the designated register pair are decremented
by 1 and the result is stored in the same place.
Example: DCX H

Decimal adjust accumulator

DAA none The contents of the accumulator are changed from a binary
value to two 4-bit binary coded decimal (BCD) digits. This is
the only instruction that uses the auxiliary flag to perform the
binary to BCD conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are altered to reflect
the results of the operation.

If the value of the low-order 4-bits in the accumulator is

greater than 9 or if AC flag is set, the instruction adds 6 to the
low-order four bits.

If the value of the high-order 4-bits in the accumulator is

greater than 9 or if the Carry flag is set, the instruction adds 6
to the high-order four bits.

Example: DAA

BRANCHING INSTRUCTIONS

Opcode Operand Description

Jump unconditionally
IMP 16-bit address The program sequence is transferred to the memory location
specified by the 16-bit address given in the operand.
Example: JMP 2034 or IMP XYZ

Jump conditionally

Operand: 16-bit address

The program sequence is transferred to the memory location

specified by the 16-bit address given in the operand based on
the specified flag of the PSW as described below.
Example: JZ 2034 or JZ XYZ

Opcode Description Flag Status

IC Jump on Carry CY=1
INC Jump on no Carry CY=0
IP Jump on positive S=0
IM Jump on minus S=1
17 Jump on zero Z=1
INZ Jump on no zero Z=0
IPE Jump on parity even P=1
JPO Jump on parity odd P=0
Unconditional subroutine call
CALL 16-bit address The program sequence is transferred to the memory location
specified by the 16-bit address given in the operand. Before
the transfer, the address of the next instruction after CALL
(the contents of the program counter) is pushed onto the stack.
Example: CALL 2034 or CALL XYZ

Call conditionally

Operand: 16-bit address

The program sequence is transferred to the memory location

specified by the 16-bit address given in the operand based on
the specified flag of the PSW as described below. Before the
transfer, the address of the next instruction after the call (the
contents of the program counter) is pushed onto the stack.
Example: CZ 2034 or CZXYZ

Opcode Description Flag Status

cC Call on Carry CY =1
CNC Call on no Carry CY=0
CP Call on positive S=0
CM Call on minus S=1
CcZ Call on zero Z=1
CNZ Call on no zero Z=0
CPE Call on parity even P=1
CPO Call on parity odd P=0

Return from subroutine unconditionally

RET none The program sequence is transferred from the subroutine to
the calling program. The two bytes from the top of the stack
are copied into the program counter, and program execution
begins at the new address.
Example: RET

Return from subroutine conditionally

Operand: none

The program sequence is transferred from the subroutine to

the calling program based on the specified flag of the PSW as
described below. The two bytes from the top of the stack are
copied into the program counter, and program execution
begins at the new address.
Example: RZ

Opcode Description Flag Status

RC Return on Carry CY =1
RNC Return on no Carry CY=0
RP Return on positive S=0
RM Return on minus S=1
RZ Return on zero Z=1
RNZ Return on no zero Z=0
RPE Return on parity even P=1
RPO Return on parity odd P=0
ILLoad program counter with HL. contents
PCHL none The contents of registers H and IL. are copied into the program
counter. The contents of H are placed as the high-order byte
and the contents of I. as the low-order byte.
Example: PCHL

Restart
RST 0-7 The RST instruction is equivalent to a l-byte call instruction
to one of eight memory locations depending upon the number.
The instructions are generally used in conjunction with
interrupts and inserted using external hardware. However
these can be used as software instructions in a program to
transfer program execution to one of the eight locations. The
addresses are:

Instruction Restart Address

RST O 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

The 8085 has four additional interrupts and these interrupts

generate RST instructions internally and thus do not require
any external hardware. These imstructions and their Restart
addresses are:

Interrupt Restart Address

TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

LOGICAL INSTRUCTIONS

Opcode Operand Description

Compare register or memory with accumulator

CMP R The contents of the operand (register or memory) are
M compared with the contents of the accumulator. Both
contents are preserved . The result of the comparison is
shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set, s=1
if (A) = (reg/mem): zero flag is set, s=0
if (A) => (reg/mem): carry and zero flags are reset, s=0
Example: CMP B or CMP M

Compare immediate with accumulator

CPI 8-bit data The second byte (8-bit data) is compared with the contents of
the accumulator. The values being compared remain
unchanged. The result of the comparison is shown by setting
the flags of the PSW as follows:
if (A) < data: carry flag is set, s=1
if (A) = data: zero flag is set, s=0
if (A) > data: carry and zero flags are reset, s=0
Example: CPI 89

Logical AND register or memory with accumulator

ANA R The contents of the accumulator are logically ANDed with
M the contents of the operand (register or memory), and the
result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANA B or ANA M

Logical AND immediate with accumulator

ANI 8-bit data The contents of the accumulator are logically ANDed with the
8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANI 86
Exclusive OR register or memory with accumulator
XRA R The contents of the accumulator are Exclusive ORed with
M the contents of the operand (register or memory), and the
result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRA Bor XRAM

Exclusive OR immediate with accumulator

XRI 8-bit data The contents of the accumulator are Exclusive ORed with the
8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRI 86

Logical OR register or memory with accumulaotr

ORA R The contents of the accumulator are logically ORed with
M the contents of the operand (register or memory), and the
result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents of
HL registers. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORA B or ORA M

Logical OR immediate with accumulator

ORI 8-bit data The contents of the accumulator are logically ORed with the
8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORI 86

Rotate accumulator left

RLC none Each binary bit of the accumulator is rotated left by one
position. Bit D7 1s placed in the position of Dg as well as in
the Carry flag. CY is modified according to bit D7. S, Z, P,
AC are not affected.
Example: RLC

Rotate accumulator right

RRC none Each binary bit of the accumulator is rotated right by one
position. Bit Dg 1s placed in the position of D7 as well as in
the Carry flag. CY is modified according to bit Dg. S, Z, P,
AC are not affected.
Example: RRC
Rotate accumulator left through carry
RAL none Each binary bit of the accumulator is rotated lett by one
position through the Carry flag. Bit D7 is placed in the Carry
flag, and the Carry flag is placed in the least significant
position DQ. CY is modified according to bit D7. S. Z, P, AC
are not affected.
Example: RAL

Rotate accumulator right through carry

RAR none Each binary bit of the accumulator is rotated right by one
position through the Carry flag. Bit Dg 1s placed in the Carry
flag, and the Carry flag is placed in the most significant
position D7. CY is modified according to bit Dg. S, Z, P, AC
are not affected.
Example: RAR

Complement accumulator
CMA none The contents of the accumulator are complemented. No flags
are affected.
Example: CMA

Complement carry
CMC none The Carry flag is complemented. No other flags are affected.
Example: CMC

Set Carry
STC none The Carry flag is set to 1. No other flags are affected.
Example: STC

CONTROL INSTRUCTIONS

Opcode Operand Description

No operation
NOP none No operation is performed. The instruction is fetched and
decoded. However no operation is executed.
Example: NOP

Halt and enter wait state

HLT none The CPU finishes executing the current instruction and halts
any further execution. An interrupt or reset is necessary to
exit from the halt state.
Example: HLT

Disable interrupts
DI none The interrupt enable flip-flop 1s reset and all the interrupts
except the TRAP are disabled. No flags are affected.
Example: DI

Enable interrupts
EI none The interrupt enable flip-flop is set and all interrupts are
enabled. No flags are affected. After a system reset or the
acknowledgement of an interrupt, the interrupt enable flip-
flop 1s reset, thus disabling the interrupts. This instruction is
necessary to reenable the interrupts (except TRAP).
Example: EI
Read interrupt mask
RIM none This 1s a multipurpose instruction used to read the status of
mterrupts 7.5, 6.5, 5.5 and read serial data input bit. The
struction loads eight bits in the accumulator with the
following interpretations.
Example: RIM

D; Dg Ds D. Di D, D Dy
[SD] 17 [16 [15 [IEJ75[65[55]
| Ll | (I —
Serial input R Interrupt
data bit masked if
bit = 1
Interrupts Interrupt enable
pending if flip-flop is set
bit = 1 if bit = 1

Set interrupt mask

SIM none This 1s a multipurpose instruction and used to implement the
8085 interrupts 7.5, 6.5, 5.5, and serial data output. The
instruction interprets the accumulator contents as follows.
Example: SIM

D, Db Ds D, Dy Db DD

I | |
[SOD | SDE [XXX | R7.5 [ MSE [M7.5 [M6.5 [M55 |
Lr 1
Serial output data Reset R7.5 Masks interrupts
if D, = 1 if bits= 1
Serial data enable Mask set
1 = Enable enable if
0 = Disable D;=1

— Serial Output Data: Bit D; of the accumulator is latched into the SOD output
71 SOD
line and made available to a serial peripheral if bit Dy = 1.
0 SDE — Serial Data Enable: If this bit = 1, it enables the serial output. To implement
serial output, this bit needs to be enabled.
0 XXX —Don't Care
OJ R7.5—Reset RST 7.5: If this bit = 1, RST 7.5 flip-flop is reset. This is an additional
control to reset RST 7.5.
[J MSE— Mask Sct Enable: If this bit is high, it enables the functions of bits Dy, Dy, Dy.
This is a master control over all the interrupt masking bits. If this bit is low, bits Dy,
D,, and D; do not have any effect on the masks.
0 M7.5—D, = 0, RST 7.5 is enabled.
= |, RST 7.5 is masked or disabled.
0 M6.5—D, = 0, RST 6.5 is enabled.
= I, RST 6.5 is masked or disabled.
0 M5.5—D, = 0,RSTS5.5 is enabled.
= |, RST 5.5 is masked or disabled.
6. INSTRUCTION
6. INSTRUCTION EXECUTION
EXECUTION AND TIMING DIAGRAM:
AND TIMING DIAGRAM:

Each instruction
Each instruction in
in 8085
8085 microprocessor
microprocessor consists
consists of of two
two part-
part- operation
operation code
code (opcode)
(opcode) and
and
operand. The
operand. The opcode
opcode is is aa command
command suchsuch as as ADD
ADD and and the
the operand
operand is
is an
an object
object to
to be
be
operated on,
operated on, such
such as
as aa byte
byte oror the
the content
content of
of aa register.
register.

Instruction Cycle:
Instruction Cycle: The
The time
time taken
taken byby the
the processor
processor toto complete
complete the
the execution
execution of
of an
an
instruction. An
instruction. An instruction
instruction cycle
cycle consists
consists of
of one
one to
to six
six machine
machine cycles.
cycles.

Machine Cycle:
Machine Cycle: The
The time
time required
required to
to complete
complete one
one operation;
operation; accessing
accessing either
either the
the memory
memory
or I/O
or I/O device.
device. A
A machine
machine cycle
cycle consists
consists of
of three
three to
to six
six T-states.
T-states.

T-State: Time
T-State: Time corresponding
corresponding toto one
one clock
clock period. It is
period. It is the
the basic unit to
basic unit to calculate
calculate execution
execution
of instructions
of instructions or
or programs
programs in
in aa processor.
processor.

To execute
To execute aa program,
program, 8085
8085 performs
performs various
various operations
operations as:
as:

e Opcode fetch
Opcode fetch
e Operand fetch
Operand fetch
eo Memory read/write
Memory read/write
e [/O read/write
I/O read/write

External communication
External communication functions
functions are:
are:

eo Memory read/write

Memory read/write
e [/O read/write
I/O read/write
e Interrupt request
Interrupt request acknowledge
acknowledge

Opcode Fetch
Opcode Fetch Machine
Machine Cycle:
Cycle:

It is
It is the
the first
first step
step in
in the
the execution
execution of
of any
any instruction.
instruction. The
The timing
timing diagram
diagram of
of this
this cycle
cycle is
is
given in
given in Fig.
Fig. 7.
7.

The following
The following points
points explain
explain the
the various
various operations
operations that
that take
take place and the
place and the signals
signals that
that are
are
changed during
changed during the
the execution
execution of
of opcode
opcode fetch
fetch machine
machine cycle:
cycle:

T1 clock
T1 clock cycle
cycle

i.
i. The content
The content of
of PC
PC is
is placed
placed in
in the
the address
address bus;
bus; ADO
AD0 -- AD7
AD7 lines
lines contains
contains lower
lower bit
bit
address and
address and A8
A8 —– A15
A15 contains
contains higher
higher bit
bit address.
address.
ii.
ii. IO/Msignal
IO/ M signal isis low
low indicating
indicating that
that aa memory
memory location
location is
is being
being accessed.
accessed. S1 S1 and
and S0
SO
also changed
also changed to to the
the levels
levels as
as indicated
indicated in
in Table
Table 1.
1.
iii.
iii. ALE
ALE isis high,
high, indicates
indicates that
that multiplexed
multiplexed AD0ADO —– AD7
AD7 act
act as
as lower
lower order
order bus.
bus.

T2 clock
T2 clock cycle
cycle

i.
i. Multiplexed address
Multiplexed address bus is now
bus is now changed
changed toto data
data bus.
bus.
ii.
ii. The RD
The RD signal
signal is
is made
made low
low byby the
the processor. This signal
processor. This signal makes
makes the
the memory
memory device
device
load the
load the data
data bus
bus with
with the
the contents
contents of
of the
the location
location addressed
addressed byby the
the processor.
processor.
T3 clock
T3 clock cycle
cycle

i.
i. The opcode
The opcode available
available on on the
the data
data bus
bus is
is read
read by the processor
by the and moved
processor and moved to
to the
the
instruction register.
instruction register.
ii.
ii. The RD
The RD signal
signal isis deactivated
deactivated by
by making
making itit logic
logic 1.
1.

T4 clock
T4 clock cycle
cycle

i.
i. The processor
The decode the
processor decode the instruction
instruction in
in the
the instruction
instruction register
register and
and generate
generate the
the
necessary control
necessary control signals
signals toto execute
execute the
the instruction.
instruction. Based
Based on
on the
the instruction
instruction further
further
operations such
operations such as
as fetching,
fetching, writing
writing into
into memory
memory etc etc takes
takes place.
place.

|
fo m— i

N NN
was RO pig an
0X omyaina] KO)
ALE \
|

RO
A .
A ot ds “i

IE ERT IERE
2 Bor UME

Fig. 77 Timing
Fig. Timing diagram
diagram for
for opcode
opcode fetch
fetch cycle
cycle

Memory Read
Memory Read Machine
Machine Cycle:
Cycle:

The memory
The memory read cycle is
read cycle is executed
executed by
by the
the processor
processor toto read
read aa data
data byte
byte from
from memory.
memory. The
The
machine cycle
machine cycle is
is exactly
exactly same
same to
to opcode
opcode fetch
fetch except:
except: a)
a) It
It has
has three
three T-states
T-states b) The S0
b) The SO
signal is
signal is set
set to
to 0.
0. The
The timing
timing diagram
diagram of
of this
this cycle
cycle is
is given
given in
in Fig.
Fig. 8.8.
 | CLOCK \_ _
|

Lower-order

PhS nw
RD VARY

Fig. 88 Timing
Fig. Timing diagram
diagram for
for memory
memory read
read machine
machine cycle
cycle

Memory Write
Memory Write Machine
Machine Cycle:
Cycle:

The memory
The memory write cycle is
write cycle is executed
executed by
by the
the processor to write
processor to write aa data
data byte
byte in
in aa memory
memory
location. The
location. The processor
processor takes
takes three
three T-states
T-states and
and WR signal is
WR signal is made
made low.
low. The
The timing
timing
diagram of
diagram of this
this cycle
cycle is
is given
given in
in Fig.
Fig. 9.
9.

I/O Read
I/O Read Cycle:
Cycle:

The I/O
The I/O read
read cycle
cycle isis executed
executed by
by the
the processor
processor toto read
read aa data
data byte
byte from
from I/OI/O port or from
port or from
peripheral, which is
peripheral, which is I/O
I/O mapped
mapped in in the
the system.
system. The
The 8-bit
8-bit port address is
port address is placed
placed both
both inin the
the
lower and
lower and higher
higher order
order address
address bus.
bus. The
The processor takes three
processor takes three T-states
T-states to to execute
execute this
this
machine cycle.
machine cycle. The
The timing
timing diagram
diagram of of this
this cycle
cycle is
is given
given in in Fig.
Fig. 10.
10.
 aaa
sion no 2 AR

SD a
oe —
NL]
ET GE N.C WN CE
h ~ -

WR
HA EN I pA
Fig. 9
Fig. 9 Timing
Timing diagram
diagram for
for memory
memory write
write machine
machine cycle
cycle

aa
IE ER

GL
wor —
CN]
PET CR 0 NN CL
. ~ .

— J
Fig. 10
Fig. 10 Timing
Timing diagram
diagram I/O
I/O read
read machine
machine cycle
cycle
I/O Write
I/O Write Cycle:
Cycle:

The I/O
The I/O write
write cycle
cycle is is executed
executed by
by the
the processor
processor toto write
write aa data
data byte
byte toto I/O
I/O port or to
port or to aa
peripheral, which is
peripheral, which is I/O
I/O mapped
mapped inin the
the system.
system. The
The processor
processor takes
takes three
three T-states
T-states to
to execute
execute
this machine
this machine cycle.
cycle. The
The timing
timing diagram
diagram ofof this
this cycle
cycle is
is given
given in
in Fig.
Fig. 11.
11.

B To T3
: SIGNAL ™ | T2
— |
| |

SD CR

) ~ N

osteo Met fstmost

[| |

Fig. 11
Fig. 11 Timing
Timing diagram
diagram I/O
I/O write
write machine
machine cycle
cycle

Ex: Timing
Ex: Timing diagram
diagram for
for IN
IN 80H.
80H.

The instruction
The instruction and
and the
the corresponding
corresponding codes
codes and
and memory
memory locations
locations are
are given
given in
in Table
Table 5.
5.

Table 55 IN
Table IN instruction
instruction

Address Mnemonics
Opcode
800F
800F INSOH
| DB
IN 80H
DB |
sooo
8010 [|8080 |

i.
i. During the
During the first
first machine
machine cycle,
cycle, the
the opcode
opcode DBDB isis fetched
fetched from
from the
the memory,
memory, placed
placed
in the
in the instruction
instruction register
register and
and decoded.
decoded.
ii. ~~ During
ii. During second
second machine
machine cycle,
cycle, the
the port address 80H
port address 80H is is read
read from
from the
the next
next memory
memory
location.
location.
iii.
iii. During the
During the third
third machine
machine cycle,
cycle, the
the address
address 80H
80H is is placed
placed inin the
the address
address bus and the
bus and the
data read
data read from
from that
that port address is
port address is placed in the
placed in the accumulator.
accumulator.

The timing
The timing diagram
diagram is
is shown
shown in
in Fig.
Fig. 12.
12.
 Docone tect Merrory read vO read

ixo -elfet lvl= = {oh=)

-— pe pe]
TTT Ts 4 TS TE TT TB TS TIO
CuK : . : :

| t
Lo

sae DCJae] hf Jew] I Tw]

nL ALR
i TH
omsost [Xf fon] JX oot] JY [re] |

Fig. 12
Fig. 12 Timing
Timing diagram
diagram for
for the
the IN
IN instruction
instruction

7. 8085
7. 8085 INTERRUPTS
INTERRUPTS

Interrupt Structure:
Interrupt Structure:

Interrupt is
Interrupt is the
the mechanism
mechanism by by which
which the
the processor
processor is
is made
made toto transfer
transfer control
control from
from its
its
current program
current execution to
program execution to another
another program having higher
program having higher priority. The interrupt
priority. The interrupt signal
signal
may be
may be given
given to
to the
the processor
processor by any external
by any external peripheral device.
peripheral device.

The program
The program or or the
the routine
routine that
that is
is executed
executed upon interrupt is
upon interrupt is called
called interrupt
interrupt service
service routine
routine
(ISR). After
(ISR). After execution
execution ofof ISR,
ISR, the
the processor must return
processor must return to
to the
the interrupted
interrupted program. Key
program. Key
features in
features in the
the interrupt
interrupt structure
structure ofof any
any microprocessor
microprocessor are
are as
as follows:
follows:

i.i. Number
Number andand types
types of of interrupt
interrupt signals
signals available.
available.
ii. ~~ The
ii. The address
address ofof the
the memory
memory where
where thethe ISR
ISR is
is located
located for
for aa particular interrupt signal.
particular interrupt signal.
This address
This address isis called
called interrupt
interrupt vector
vector address
address (IVA).
(IVA).
iii.
iii. Masking and
Masking and unmasking
unmasking feature
feature ofof the
the interrupt
interrupt signals.
signals.
iv.
iv. Priority among
Priority among the the interrupts.
interrupts.
v. Timing of
v. Timing of the
the interrupt
interrupt signals.
signals.
vi.
vi. Handling and
Handling and storing
storing of of information
information aboutabout thethe interrupt
interrupt program (status
program (status
information).
information).

Types of
Types of Interrupts:
Interrupts:

Interrupts are
Interrupts are classified
classified based
based on
on their
their maskability,
maskability, IVA
IVA and
and source.
source. They
They are
are classified
classified as:
as:
 i.
i. Vectored and Non-Vectored
Vectored and Interrupts
Non-Vectored Interrupts
e Vectored interrupts require
Vectored interrupts require the
the IVA
IVA to
to be
be supplied
supplied by
by the
the external
external device
device that
that
gives the
gives the interrupt
interrupt signal.
signal. This
This technique
technique isis vectoring,
vectoring, isis implemented
implemented in in
number of
number of ways.
ways.
oeNon-vectored interrupts have
Non-vectored interrupts have fixed
fixed IVA
IVA for
for ISRs
ISRs of
of different
different interrupt
interrupt
signals.
signals.
ii. ~~ Maskable
ii. Maskable and
and Non-Maskable Interrupts
Non-Maskable Interrupts
e Maskable interrupts
Maskable interrupts areare interrupts
interrupts that
that can
can bebe blocked.
blocked. Masking
Masking cancan be
be done
done
by software or
by software or hardware
hardware means.
means.
eo Non-maskable interrupts are
Non-maskable interrupts are interrupts
interrupts that
that are
are always
always recognized;
recognized; the the
corresponding ISRs
corresponding ISRs are
are executed.
executed.
iii.
iii. Software and
Software and Hardware
Hardware Interrupts
Interrupts
e Software
Software interrupts
interrupts are are special
special instructions,
instructions, after
after execution
execution transfer
transfer the
the
control to
control to predefined
predefined ISR.ISR.
eo Hardware
Hardware interrupts
interrupts are
are signals
signals given
given to
to the
the processor,
processor, for
for recognition
recognition asas an
an
interrupt and
interrupt and execution
execution of of the
the corresponding
corresponding ISR. ISR.

Interrupt Handling
Interrupt Handling Procedure:
Procedure:

The following
The following sequence
sequence of
of operations
operations takes
takes place
place when
when an
an interrupt
interrupt signal
signal is
is recognized:
recognized:

i.
i. Save the
Save the PCPC content
content and
and information
information about
about current
current state
state (flags,
(flags, registers
registers etc)
etc) in
in the
the
stack.
stack.
ii.
ii. Load PC
Load PC with
with the
the beginning
beginning address
address of
of an
an ISR
ISR and
and start
start to
to execute
execute it.
it.
iit.
iii. Finish ISR
Finish ISR when
when the
the return
return instruction
instruction is
is executed.
executed.
iv.
iv. Return to
Return to the
the point in the
point in the interrupted
interrupted program
program where execution was
where execution was interrupted.
interrupted.

Interrupt Sources
Interrupt Sources and
and Vector
Vector Addresses
Addresses in
in 8085:
8085:

Software Interrupts:
Software Interrupts:

8085 instruction
8085 instruction set
set includes
includes eight
eight software
software interrupt
interrupt instructions
instructions called
called Restart
Restart (RST)
(RST)
instructions. These
instructions. These are
are one
one byte
byte instructions
instructions that
that make
make the
the processor
processor execute
execute aa subroutine
subroutine at
at
predefined locations. Instructions
predefined locations. Instructions and
and their
their vector
vector addresses
addresses are
are given
given in
in Table
Table 6.
6.

Table 6
Table 6 Software
Software interrupts
interrupts and
and their
their vector
vector addresses
addresses

Instruction Machine hex code Interrupt Vector Address

RST 0 C7 0000H
RST 1 CF 0008H
RST 2 D7 0010H
RST 3 DF 0018H
RST 4 E7 0020H
RST 5 EF 0028H
RST 6 F7 0030H
RST 7 FF 0032H
The software
The software interrupts
interrupts can
can be
be treated
treated as
as CALL
CALL instructions
instructions with
with default
default call
call locations.
locations. The
The
concept of
concept of priority
priority does
does not
not apply
apply toto software
software interrupts
interrupts as
as they
they are
are inserted
inserted into
into the
the
program
program as as instructions
instructions byby thethe programmer
programmer and and executed
executed by by the
the processor when the
processor when the
respective program lines
respective program lines are
are read.
read.

Hardware Interrupts
Hardware Interrupts and
and Priorities:
Priorities:

8085 have
8085 have five
five hardware interrupts —– INTR,
hardware interrupts INTR, RST
RST 5.5,
5.5, RST
RST 6.5,
6.5, RST
RST 7.5
7.5 and
and TRAP.
TRAP. Their
Their
IVA and
IVA and priorities are given
priorities are given in
in Table
Table 7.
7.

Table 7
Table 7 Hardware
Hardware interrupts
interrupts of
of 8085
8085

Interrupt
Interrupt Interrupt vector
Interrupt vector Maskable or
Maskable or non-
non- Edge or
Edge or level
level | priority
priority
address
address maskable
maskable triggered
triggered
TRAP 0024H
0024H Non-makable
Non-makable Level 1
RST 7.5
RST 7.5 003CH
003CH Maskable
Maskable Rising edge
Rising edge 2
RST 6.5
RST 6.5 0034H
0034H Maskable
Maskable Level 3
RST 5.5
RST 5.5 002CH
002CH Maskable
Maskable Level 4
INTR Decided by
Decided by hardware
hardware Maskable
Maskable Level 5

Masking of
Masking of Interrupts:
Interrupts:

Masking can
Masking can be
be done
done for
for four
four hardware
hardware interrupts
interrupts INTR,
INTR, RST
RST 5.5,
5.5, RST
RST 6.5,
6.5, and
and RST
RST 7.5.
7.5.
The masking
The masking of
of 8085
8085 interrupts
interrupts is
is done
done at
at different
different levels.
levels. Fig.
Fig. 13
13 shows
shows the
the organization
organization of
of
hardware interrupts
hardware interrupts in
in the
the 8085.
8085.

Interrupt vector addresses

cow poo. 0024

Fip-flop
EB 9) 003C
wos]
2D _
=.
4)

Cow] 1)

a
©
ot

Fig. 13
Fig. 13 Interrupt
Interrupt structure
structure of
of 8085
8085

The Fig.
The Fig. 13
13 is
is explained
explained by
by the
the following
following five
five points:
points:
 i.
i. The maskable
The maskable interrupts
interrupts are
are by
by default
default masked
masked by by the
the Reset
Reset signal.
signal. So
So no
no interrupt
interrupt is
is
recognized
recognized by by the
the hardware
hardware reset.
reset.
ii. ~~ The
ii. The interrupts
interrupts can
can be
be enabled
enabled by by the
the EI
EI instruction.
instruction.
iii. ~~ The
iii. The three
three RST
RST interrupts
interrupts can
can be selectively masked
be selectively masked by by loading
loading the
the appropriate
appropriate word
word
in the
in the accumulator
accumulator and and executing
executing SIM SIM instruction.
instruction. This
This isis called
called software
software masking.
masking.
iv.
iv. All maskable interrupts
All maskable interrupts are
are disabled
disabled whenever
whenever an an interrupt
interrupt isis recognized.
recognized.
v.
v. All maskable interrupts
All maskable interrupts can
can be
be disabled
disabled by executing the
by executing the DI
DI instruction.
instruction.

RST 7.5
RST 7.5 alone
alone has
has aa flip-flop
flip-flop to
to recognize
recognize edge
edge transition.
transition. The
The DI
DI instruction
instruction reset
reset interrupt
interrupt
enable flip-flop
enable flip-flop in
in the
the processor and the
processor and the interrupts
interrupts are
are disabled.
disabled. To
To enable
enable interrupts,
interrupts, EI
EI
instruction has
instruction has to
to be
be executed.
executed.

SIM Instruction:
SIM Instruction:

The SIM
The SIM instruction
instruction isis used
used toto mask
mask oror unmask
unmask RSTRST hardware
hardware interrupts.
interrupts. When
When executed,
executed,
the SIM
the SIM instruction
instruction reads
reads thethe content
content ofof accumulator
accumulator andand accordingly
accordingly mask
mask oror unmask the
unmask the
interrupts. The
interrupts. The format
format ofof control
control word
word to
to be
be stored
stored in
in the
the accumulator
accumulator before
before executing
executing SIM
SIM
instruction is
instruction is as
as shown
shown in in Fig.
Fig. 14.
14.

Bit position D7 D6 D§ D4 D3 D2 1] Do
Name SOD SDE X R75 MSE M75 M65 MSS
Explanation Serial Serial Not Reset Mask set Setto Setto Setto
data data used RST7.5 enable— 1to lto 1to
tobe enable— flip-flop Settol mask mask mask
sent set to tomask RST RST RST
1 for interrupts 7.5 6.5 55
sending

Fig. 14
Fig. 14 Accumulator
Accumulator bit
bit pattern for SIM
pattern for SIM instruction
instruction

In addition
In addition to to masking
masking interrupts,
interrupts, SIM
SIM instruction
instruction can
can be
be used to send
used to send serial
serial data
data on
on the
the
SOD line
SOD line of
of the
the processor. The data
processor. The data to
to be
be send
send is
is placed
placed inin the
the MSB
MSB bit
bit of
of the
the accumulator
accumulator
and the
and the serial
serial data
data output
output is
is enabled
enabled by
by making
making D6D6 bit
bit to
to 1.
1.

RIM Instruction:
RIM Instruction:

RIM instruction
RIM instruction isis used
used to
to read
read the
the status
status of
of the
the interrupt
interrupt mask
mask bits.
bits. When
When RIMRIM instruction
instruction
is executed,
is executed, the
the accumulator
accumulator is is loaded
loaded with
with the
the current
current status
status of
of the
the interrupt
interrupt masks
masks and
and the
the
pending interrupts. The
pending interrupts. The format
format and
and the
the meaning
meaning of of the
the data
data stored
stored inin the
the accumulator
accumulator after
after
execution of
execution of RIM
RIM instruction
instruction is
is shown
shown in in Fig.
Fig. 15.
15.

In addition
In addition RIM
RIM instruction
instruction is
is also
also used
used toto read
read the
the serial
serial data
data on
on the
the SID
SID pin
pin of
of the
the
processor. The data
processor. The data onon the
the SID
SID pin is stored
pin is stored in
in the
the MSB
MSB of of the
the accumulator
accumulator after
after the
the
execution of
execution of the
the RIM
RIM instruction.
instruction.
 ee
Bit D7 Dé D5 D4 D3 D2 D1 Do
osith

Name SID 175 16.5 [5.5 IE M7.5 M65 M55

Explanation Serial Settol Settol Settol Setto Setto I Set 1 Setto 1

if RST ifRST ifRST 1 if if RST if RST if RST
input
data 75is 65is 5.5is interrupts 7.5is 65is 5.5is
inthe pending pending pending are masked masked masked

SID enabled
pin [

Fig. 15
Fig. bit pattern
Accumulator bit
15 Accumulator pattern after of RIM
execution of
after execution instruction
RIM instruction

Ex: Write an
Ex: Write language program
assembly language
an assembly to enables
program to enables all interrupts in
the interrupts
all the 8085 after
in 8085 reset.
after reset.

EI
EI :: Enable interrupts
Enable interrupts

MVI A,
MVI 08H :: Unmask
A, 08H Unmask the interrupts
the interrupts

SIM
SIM :: Set mask and
the mask
Set the using SIM
unmask using
and unmask instruction
SIM instruction

Timing of
Timing Interrupts:
of Interrupts:

The interrupts
The are sensed
interrupts are sensed byby the processor one
the processor cycle before
one cycle end of
the end
before the execution of
of execution each
of each
instruction. An
instruction. interrupts signal
An interrupts must be
signal must applied long
be applied enough for
long enough it to
for it recognized. The
be recognized.
to be The
longest instruction
longest instruction of 8085 takes
the 8085
of the takes 1818 clock periods. So,
clock periods. So, the interrupt signal
the interrupt must be
signal must be
applied for
applied least 17.5
at least
for at clock periods.
17.5 clock periods. This decides the
This decides minimum pulse
the minimum width for
pulse width the
for the
signal.
interrupt signal.
interrupt

The maximum
The maximum pulse for the
width for
pulse width interrupt signal
the interrupt decided by
is decided
signal is condition that
the condition
by the the
that the
signal must
interrupt signal
interrupt not be
must not recognized once
be recognized This is
again. This
once again. the control
under the
is under the
of the
control of
programmer.
programmer.
QUESTIONS:
QUESTIONS:

1.
1. What is
What is the
the function
function of of aa microprocessor
microprocessor in in aa system?
system?
2.
2. Why is
Why is the
the data
data bus bus in in 8085
8085 bidirectional?
bidirectional?
3.
3. How
How does
does microprocessor
microprocessor differentiatedifferentiate between
between data data andand instruction?
instruction?
4.
4. How long
How long would
would the the processor
processor take take to to execute
execute the the instruction
instruction LDA LDA
1753H if
1753H if the
the T-state
T-state duration
duration is is 2μs?
2ps?
5.
5S. Draw
Draw thethe timing
timing diagram
diagram of of the
the instruction
instruction LDAX LDAX B. B.
6.
6. Sketch
Sketch and and explain
explain the the various
various pins pins of of the
the 8085.
8085.
7.
7. Explain
Explain direct
direct addressing
addressing mode mode of of 8085
8085 withwith anan example?
example?
8.
8. Draw
Draw andand explain
explain the the timing
timing diagram
diagram of of the
the instruction
instruction IN IN 82H.
82H.
9. What is
9. What is meant
meant by by ‘priority
‘priority of of the
the interrupts’?
interrupts? ExplainExplain the the operation
operation of of
the
the interrupts
interrupts structure
structure of of the
the 8085,
8085, withwith thethe help
help ofof aa circuit
circuit diagram.
diagram.
10. Explain the
10.Explain the bit
bit pattern
pattern for for SIMSIM instruction.
instruction. Write Write the
the assembly
assembly language
language
program
program lines lines to to enable
enable all all the
the interrupts
interrupts in in the
the 8085
8085 after
after reset.
reset.
11. Write
11. Write the
the logical
logical instructions
instructions which affect and
which affect and which
which does does not not affect
affect
flags
flags in
in 8085.
8085.
12. Write an
12.Write an ALPALP in in 8085
8085 MPU MPU to to reject
reject allall the
the negative
negative readings
readings and and addadd all
all
the
the positive
positive readingreading from from a a setset of of ten
ten reading
reading stored
stored in in memory
memory
locations starting at XX60H. When the sum
locations starting at XX60H. When the sum exceeds eight bits produce exceeds eight bits produce
output
output FFH FFH to to PORT1
PORT1 to to indicate
indicate overload
overload otherwise
otherwise display
display thethe sum.
sum.
13.
13. Write
Write anan ALPALP in in 8085
8085 to to eliminate
eliminate the the blanks
blanks (bytes
(bytes withwith zero value)
zero value)
from
from a a string
string of of eight
eight data
data bytes.
bytes. Use Use two
two memory
memory pointers:
pointers: one one to to get
get aa
byte
byte and
and the the other
other to to store
store the the byte.
byte.
14. Design an
14.Design an up-down
up-down counter counter to to count
count from from 0 O to to 9 9 and
and 9 9 to to 0 O
continuously
continuously with with a a 1.5
1.5 second
second delay delay between
between each each count,
count, andand display
display
the count at one of the
the count at one of the output ports. output ports.