Implementation of Advanced pipelined
RISC processor
1. Objective
The goal of this project is to design and implement a 5-stage
pipelined RISC-V processor with support for data forwarding,
hazard detection, and control hazard handling. The processor
supports standard RV32I instructions and handles common hazards
in pipelined architectures.
2. Pipeline Stages
IF (Instruction Fetch):
1. Fetches instruction from instruction memory.
2. Increments the Program Counter (PC).
ID (Instruction Decode):
1. Decodes the instruction.
2. Reads registers.
3. Generates immediate values and control signals.
EX (Execute):
1. Performs arithmetic/logic operations using the ALU.
2. Calculates memory addresses and branch targets.
MEM (Memory Access):
1. Accesses data memory for lw and sw instructions.
WB (Write Back):
1. Writes results back to the register file.
3. Hazard Types and Solutions
3.1 Data Hazards
Occur when an instruction depends on the result of a
previous instruction still in the pipeline.
Solution: A Forwarding Unit checks dependencies and
forwards values from EX/MEM or MEM/WB stages to the
EX stage.
Example:
add x1, x2, x3
sub x4, x1, x5
3.2 Load-Use Hazards
A specific case of data hazard where a lw instruction is
followed by an instruction that uses the loaded value.
Solution: A Hazard Detection Unit stalls the pipeline and
inserts a NOP to allow the load to complete.
Example:
lw x1, 0(x2)
add x3, x1, x4
3.3 Control Hazards
Caused by branch and jump instructions where the next
instruction depends on the outcome.
Solution: Resolve the branch in the ID stage. If
taken, flush the following fetched instruction.
Example:
beq x1, x2, label
add x3, x4, x5 // might be flushed
4. Modules Implemented
top.v: Top-level design connecting all components.
hazard_detection_unit.v: Detects load-use hazards and stalls
pipeline.
forwarding_unit.v: Handles data forwarding.
control_unit.v: Generates control signals.
alu_control.v, alu.v: Perform and decode ALU operations.
register_file.v: Stores and accesses registers.
instruction_memory.v: Stores instruction code.
data_memory.v: Handles data load/store.
imm_generator.v: Generates immediate values.
Pipeline registers: IF_ID.v, ID_EX.v, EX_MEM.v, MEM_WB.v.
pc.v: Program Counter logic.
testbench.v: Used for simulation and debugging.
5. Simulation,Testing and Observations:
Test cases were written to verify all hazards:
Control Hazard:
beq x1, x2, label
add x3, x4, x5 // flushed if branch taken
Data Hazard:
add x1, x2, x3
sub x4, x1, x5
Combined Load-Use + Control Hazard:
lw x1, 0(x2)
beq x1, x3, label
add x4, x5, x6 // may be flushed and stalled
6. Conclusion
This project successfully demonstrates an advanced pipelined
RISC-V processor with proper hazard management. The integration
of forwarding and stalling ensures correct execution without
unnecessary delays. The design can be further extended with
features like branch prediction and support for more complex
instructions like MUL/DIV.
End of the Report
