Stanford University

Let’s Start with the MOS Capacitor

Gate electrode
Silicon
(metal or polysilicon)
dioxide

tox

Silicon substrate

2-8 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Metal-Oxide-Semiconductor ((MOS))
Gate electrode
Silicon
(metal or polysilicon)
dioxide

tox

Silicon substrate

Vacuum Vacuum
level level
0.95 eV
High-k: Ec
qm = 4.10 eV q = 4.05 eV
Eg and barrier
q s
h i ht are diff
height differentt
from SiO2 Ec
E
f Eg 
8-9 eV q Ei
Metal B 1.12 eV
E
Ev f
(aluminum) Alternative channel
Silicon materials:
(p-type)
Eg, barrier height, and
dielectric constant
Ev Eg
Silicon
s     B
are different from Si
2q
dioxide

2-9 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Accumulation, Depletion, Inversion

p-type
p type n-type

flatband
Assume m=s: (a)
Ef
Vg = 0
_ _
Ec
Ef
Ef
Vg = 0
_ _ _ _ _ _ Ec
Ef
(e)

+ + + + + + Ev + + Ev

Vg < 0
accumulation _
___
Ef _ _ ______ _ _ _ _ _
(b) Ec Vg > 0 Ec (f)
Ef
Ef
++ Ef Ev
++ + + + + + Ev + +
++++ +

depletion Ef
Vg < 0
_ _ _ _ _ _ _
(c) Ec Ec (g)
Vg > 0 Ef
Ef
+ + + + + Ev + + Ev
Ef

Vg < 0
Ef
__ inversion
_ _ _ _ _ _
______ _ _ _
((d)) __
Ec Ec ((h))
Vg > 0 Ef
Ef ++
+ + + + Ev ++++++ + + + Ev
++
Ef

2-10 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Poisson’s
Poisson s Equation
Silicon
surface
d 2
dx 2

dE
dx

q
 sii
  
p ( x )  n( x )  N d ( x )  N a ( x) 
( Ei  E f ) / kT
Ec p( x)  ni e  ni e q ( B  ) / kT  p0e  q / kT
Eg
q ( x )
q s q E
i n( x)  ni e
( E f  Ei ) / kT
 ni e q (  B ) / kT  n0 e q / kT
B E
(> 0) f
Ev charge neutrality : (assuming uniform doping)

p(  0)  n(  0)  N d
 
 Na  0 
Oxide p-type silicon  
N d  N a   p (  0)  n(  0)

d 2
x
dx 2

q
 si
 
p0 e  q / kT  1  n0 e q / kT  1   
p (x) n(x) 
For Na doped N d  N a
substrate
d 2 q  
2
( 0=N
(p Na,
2
  Na e
 si 
 q / kT
  1  
ni q / kT
e  1
n0=ni2/Na) dx Na 
(assuming complete ionization)
2-11 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Poisson’s
Poisson s Equation
Silicon
d 2 q  
2
surface
d
dx 2
  Na e
 si 

 q / kT
1 
ni
Na
e q / kT

1  

Ec
Eg
Use a trick :
q ( x )
1        2
q E 2
q s B i
(> 0)
E
f   
Ev 2 x  x   x x 2

Oxide p-type silicon


x E
x
2
1       2

   
x d x qN n
   x  d   
 q / kT q / kT
d a
 e 1  2 e
i
1 
2  dx
d    si  
 Na 
x

2-12 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Poisson’s
Poisson s Equation

2
1 x  d   qqN a    q / kT ni 2 q / kT 
   
x

2 x 
d   x  d   
 dx    si
 e

1  2 e
Na
1 

Silicon
surface


E Ec
x Eg
q ( x )
q s q E
i
B
Boundary conditions: (> 0)
E
f
Ev
  x    0
Oxide p-type silicon
d
0
dx x  x

2-13 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Solving Poisson’s Equation

 d 
2
2kTN a  q / kT q  ni  q / kT q
2

E ( x)  
2
   e   1  2 
e   1
 dx   si  kT  N a  kT 

p ( x) p ( x) n( x ) n( x ) N d  N a
1/ 2
  q s / kT q s  ni 2  q s / kT q s 
Qs   si Es   2 si kTN a  e   1  2  e   1
 kT  N a  kT 

Term related to the

Debye length:
What is the value
 si kT
LD  of ni for Si?
q2 Nd

LD=41 nm for Nd =
1016cm-3 at 300K

For details, see C.Y. Chang, S.M. Sze,

ULSI D
Devices,
i Wil
Wiley, Ch
Chapter
t 3 3.

2-14 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Depletion Charge, Inversion Charge

Qs  Qd  Qi
Depletion Inversion
Charge Charge

2-15 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Condition for Strong Inversion

Silicon
surface kT  N a 
 s ( inv )  2 B  2 ln 
q  ni 
Ec
Eg
q ( x )
q s q E
i i.e., (ni2/Na2)exp(qs/kT) = 1.
B E
(> 0) f
Ev
And the electron
p-type silicon
concentration at the surface
Oxide
equals the hole concentration
in the bulk Si.
x

2-16 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Carrier Generation Transient – Example: Photo-

Generation
Depletion
 Electrons generated in the depletion region
region
eg o will be collected
co ected in tthe
e VG>0
potential well
 Electrons generated in the neutral
hν
region will
– Recombine
R bi with ith h
holes
l P Si
P-Si
– Diffuse to depletion region and get
collected in the potential well if it is
within the diffusion length of the 0 xp L
minority
i it carriers
i
 Holes will be collected in the
substrate
 How many of the photo
photo-generated
generated
carriers are collected depends on:
– Diffusion length of minority carriers
– Location and length of the depletion
region

2-17 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Depletion Approximation: 1-D Uniform Doping


qNa Qd = -qN
qNaWd

x
Wd E = -qNa(Wd - x)/si

-EE  = qNa(Wd - x)2/2si

 s = qN
NaWd2/2si
x
Wd
2 si s
Wd 
Wd qNa
x
2
 x 
   s 1  
  Wd 
2-19 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Maximum Depletion Width in MOS (1D Uniform Doping)

In contrast to p n junctions, Wd
p-n 10 When MOS theory
was developed
reaches a maximum value Wdm

Maximum Depletiion Width (µm)

at the onset of strong inversion 1
when
Today’s
Today s device
s = 2B = 2(kT/q)ln(Na/ni):
0.1

4 si kT
k ln(
l ( N a / ni )
M
Wdm  0.01
q2 N a 1.0E+14 1.0E+15 1.0E+16 1.0E+17 1.0E+18
Substrate Doping Concentration (cm-3)
1.0E+19

This defines the threshold condition of a MOSFET. We will

discuss
Wdm also plays a key role in the short-channel that later
scaling
g of a MOSFET,, namely,y, LminWdm.

“minimum” channel length

2-20 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Strong
g Inversion
d 2 kTN a  q ni 2 q / kT 
   2 e 
dx  si  kT N a 
1.2E+19
m-3 )

Inversion charge
g pper
Electron cconcentratioon, n(x) (cm

N a  1016 cm 3
1E+19
area:
8E+18
 s  088
. V 2 si kTni 2 q s / 2 kT
Qi   e
Na
6E+18

 s  085
. V
4E+18 Electron conc. at
surface:
2E+18 ni 2 q s / kT
n( 0)  e
Na
0
0 50 100 150 200

Distance from surface, x (Å ) Inversion layer

thickness:
Large change in carrier concentration with
q ( ) = 2sikT/(qQ
Qi /qn(0) (q i)
small changes in surface potential (s) →
“pinning” of surface potential at 2B Tinv=0.4 nm for Qi = 8×1012cm-2 at 300K

2-21 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

MOSFET Charge
g and Potential
Metal Oxide p-type
silicon Na = 1017 cm-3 tox = 10 nm
Vox 1.2 1E-6
Ec
q s

nsity (C/cm2 )
V)
otential s (V
q Ei 1
B 8E-7
Ef s
0.8 Qs
B
Ev
Vg  0 6E-7
Deple- Neutral
0.6
region Qi

Charge Den
tion

Surface Po
Ef 4E-7
region
0.4
Inversion
region Qd 2E-7
0.2

Q 0 0E+0
M 0 0.5 1 1.5 2 2.5 3 3.5
Gate Voltage Vg (V)
0 W
dm

ttox x Gate voltage equation (Vfb=0):
0):
Q
d
Q Q s
i
V g  V ox   s  s
Qs  Q C ox
M

Note: Cox=ox/tox
Note   q s / kT q s  ni 2  q s / kT q s 
1/ 2

Qs   si Es   2 si kTN a  e   1  2  e   1
and oxEox=siEs  kT  Na  kT 

2-23 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Inversion Charge
g in Log
g Scale
1E-5 1E-6
cm )

cm2 )
2

1E 7
1E-7
sity (C/c

sity (C/c
8E-7

1E-9
6E-7
Inv. Charge Dens

Inv. Charge Dens

1E-11 Qi
4E-7
1E-13 Qi

1E-15 B 2E-7

1E-17 0E+0
0 0.5 1 1.5 2 2.5 3 3.5
Gate Voltage Vg (V)

Na = 1017cm-3 tox = 10 nm
2-24 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Differentiate w.r.t. -Qs

MOS Capacitances V g  V ox   
 Qs

Metal Oxide p-type
silicon
ili
s s
C ox Vox

Gate Gate
Ec
q s

d ( Q s ) q
B
Ei

Vg Vg C
Ef
Ev
Vg  0
dV g Deple
Deple-
tion
Neutral
region
Ef
region
Inversion
Qs Qs d ( Q s ) region

C si 
Cox Cox
d s Q
M

(inversion) 0 W
dm
tox x
Q
d
Q
i
Qs  Q
M

C C C
si d i
Qs Q Q
d i 1 1 d s
 
(low freq.) C Cox d ( Qs )
1 1
 
p-type p-type n+ Cox C si
substrate substrate channel
Through carrier generation/recombination
2-25 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Capacitance-Voltage
g Characteristics - Accumulation

low freq.

high freq.

Deep depletion

 In accumulation, Qsexp(-qs/2kT),  
1 1  2kT / q 
so Csii=-dQs/ds=(q/2kT)Qs  1
=(q/2kT)Cox|Vg-s|. C Cox  V g   s 
 
2-26 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Capacitance-Voltage
g Characteristics – Flatband

low freq.

high freq.

Deep depletion

 At flatband voltage, qs/kT<<1, 1 1 kT 1 LD

   
therefore, Qs=(siq2Na/kT)1/2s. C fb Cox  si q 2 N a Cox  si

2-27 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Capacitance-Voltage Characteristics – Depletion

 In depletion,
1 1 1
 
low freq. C Cox Cd

where
d( Qd )  si qNa  si
high freq. Cd   
d s 2 s Wd
Deep depletion

Note that
qNaWd 2 si qNa s
Vg   s   s
Solving the quadratic equation for ψs Cox Cox
and will give Cd as a function of Vg
2-28 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Capacitance-Voltage
g Characteristics – Inversion
 Inversion, high freq.:
Inversion charge
cannot respond,
1 1 4kT ln( Na / ni )
 
low freq. C min Cox  si q 2 Na

 Inversion, low freq.,

high freq. or connected to a
reservoir:
Deep depletion 1 1 1
 
C Cox Cd  Ci
where
d( Qi ) Qi
Ci  
d s 2 kT / q
is the inv. layer cap.
 
1 1  2kT / q
Like accumulation,  1  (Ci  Cd )
C Cox  V g   s 

2-29 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Split C-V Measurement

 Measures the inversion
charge
c a ge (Qinv) a
and
d dep
depletion
et o
charge (QD) separately and
directly
 Required to extract carrier
mobility

C. Sodini, T. Ekstedt, J. Moll, Solid-State Electronics; Sept. 1982; vol.25, no.9, p.833-4

2-30 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Split C-V Basics

dQN d S
I1   (1)
d S dt
dQB d S
I2   (2)
d S dt

U
s
e
,
,
a
n
d

,
g
e
t
u
s
e

a
n
d

g
e
t
QS  QB  QN  (6) (4) ( 6) (1) (5) (7) /(8) /(9)
dQS  dQN 
Cox  Cox  dV
dQS dQS d S d S dV d S dQN dQN
 S  VG  VFB 
QS
 (3)    (7 ) I1  G   G   (10)
Cox dVG d S dVG C  dQ N

dQB dt  C  N 
dQ dQB  dt dVG dVG
ox
d S d S  ox d S d S 
d S Cox
  ( 4) dQB
dVG C  dQS Cox  dQB 
dQB dQB d S d S  Cox  dV
ox
d S    (8) I  dVG  d S dQB dQB
dVG d S dVG C  dQN  dQB 2  G   (10)
d S dVG dQS dVG 1 dt  C  N 
dQ dQ B  dt dVG dVG
  d S d S
ox
 (5)  ox d S d S 
dt dt dVG dt Cox
dQN
Cox
dQN dQN d S d S
   (9)
dVG d S dVG C  dQ QN dQ

QB
d S d S
ox

C. Sodini, T. Ekstedt, J. Moll, Solid-State Electronics; Sept. 1982; vol.25, no.9, p.833-4

2-32 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

C-V Measurement

 When performing CV measurements,

meas rements start from
inversion and sweep the gate voltage to
accumulation
 Inversion layer build up is a slower process than
collapsing the inversion layer and forming the
accumulation
l ti layer
l (see
( Taur
T & Ning
Ni p. 28,
28
Chapter 2.1.4.6)

2-33 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Flatband Voltage
g
Zero flatband Qs
Vg   s  V ox   s 
voltage: C ox
Vacuum Vacuum
level level
0.95 eV
Ec
qm = 4.10 eV q = 4.05 eV
q s

Ec
E
f Eg 
8-9 eV q E
i
Metal B 1.12 eV
E
Ev f
(aluminum)
Silicon
(p-type)

Ev

Silicon
dioxide
Qs
V g  V FB   s  V ox  V FB   s 
C ox
2-34 H.-S. Philip Wong EE 316 Department of Electrical Engineering
 Stanford University

Effect of Gate Work Function

Qd
Vt  V fb  2 B  Vox  V fb  2 B 
Cox
Q
V fb  (m   s )  ox
Cox
Vacuum Vacuum
Eg
s     B
level l l
level
0.95 eV
Ec
q = 4.05 eV
2q
qm = 4.10 eV
q s

E
f
Ec
q E
Eg  m   (n  poly)
8-9 eV B i
Metal E 1.12 eV
Ev f
(aluminum)
Silicon Eg
(p-type) m    ( id )
(midgap)
2q
Ev
Eg
Silicon m    (p  poly)
p y)
dioxide q

2-35 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Effect of Gate Work Function

Example: n+ polysilicon gate on p-type silicon

Eg kT  Na 
 ms    B   0.56  ln 
2q q  ni 

Vg  0 Vg  V  ms
fb


B qms
Ec E Ec
f
E E
E i i
f E E
Ev f Ev f

n+ poly p-type silicon n+ poly p-type silicon

oxide

oxide

2-36 H.-S. Philip Wong EE 316 Department of Electrical Engineering

 Stanford University

Polysilicon Gate Depletion Effect

n+ poly Oxide p-type silicon
Gate eq. becomes:
Qs
Vox V g  V fb   s   p 
Ec C ox
s and,
Ei
E 1 1 1 1
Vg f   
Ec Ev C C ox C si C p
E
f p
E 1
i Why does
Actual CV curve capacitance fall
0.8 with increasing
tox

Capacittance
gate bias?
Ev
0.6
tinv Cinv
0.4

Typically, tinv is 0.7-1.0 nm 0.2

thicker than tox. 0
-2 -1 0 1 2
Gate voltage
2-37 H.-S. Philip Wong EE 316 Department of Electrical Engineering