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Cautions
Keep safety first in your circuit designs!
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 HA16107P/FP, HA16108P/FP
PWM Switching Regulator for
High-performance Voltage Mode Control

ADE-204-012C (Z)

Rev.3
Jul. 2002

Description
The IC products in this series are primary control switching regulator control IC’s appropriate for obtaining
stabilized DC voltages from commercial AC power.

These IC’s can directly drive power MOS FET’s, they have a timer function built in to the secondary
overcurrent protection, and they can perform intermittent operation or delayed latched shutdown as
protection operations in unusual conditions. They can be used to implement switching power supplies with
a high level of safety due to the wide range of built-in functionality.

Functions
• 6.45 V reference voltage
• Triangle wave generator
• Error amplifier
• Under voltage lockout protector
• PWM comparator
• Pulse-by-pulse current limitting
• Timer-latch current limitting (HA16107)
• ON/OFF timer function (HA16108)
• Soft start and quick shutdown
• Output circuit for power MOS FET driving
HA16107P/FP, HA16108P/FP

Features
• Operating frequencies up to a high 600 kHz
• Built-in pre-driver circuit for driving power MOS FET
• Built-in timer latch over-current protection function (HA16107)
• The OCL enables intermittent operation by an ON/OFF timer for prevention of secondary overcurrent.
(HA16108)
• The UVL function (under voltage lockout) is applied to both Vin and Vref.
• ON/OFF reset: an auto-reset function which is based on the time constant of an external capacitor and
observation of drops in Vin.
• Since the over-voltage protection function OVP (the TL pin) only observes voltage drops in Vin, it is
possible to use the OVP and ON/OFF pin for independent purposes.
• Built-in 34 V Zener diode between Vin and ground.

Ordering Information
Typical Threshold Voltage
Product UVL1 OVP Notes Package
HA16107P Hi: 16.2 V 7.0 V Timer latch protection DP-16
HA16107FP Lo: 9.5 V FP-16DA
HA16108P Hi: 16.2 V Hi: 7.0 V On-off timer protection DP-16
HA16108FP Lo: 9.5 V Lo: 1.3 V (intermittent operation possible) FP-16DA

Rev.3, Jul. 2002, page 2 of 2

 HA16107P/FP, HA16108P/FP

Pin Arrangement

Note 2
VIN 1 16 TL, ON/OFF

OUT 2 15 E/O

CL(+) 3 14 IN(−)

VE 4 13 NC

CL(−) 5 12 GND

Note 1
RT1 6 11 IN(+)

CT 7 10 ST

RT2 8 9 Vref

(Top view)
Notes: 1. In the SOP package models (HA16107FP and HA16108FP) pins 4, 5, and 13 are connected
inside the IC. However, all must be connected to the system ground.
2. Pin 16 is TL (HA16107), ON/OFF (HA16108).

Pin Functions
• HA16107P, HA16108P
Pin No. Symbol Pin Functions
1 VIN Input voltage
2 OUT Pulse output
3 CL (+) Current limiter
4 VE Output ground
5 CL (–) Current limiter
6 RT1 Timing resistor (rising time)
7 CT Timing capacitor
8 RT2 Timing resistor (falling time)
9 Vref Reference voltage output
10 ST Soft start
11 IN (+) Error amp (+) input
12 GND Ground
13 NC NC
14 IN (–) Error amp (–) input
15 E/O Error output
16 TL, ON/OFF Timer latch (HA16107), ON/OFF (HA16108)

Rev.3, Jul. 2002, page 3 of 3

HA16107P/FP, HA16108P/FP
• HA16107FP, HA16108FP
Pin No. Symbol Pin Functions
1 VIN Input voltage
2 OUT Pulse output
3 CL (+) Current limiter
4 GND Ground
5 GND Ground
6 RT1 Timing resistor (rising time)
7 CT Timing capacitor
8 RT2 Timing resistor (falling time)
9 Vref Reference voltage output
10 ST Soft start
11 IN (+) Error amp (+) input
12 GND Ground
13 GND Ground
14 IN (–) Error amp (–) input
15 E/O Error output
16 TL, ON/OFF Timer latch (HA16107), ON/OFF (HA16108)

Rev.3, Jul. 2002, page 4 of 4

 HA16107P/FP, HA16108P/FP

Block Diagram

• HA16107P/FP
TL E/O IN (−) NC GND IN (+) ST Vref
16 15 14 13 12 11 10 9

−
EA Error amp.
140 µA +

VIN 34 V
UVL1 Vref
H 6.45 V
16 µA L zener type UVL2
VL VH Ref. O H UVL2
voltage V L
R Q Gen. P 4V 5V
S
4 µA On/Off latch UVL1
(VTH = 7 V) ST

+ + − PWM Comparator Triangle waveform

UVL1 and UVL2
Triangle waveform OSC
Pulse-by-pulse latch 3.4 V 10 µA

Vref
Q R Triangle waveform
QCLM Q S Latch reset pulse
Current
OUT limiter ON duty pulse
VC VE

1 2 3 4 5 6 7 8
VIN OUT CL (+) VE CL (−) RT1 CT RT2

• HA16108P/FP
ON/OFF E/O IN (−) NC GND IN (+) ST Vref
16 15 14 13 12 11 10 9

−
EA Error amp.
140 µA +

VIN 34 V
UVL1 Vref
H 6.45 V
16 µA L zener type UVL2
VL VH Ref. O H UVL2
voltage V L
R Q Gen. P 4V 5V
S
4 µA On/Off latch UVL1
(VTH = 7 V) ST

+ + − PWM Comparator Triangle waveform

UVL1 and UVL2 Triangle waveform OSC
Pulse-by-pulse latch 3.4 V 10 µA

Q R Vref Triangle waveform

QCLM Q S Latch reset pulse
Current
OUT limiter ON duty pulse
VC VE

1 2 3 4 5 6 7 8
VIN OUT CL (+) VE CL (−) RT1 CT RT2
Note: Dotted lines apply to the SOP package model (pins 4, 5, and 13: ground)

Rev.3, Jul. 2002, page 5 of 5

HA16107P/FP, HA16108P/FP

Function and Timing Chart

Triangle Waveform and PWM Output

• Timing chart (during normal operation)

Triangle waveform
VTH 4.2 V typ is output to CT pin

E/O

CT
2VBE VTL 2.2 V typ

VRT2 0V

VIN
OUT 0V

Dead band tON

tDB
• Oscillator equivalent circuit

9 Vref
(connected internally)
×2 ×2
RT2 VRT2

×2 −
8 +
I2
I1 I1
Comparator for
triangle waveform
6 7 oscillation
2I2
−
×2
RT1 CT +
0.6 V

The × 2s are transistors whose emitter area is doubled.

Vref − 2VBE CT × RT1 × 2V RT2

I1 = tDB = ≈ 0.4 × CT × RT1 (s) Du max =
RT1 Vref − 2VBE 2RT1
Vref − 2VBE RT2 1 − Du max
I2 = tON ≈ tDB (s) fOSC ≈ (Hz)
RT2 2RT1 − RT2 tDB

Note: When fOSC is high, the actual value will differ from that given by the formula due to the delay time.
Determine the correct constants after constructing a test circuit.

Rev.3, Jul. 2002, page 6 of 6

 HA16107P/FP, HA16108P/FP
1. Timing in Normal Operation
Timing in these ICs is based on a triangular voltage waveform. The rising edge (leading edge) defines
the deadband time tDB. The falling edge (trailing edge) defines the ON-duty control band tON. PWM
output is on in the area within tON that is bounded above by the triangle wave VCT and error output VE/O.
The following pin outputs are related to PWM control:
• CT (pin 7): triangle-wave voltage output
• E/O (pin 15): error output voltage
• RT2 (pin 8): ON-duty pulse output voltage
• OUT (pin 2): PWM pulse output (for driving the gate of a power MOS FET)

2. Triangle Oscillator, Waveform and Frequency

The triangle oscillator in these ICs generates a triangular waveform by charging and discharging timing
capacitor CT with a constant current, as shown in the equivalent circuit. The CT charge current is:
VREF − 2VBE
I(CTchg) = I1 =
RT1
The discharge current is:
VREF − 2VBE
I(CTdischg) = 2I2 − I1, where I2 =
RT2
In these equations Vref (reference voltage) is typically 6.45 V, and VBE (base-emitter voltage of internal
transistors) is about 0.7 V.
The deadband time is:
CT × RT1 × 2V
tDB = + 0.25 µs
VREF − 2VBE
≈ 0.4 × CT × RT1 + 0.25 µs
The ON-duty time is:
RT2
tON = tDB ×
2RT1 − RT2
The 0.25 µs in these equations is a correction term for internal circuit delays.
The maximum ON-duty is
RT2
Du max =
2RT1
The oscillating frequency is:
1
fOSC =
0.4 CT RT1 + 0.25 µ
+ 0.25 µ
RT2
1–
2RT1
1
= (Hz)
0.8 CT RT12 + 0.25µ × 2RT1
+ 0.25 µ
2RT1 − RT2
When RT1 = RT2, the maximum ON-duty is 50%, and:
1
fOSC ≈
0.8 CT RT1 + 0.25 µ × 2 + 0.25 µ
1
= (Hz)
0.8 CT RT1 + 0.75 µ
This approximation is fairly close, but it should be checked in-circuit.

Rev.3, Jul. 2002, page 7 of 7

HA16107P/FP, HA16108P/FP
3. Programming of Maximum ON-Duty (Du Max)
The preceding equations should be used to program the deadband or maximum ON-duty. The
following table gives a summary.

Condition RT1 > RT2 RT1 = RT2 RT1 < RT2

Triangle
waveform

Du max Less than 50% 50% Greater than 50%*

Note: In a primary-control switching regulator, Du Max > 50% is dangerous because the transformer will
saturate.

Soft Start and Quick Shutdown

One purpose of the soft-start function is to protect the switching controller and power MOS FET from
surges at power-up. Another purpose is to let the secondary-side DC voltage rise smoothly.

When power goes off, the quick-shutdown function rapidly discharges the capacitor in the soft-start circuit
(and at the same time switches the PWM output off) to prepare for the next power-on.

The soft-start function in these ICs lets the PWM output develop smoothly from zero to the designated
pulse width at power-up. The soft-start voltage is the 3.8 V voltage value of an internal Zener diode, so the
PWM output is able to start widening gradually as soon as the soft-start function starts operating. The soft-
start function will start promptly even if CST is large.

The soft-start and quick-shutdown modes are selected automatically in the IC, under control of the UVL
signal.

Rev.3, Jul. 2002, page 8 of 8

 HA16107P/FP, HA16108P/FP

• Timing waveforms
Level determined by transformer

VIN
16.2 V

VIN 9.5 V

6.45 V
5V Vref
Vref 4V
0V
VST VCT CST discharge
4.2 V
VCT, VST, 3.8 V
VE/O 2.2 V
0V
VE/O
VIN Quick shutdown
VOUT
(PWM pulse) 0V
Soft start Normal operation (Time t)

Vref
Vref
9 from Vref
from UVL2
CST
(Effective for
ST quick shutdown)
10 +
Zener +
3.8 V diode
−
PWM comparator
10 µA
VCT

E/O

15 7

Note: The soft-start time constant is determined by CST and the constant-current value (typically 10 µA).

Rev.3, Jul. 2002, page 9 of 9

HA16107P/FP, HA16108P/FP

Vref Protection Functions: Overvoltage and Undervoltage

Vref overvoltage and undervoltage conditions are detected by the overvoltage detection circuit and UVL2
circuit. PWM output shuts down when Vref ≥ 8 V. UVL2 detects undervoltage with hysteresis between
approximately 4 V and 5 V. PWM output also shuts down below these voltages. It follows that PWM
output will shut off whenever the Vref pin is shorted to the power supply (VIN) or ground (GND). PWM
output also shuts off when VIN is turned on or off.

The following diagram shows how these protection functions operate when power comes on and goes off
(Vref < 6.45 V), and when a high external voltage is applied to the Vref pin (Vref > 6.45 V).

PWM output shut-

down region PWM output
PWM
operating region
OUT Power-off,
or shorted
to ground
Shorted to
power supply PWM output
shut-down region
Power-up

Vref
0 4V 5V 6.45 V 8 V 10 V

Vref
UVL2 OVP

1. Current-Limiter Circuit
The current limiter pin (CL) is connected to the emitter of an npn transistor, as shown in the block
diagram. The threshold voltage is 240 mV typ. The switching speed of this circuit is approximately
100 ns from detection of overcurrent to shut-down of PWM output. Switching speed increases with the
strength of the signal input to the CL pin.
Instead of simple pulse-by-pulse current limiting, in these ICs the current limiting circuit is linked to the
timer-and-latch or ON/OFF timer circuit, and also detects the degree of overcurrent. The overcurrent
value is determined from the point at which current limiting is triggered in the ON-duty cycle. With a
large overcurrent (causing current limiting to operate even at a small ON-duty), the IC automatically
shortens the timer time.

Rev.3, Jul. 2002, page 10 of 10

 HA16107P/FP, HA16108P/FP

Undervoltage Lockout and PWM Output

The undervoltage lockout function turns off the PWM pulse output when the controller’s supply voltage
goes below a designated value. These ICs have two undervoltage lockout circuits. The UVL1 circuit
senses the supply voltage VIN. The UVL2 circuit senses the Vref voltage. A feature of these ICs is that
PWM output is turned on only when both voltages are above designated values. Otherwise, the IC operates
in standby mode.

The two built-in undervoltage lockout circuits make it possible to configure an extremely safe power
supply system. PWM output will shut down under a variety of abnormal conditions, such as if Vref is
shorted to ground while VIN is applied.

• UVL1 (VIN and Vref) *1

IIN 9.5 V 16.2 V

VIN
0 10 V 20 V 30 V 34 V

Notes: 1. Breakdown voltage of

Vref 6.45 V the internal Zener
diode (Vz = 34 V typ).
*2 2. Hysteresis characteristic.

VIN
0 10 V 20 V 30 V

• UVL2 (Vref and PWM output)

Vref
6.45 V
5V
4V

VIN
0 10 V 20 V 30 V

Operating region
OUT

VIN
0 10 V 20 V 30 V
PWM output shut-down region
• UVL1 and UVL2
VIN (UVL1) L H H L
Vref (UVL2) L L H H
PWM OUT L L OUT L
Standby mode 
Note: Double circles indicate standby mode.

Rev.3, Jul. 2002, page 11 of 11

HA16107P/FP, HA16108P/FP

Timer Latch and ON/OFF Timer

The HA16107 has a built-in timer-latch function. The HA16108 has a built-in ON/OFF timer function.
The timer-latch function is an overvoltage protection function that combines latched shutdown of PWM
output with a timer function to vary the time until latched shutdown occurs according to the overcurrent
value. A dedicated voltage detection pin is provided in addition to Vref overvoltage protection.
The ON/OFF timer function is equivalent to the above timer-latch function without the latch. If
overcurrent is detected continuously, PWM output shuts down temporarily, then normal operation resumes.
This process repeats, temporary shutdown alternating with normal operation.
Both the timer-latch function in the HA16107 and the ON/OFF function in the HA16108 wait for an
interval after overcurrent detection before shutting down PWM output. The interval is determined by
capacitor CTM and the value of the charge/discharge current supplied internally from the IC. Normal
operation therefore continues if a single overcurrent spike is detected, while if continuous overcurrent is
detected, the current and voltage droop curves for the secondary-side output have sharp characteristics.
1. Use of Timer-Latch Pin (HA16107)
• Timer-Latch Usage
See external circuit 1 in the following diagram. Under continuous overcurrent, the CML switch turns
on, charging CTM with 12 µA. PWM output shuts down when the voltage at pin 15 exceeds 7 V.
• Overvoltage Protection Usage
See external circuit 2 in the diagram. This configuration is suitable when overvoltage is detected by an
OVP signal received through an optocoupler from the DC output on the secondary side of an AC/DC
converter. PWM output shuts down when the OVP signal allows the voltage at the TL pin to exceed 7
V. The shutdown is latched. VIN must go below approximately 6.5 V (VINR2) to release the latched state.

• External circuit 1 • External circuit 2 VIN

16 µA
from CML
OVP signal
OVP with (from secondary)
15
latch timer TL
CTM
4 µA
HA16107

VTH Latch
7.0 V (PWM output shuts down)

VTL B

0V t
OCL detected continuously
(activating pulse-by-pulse current limiter)
Notes: 1. Path A is followed if the OCL input stops before VTH is reached.
2. Path B is followed if OCL is detected continuously until the latch point is reached.
3. The latch function is cleared when VIN goes below approximately 7.0 V.

Rev.3, Jul. 2002, page 12 of 12

 HA16107P/FP, HA16108P/FP
2. Use of ON/OFF Timer Pin (HA16108)
• External Circuit

16 µA
from CML
ION
16 OVP with
+ latch timer
IOFF

4 µA
HA16108

• ON/OFF Timer Operation

tOFF tON
VTHH
7.0 V

VTHL
1.2 V

0V t
OCL detected PWM OCL detected
(PWM output on) output (PWM output on)
shut down

Pulse-by-pulse current limiting

C × 5.8 V
tON ≈
(0.9 − Du) × 16 µA − 4 µA

tOFF ≈ C × 5.8 V
4 µA

Notes: 1. C is the capacitance of an external timing capacitor connected between this pin and ground.
2. Du is the ON-duty of the PWM output when overcurrent limiting is triggered.
3. The values of tON and tOFF for TL can be determined by the same equations as given for
the ON/OFF timer, except that 5.8 V (VTHH − VTHL) becomes VTHH = 7 V.
4. If the timer goes off during soft start or in the undervoltage lockout region, after recovery,
output will come on after the soft-start time or after the rise time to the undervoltage lockout
release point, which is determined by the time constant.

Rev.3, Jul. 2002, page 13 of 13

HA16107P/FP, HA16108P/FP

Absolute Maximum Ratings

(Ta = 25°C)

Item Symbol Rating Value Units Notes

Supply voltage VIN 30 V
Output current (DC) IO ±0.2 A
Output current (peak) Iopeak ±2 A
Current limiter voltage VCL +4, –1 V
Error amp input voltage VIEA Vref V
E/O output voltage VIE/O Vref V
RT1 pin current IRT1 500 µA
RT2 pin current IRT2 5 mA
Power dissipation PT 680 mW 1, 2
Operating temperature range Topr –20 to +85 °C
Storage temperature range Tstg –55 to +125 °C
Notes: 1. For the “FP” products (SOP package), this value is when mounted on a 40 by 40 by 1.6 mm
glass epoxy substrate. However, this value must be derated by 8.3 mW/°C from Ta = 45°C.
When the wiring density is 10%, and 11.1 mW/°C from Ta = 64°C when the wiring density is
30%.
2. For the “P” products (DIP package), this value is valid up to 45°C, and must be derated by
8.3 mW/°C above 45°C.
3. In the case of SOP, use center 4 pins, (4), (5), (12), (13) for solder-mounting and connect the
wide ground pattern, because these pins are available for heat sink of this IC.
Power dissipation PT (mW)

700 45˚C 64˚C 30% Wiring density

600
10% Wiring density
500
400
300
200
100

–20 0 20 40 60 80 100 120 140

Ambient temperature Ta (˚C)

Rev.3, Jul. 2002, page 14 of 14

 HA16107P/FP, HA16108P/FP

Electrical Characteristics
(Ta = 25°C, VIN = 18 V, fOSC = 100 kHz)

Section Item Symbol Min Typ Max Unit Test Conditions Note
Reference Output voltage Vref 6.10 6.45 6.80 V
voltage
Line regulation Line — 30 60 mV 12 V ≤ VIN ≤ 30 V
Load regulation Load — 30 60 mV 0 mA ≤ IO ≤ 10 mA
Temperature ∆Vref/ — 40 — ppm/
stability ∆Ta °C
Short circuit current IOS 30 50 — mA Vref = 0 V
Over voltage protec- Vrovp 7.4 8.0 9.0 V
tion (Vref OVP
voltage)
Triangle Maximum frequency fmax 600 — — kHz
wave
Minimum frequency fmin — — 1 kHz
generator
Voltage stability ∆f/fo1 — ±1 ±3 % 12 V ≤ VIN ≤ 30 V
fo1 = (fmax + fmin)/2
Temperature stability ∆f/fo2 — ±1 — % –20°C ≤ Ta ≤ +85°C
fo2 = (fmax + fmin)/2
Frequency accuracy fOSC 270 300 330 kHz RT1 = RT2 = 27 kΩ
CT = 120 pF
PWM Minimum deadband tDB — — 1.0 µs
comparator pulse width
Low level threshold VTL 1.9 2.2 2.5 V
voltage
High level threshold VTH 3.8 4.2 4.6 V
Differential threshold ∆VTH 1.7 2.0 2.3 V
Deadband width ∆DB1 — ±1 ±3 % RT1 = RT2 = 27 kΩ
initial accuracy CT = 470 pF
Deadband width ∆DB2 — ±0.2 ±2.0 % 12 V ≤ VIN ≤ 30 V
voltage stability (Dmax – Dmin)/2
Deadband width ∆DB3 — ±1 — % –20°C ≤ Ta ≤ +85°C
temperature stability (Dmax – Dmin)/2
Error amp Input offset voltage VIO — 2 10 mV
Input bias current IIB — 0.8 2.0 µA
Input sink current Iosink 80 140 — µA VO = 2 V
Output source current Iosource 80 140 — µA VO = 5 V

Rev.3, Jul. 2002, page 15 of 15

HA16107P/FP, HA16108P/FP

Electrical Characteristics (cont.)

(Ta = 25°C, VIN = 18 V, fOSC = 100 kHz)

Section Item Symbol Min Typ Max Unit Test Conditions Note
Error amp High level output VOH Vref – — — V IO = 10 µA
(cont.) voltage 1.5
Low level output VOL — — 0.5 V IO = 10 µA
voltage
Voltage gain GV — 55 — dB f = 10 kHz
Band width BW — 15 — MHz
(–) Common mode VCM– 1.2 — — V
voltage
(+) Common mode VCM+ — — Vref – V
voltage 1.5
Over- (+) Threshold voltage VTH+ 0.216 0.240 0.264 V
current
(+) Bias current IB+ — 180 250 µA VCL+ = 0 V
detector
(–) Threshold voltage VTH– –0.264 –0.240 –0.216 V 1, 2
(–) Bias current IB– — 950 1350 µA VCL = –0.3 V 1, 2
Response time toff — 100 — ns CL; open
VCL = +0.35 V
Soft start High level voltage VSTH 3.2 3.8 4.4 V Isink = 1 mA
Sink current Isink 7 10 13 µA VST = 2.0 V
Under VIN high level thre- VINTH 14.7 16.2 17.7 V
voltage shold voltage
lockout 1
VIN low level thre- VINTL 8.5 9.5 10.5 V
shold voltage
Threshold differential ∆VTH 5.2 6.2 7.2 V (VINTH – VINTL)
voltage
Under Vref high level thre- VrTH 4.5 5.0 5.5 V
voltage shold voltage
lockout 2
Vref low level thre- VrTL 3.5 4.0 4.5 V
shold voltage
Notes: 1. Only applies to the HA16107P, HA16108P
2. The terminal should not be applied under –1.0 V.

Rev.3, Jul. 2002, page 16 of 16

 HA16107P/FP, HA16108P/FP

Electrical Characteristics (cont.)

(Ta = 25°C, VIN = 18 V, fOSC = 100 kHz)

Section Item Symbol Min Typ Max Unit Test Conditions Note
Timer latch, Latch threshold VTHH 6.5 7.0 7.5 V
ON/OFF voltage
2
timer*
VIN reset voltage VINR2 6.0 6.5 7.0 V
Reset voltage VTHL2 1.0 1.3 1.6 V 1
Differential threshold ∆V 2.0 3.0 — V (VINTL – VINR2)
to UVL low voltage
Source current Isource 8 12 16 µA Over current
(OCL mode) detection mode
Sink current Isink 2.5 4 5.5 µA TL(ON/OFF)
(latch mode) terminal = 4 V
Output Low voltage VOL1 — 1.7 2.2 V Iosink = 0.2 A
High voltage VOH VIN – — — V Iosource = 0.2 A
2.2
Low voltage VOL2 — — 0.5 V Iosink = 1 mA
(standby mode)
Rising time tr — 40 — ns CL = 1000 pF
Falling time tf — 60 — ns CL = 1000 pF
Total Standby current Ist — 160 250 µA VIN = 14 V
Operation current IIN1 — 16 20 mA VIN = 30 V,
CL = 1000 pF,
f = 100 kHz
Operation current IIN2 — 12 16 mA VIN = 30 V,
f = 100 kHz,
Output open
ON/OFF latch IIN3 — 350 460 µA VIN = 14 V
current
VIN – GND Zener VZ 30 34 — V
voltage
Notes: 1. Only applies to the HA16108P/FP.
2. Timer latch: HA16107P/FP.
ON/OFF timer: HA16108P/FP.

Rev.3, Jul. 2002, page 17 of 17

HA16107P/FP, HA16108P/FP

Note on Standby Current

In the test circuit shown in figure 1, the operating current at the start of PWM pulse output is the standby
current.

If the resistance connected externally to the Vref pin (including RT2) is smaller than that of the test circuit,
the apparent standby current will increase.

↑
VIN Ist

Vref HA16107
Series + CIN
↑ IIN
Rref

Figure 1 Standby Current Test Circuit

Rev.3, Jul. 2002, page 18 of 18

 HA16107P/FP, HA16108P/FP

Application Note
• Case:
When DC power is applied directly as the power supply of the HA16107/HA16108, without using the
transformer backup coil.
• Phenomenon:
The IC may not be activated in the case of a circuit in which VIN rises quickly (10 V/100 µs or faster),
such as that shown in figure 2.
• Reason:
Because of the IC circuit configuration, the timer latch block operates first.
• Remedy (counter measure):
Take remedial action such as configuring a time constant circuit as shown in figure 3, to keep the VIN
rise speed below 10 V/100 µs.

If the IC power supply consists of an activation resistance and backup coil, as in an AC/DC converter, The
VIN rise speed is usually around 1 V/100 µs, and there is no risk of this phenomenon occurring.

Output
Input

VIN

HA16107
Series
VIN
Feedback

GND

Figure 2 Example of Circuit with Fast VIN Rise Time

Input Output

Time constant R 51Ω

circuit
VIN

HA16107
VIN Series
18 V
1 µF C Feedback

GND

Figure 3 Sample Remedial Circuit

Rev.3, Jul. 2002, page 19 of 19

HA16107P/FP, HA16108P/FP

Characteristic Curves

Operating Current vs. Power Supply Voltage

40
Ta = 25°C
RT1 = RT2 = 27 kΩ
CT = 470 pF
30 fOSC = 100 kHz
Operating current (mA)

20

10

0 10 20 30 40
Power supply voltage (V)

Latch Current vs. Power Supply Voltage

2.0
Ta = 25°C
RT1 = RT2 = 27 kΩ
CT =470 pF
1.5 fOSC = 100 kHz
Latch current (mA)

1.0

0.5

0 10 20 30 40
Power supply voltage (V)

Rev.3, Jul. 2002, page 20 of 20

 HA16107P/FP, HA16108P/FP

Standby Current vs. Power Supply Voltage

400
Ta = 25°C
RT1 = RT2 = 27 kΩ
CT =470 pF
300 fOSC = 100 kHz
Standby current (µA)

200

100

0 4 8 12 16 20
Power supply voltage (V)

Output VOH vs. Reference Voltage

20
Ta = 25°C
VIN = 20 V
CT = 470 pF
15
Output VOH (V)

10

Vref Vref
UVL2 Voltage OVP Voltage

0 2 4 6 8 10
Reference voltage (V)

Rev.3, Jul. 2002, page 21 of 21

HA16107P/FP, HA16108P/FP

Reference Voltage vs. Power Supply Voltage

8
Ta = 25°C
RT1 = RT2 = 27 kΩ
6 CT =470 pF
Reference voltage (V)

fOSC = 100 kHz

0 10 20 30
Power supply voltage (V)

Output OFF Time vs. VCL

400
Ta = 25°C
RT1 = RT2 = 27 kΩ
CT =470 pF
VCL
300 fOSC = 100 kHz
Output OFF time (ns)

200

CL = 100 pF

100 CL = unloaded

0 0.2 0.3 0.4

VCL (V)

Rev.3, Jul. 2002, page 22 of 22

 HA16107P/FP, HA16108P/FP

Output ON Duty vs. Error Input Voltage

60

Ta = 25°C
50 RT1 = RT2 = 27 kΩ
CT =470 pF
Output ON duty (%)

40 fOSC = 100 kHz

30

20

10

0 1 2 3 4 5

Error input voltage (V)

Rev.3, Jul. 2002, page 23 of 23

HA16107P/FP, HA16108P/FP

Reference Voltage and PWM Out vs. CL(+)

Vref

0 0.1 0.2 0.3 0.4 3.0

PWM OUT

0 0.1 0.2 0.3 0.4 3.0

CL(+)

Reference Voltage and PWM Out vs. CL(−)

Vref

0 −0.1 −0.2 −0.3 −0.4 −1.0

PWM OUT

0 −0.1 −0.2 −0.3 −0.4 −1.0

CL(−)

Rev.3, Jul. 2002, page 24 of 24

 HA16107P/FP, HA16108P/FP

Timing Resistance vs. Deadband Duty

20

VIN = 18V

Ta = 25°C
Timing resistance RT1,RT2 (kΩ)

15
CT = 470 pF

fOSC ≈ 100 kHz

10
RT1

RT2
5

0
30 40 50 60 70 80

Deadband duty (%)

Temperature Fluctuation vs. Ambient Temperature

2000
VIN = 18V
RT1 = RT2 = 27 kΩ

CT = 470 pF
1000
Temperature fluctuation (ppm)

fOSC = 100 kHz

−1000

−2000
−20 0 25 50 75 85

Ambient temperature (°C)

Rev.3, Jul. 2002, page 25 of 25

HA16107P/FP, HA16108P/FP

Frequency Variance vs. Ambient Temperature

10
VIN = 18V
RT1 = RT2 = 27 kΩ
CT = 470 pF
5 fOSC = 100 kHz
Frequency variance (%)

−5

−10
−20 0 25 50 75 85
Ambient temperature (°C)

Frequency Variance vs. Ambient Temperature

10
VIN = 18V
RT1 = RT2 = 27 kΩ
CT = 120 pF
5 fOSC = 300 kHz
Frequency variance (%)

−5

−10
−20 0 25 50 75 85
Ambient temperature (°C)

Rev.3, Jul. 2002, page 26 of 26

 HA16107P/FP, HA16108P/FP

Frequency Variance vs. Ambient Temperature

10
VIN = 18V
RT1 = RT2 = 13 kΩ
CT = 120 pF
5 fOSC = 600 kHz
Frequency variance (%)

−5

−10
−20 0 25 50 75 85
Ambient temperature (°C)

Output ON Duty Variance vs. Ambient Temperature

10
VIN = 18V

5
Output ON duty variance (%)

0
f = 100 kHz
f = 300 kHz

−5
f = 600 kHz

−10
−20 0 25 50 75 85
Ambient temperature (°C)

Rev.3, Jul. 2002, page 27 of 27

HA16107P/FP, HA16108P/FP

Oscillator Frequency vs. Timing Resistance

600
500
VIN = 18 V
Ta = 25°C

300
C
T =
12
0
pF

27
0
pF
100
Oscillator frequency (kHz)

90 47
0
pF
70

50
82
0
pF

30
33
00
pF

10
9

5 7 10 30 50 70 100
Timing resistance RT1 (= RT2) (kΩ)

Rev.3, Jul. 2002, page 28 of 28

 HA16107P/FP, HA16108P/FP

Vout Output Rising Waveform Test circuit Ta = 25°C

40
RT1 = RT2 = 27 kΩ
30 CT = 470 pF
Current probe VIN fOSC = 100 kHz
Vout (V)

20
IO
10 TL + 1 µF
OUT
0 CL
CL (+)
1000 pF
27 kΩ
500 R T1
IO (mA)

470 pF
0 CT ST
CST
+ 1 µF
RT2 Vref
−500
27 kΩ

200 ns/div * Current probe: Tektronix AM503

Vout Output Falling Waveform

40

30
Vout (V)

20

10

500
I O (mA)

−500

200 ns/div

Rev.3, Jul. 2002, page 29 of 29

HA16107P/FP, HA16108P/FP

Operating waveform at the TL pin HA16107

Test circuit VIN = 18V
RT1 = RT2 = 27 kΩ
When overcurrent is input at the point VIN CT = 470 pF
where the duty cycle is 0%. fOSC = 100 kHz
7
TL +
OUT SW
6 CL 1 µF
CL(+)
1000 pF
B Clock
5 RT1
470 pF
27 kΩ CT ST
4 CST
+ 1 µF
VTL (V)

RT2 Vref
3 27 kΩ

A
2

1 Triangle
wave
0
CL(+) when
input at a
duty of 0%

0.5 sec/div CL(+) when

tON tOFF
input at a
duty of 30%
Output pulse shutdown region
t1
SW ON SW OFF
t2

When overcurrent is input at the point

t1
where the duty cycle is 30%. Du = × 100 (%)
t2
7
Enlargement of section A
6
a b c

5 VTL

B
4
CTL discharged at 4 µA
VTL (V)

3 CTL discharged at 12 µA
t
2
A Enlargement of section B

1
VTL CTL discharged at 4 µA
0

t
tON tOFF 0.5 sec/div
a to b : PWM pulse output is High
Output pulse shutdown region b : The point where overcurrent
is detected
SW ON SW OFF
b to c : PWM pulse output is Low.

Rev.3, Jul. 2002, page 30 of 30

 HA16107P/FP, HA16108P/FP

Operating waveform at the ON/OFF pin HA16108

Test circuit V IN = 18V
VIN R T1 = R T2 = 27 k½
When overcurrent is input at the point C T = 470 pF
where the duty cycle is 0%. f OSC = 100kHz
7 ON/OFF
+
OUT
6 CL 1 µF
1000 pF CL(+)
B
Clock
5 R T1
470 pF
27 k½ CT ST
V ON/OFF (V)

4 C ST
+ 1 µF
R T2
3 27 k½

2
A

1 Triangle
wave
0
CL(+) when
input at a
0.5 sec/div duty of 0%

t ON t OFF t ON t OFF t ON t OFF CL(+) when

input at a
duty of 30%
t1
Output pulse shutdown region
SW ON SW OFF t2

When overcurrent is input at the point t1

where the duty cycle is 30%. Du = × 100 (%)
t2
7
Enlargement of section A
6 B
a b c
V TL
5
V ON/OFF (V)

4 CTL discharged at 4 µA

CTL discharged at 12 µA
3
t
2
A Enlargement of section B
1 V TL CTL discharged at 4 µA

0.5 sec/div
t
t ON t OFF t ON t OFF
a to b : PWM pulse output is High.
b : The point where overcurrent
is detected.
SW ON SW OFF Output pulse shutdown region
b to c : PWM pulse output is Low.

Rev.3, Jul. 2002, page 31 of 31

HA16107P/FP, HA16108P/FP

Error Amplifier Characteristic

60

Open Loop Gain AVO (dB)

40 0

Phase Change φ (deg)

45
AVO
φ
20 90

135

0 180
10 k 30 k 100 k 300 k 1M 3M 10 M 30 M 100 M
Input signal frequency fIN (Hz)

Examples of Drooping Characteristics of Power Supplies Using these ICs

5.0
ON
Normal operation Pulse by pulse
VOUT (DC) (V)

Current limiter operation

Latch state here
2.5 A
B A Heavy load
B Light load
OFF

0 1 2 3 4
IOUT (DC) (A)
HA16107 (Latch shut-down)

5.0
ON Pulse by pulse
VOUT (DC) (V)

OFF Current limiter operation

A
2.5
B A Heavy load
B Light load

0 1 2 3 4
IOUT (DC) (A)
HA16108 (Intermittent operation by means of ON/OFF timer)

Rev.3, Jul. 2002, page 32 of 32

 HA16107P/FP, HA16108P/FP

Operating Circuit Example

• Flyback Transforrmer Application Example

(IC Vref used as system as reference voltage)
Schottky barrier diode
Bridge Diode Start-up Resistor El-30
HRP 24
140 V Trans former
+

82 kΩ
1W 2SK1567 40T 6T + 5V
470 µF OUTPUT
51 Ω −

HZP 16 −

1.5 Ω 23T
RFI 3W
HRP 32
Current Sense
18.9 V
FILTER +
50 V
22 µF OVP
HZP 16 Detector

AC
VIN TL Timerlatch
INPUT
Capacitor
QCLM

−++

16
1

+ 16 V
1 µF
16
µA
4 µA

E/O −
PWM Comparator
VC

OUT
140

330
OUT

µA

15
110 Ω
2

kΩ
L
H
ON/OFF Latch
(V TH= 7V)

UVL1
VE

P{ulse by pulse latch

S
R Q
VL VH

CL(+) IN(−)
QS
QR

Error amp.

14
3

Current
Sense 510 kΩ
circuit
generation
voltage
reference
Zener type
6.45 V
UVL1&UVL2

L.P.F. 51 Ω VE NC 68
Phase kΩ
13
4

Vref
limiter
Current

UVL1
Triangle wave

4700 pF Comp.
VIN
O
P
V
ST

CL(−)
L
H
UVL2

12
5

4V 5V

GND
34 V

27 kΩ IN(+)
11
6

Vref

3.225 V
RT1
UVL2

470 pF
ST
10

Soft Start
7

− Cap.
3.4 V 10 µA

fosc = 100 kHz, CT

1 µF +16 V
Dumax = 50%
8

Vref 33kΩ 33kΩ

RT2
Frequency,
Max, Duty 27 kΩ
HA16107P/FP + −
Setting 1 µF
16 V
6.45 V

Rev.3, Jul. 2002, page 33 of 33

 Bridge diode Power thermister

+
AC 200 V
INPUT − 100 µF
DFG1C8 HRW26F 47 µH
HA17431P

Rev.3, Jul. 2002, page 34 of 34

330 Ω +
RB
0.3 φ + 16 V 3.3 kΩ
1 W 82 kΩ 50 T 0.5 φ
8T − 1000 µF
(Start-up resistor) 1.8 kΩ + DC
*
OUT
HA16107P/FP, HA16108P/FP

−
10 kΩ
• Forward Transformer Application Example

3.3 µF (5 V)
4.7 kΩ
+ 0.3 φ + B
Timer latch 1 µF − (Soft start 1 µF 0.47 µF 50 T 0.5 φ 50 V
capacitor capacitor) − + − 8T – 22 µF
Secondary error amplifier −
+ *
16 15 14 13 12 11 10 9
TL E/O IN NC IN ST Vref
(−) (+)
HZP16
HA16107P/108P 13 kΩ TLP521
2SK1567
CL
VOUT (+) RT1 CT CT2
1 2 3 4 5 6 7 8 51 Ω
* Bifiler transfomer core size
3W
13 kΩ EI-30 equivalent product
470 pF 1.5 Ω (Current sense)
110 Ω

(Current sense filter)

4700 pF 51 Ω
 HA16107P/FP, HA16108P/FP

• When OVP signal is inserted at CL(+) pin

VIN

RB

OVP detector

VIN OUT

CL(+)

TL
+

1 µF

When the OVP detection Zener diode turns on, latch shutdown of the output
is performed after the elapse of the time determined by the capacitance
connected the TL pin.

Rev.3, Jul. 2002, page 35 of 35

HA16107P/FP, HA16108P/FP

Application

1. Use of Error Amplifier for Flyback Transformer Primary-Side Control

In this example, the fact that the transformer winding ratio and voltage ratio in Figure 1.1 are mutually
proportional is made use of in a flyback transformer type AC-DC converter. As fluctuation of output
voltage V2 also appears in IC power supply voltage V3, this is divided by a resistance and amplified by an
error amplifier. An advantage of this method is that a photocoupler need not be used, making it possible to
configure a power supply with a small number of parts (this example cannot be applied to a forward
transformer).

•V1(input voltage)
Commercial AC input
Output
Start-up N1
resistance
V3(IC power supply voltage) To switch element
N2 V2(output voltage)

N3
R1 R4 C1
R3 Flyback
14 − R2 1
transformer × V3 = Vref
15 E/O R1 + R2 2
R2 +
Error amp. N3
11 Where V3 = × V2,
2.5V N2

Figure 1.1 Error Amplifier Peripheral Circuitry Diagram

<Determining External Constants around Error Amplifier>

1. Detrrrmining DC Characteristics
In Figure 1.1, the relational expression in the box is satisfied, and therefore parameters are determined
based on this. The absolute value of the number of transformer windings is determined based on the
equation N1:N2:N3 = V1:V2:V3, taking primary inductance into consideration.
Next, IC operating voltage V3 is made around 11V to 18V, taking the UVL voltage into consideration.
If V3 is too large, the power consumption of the IC will increase, causing heat emission problems. If V3
is too small, on the other hand, there will be problems with defective power supply start-up.
2. Determining Error Amplifier Gain vs. Frequency Characteristic
Taking the configuration in Figure 1.1, the error amplifier gain characteristic with respect to fluctuation
of output voltage V2 is as shown in Figure 1.2.

G1
Gain G (dB)

G2
R6 ≠ 0
R6 = 0
f1 fAC f2 fOSC Frequency f (Hz)

Figure 1.2 Error Amplifier Characteristic

Rev.3, Jul. 2002, page 36 of 36

 HA16107P/FP, HA16108P/FP
In Figure 1.2, the parameters are given by the following equations.

Gain
G1 = V3/V2 × R3/R1
G2 = V3/V2 × R4/R1
Corner frequencies
f1 = 1/(2π C1 R3)
f2 = 1/(2π C1 R4)
Where R3>>R4 (10:1 or above)
G1 is made around 30 to 50 dB, taking both regulation and stability into consideration.
f1 is made a lower value than commercial frequency ripple fAC, thus preventing hunting (a system instability
phenomenon).
Next, G2 is set to 0 dB or less as a guideline, so that there is no gain in IC operating frequency fOSC (several
tens to several hundreds of kHz). f2 should be set to a value that is substantially smaller than fOSC, and that is
appropriate for the power supply response speed (several kHz). In the case of a bridge type rectification
circuit, the commercial frequency ripple is twice the input frequency (with a 50 Hz commercial frequency,
fAC = 100 Hz).

2. External Constant Design for Current Detection Section (HA16107, HA16108, HA16666)

In the above IC models, which incorporate a current detection function, a low-pass filter such as shown in
Figure 2.1 must be inserted between switch element current detection resistance RCS and the current
detection pin of the IC.

140V
Input voltage VB

Floating capacitance
CX Output

From PWM
output pin
of IC Switch element
power MOS FET
To current
detection pin ID
of IC RA V11
V12 Current detection resistance

RB RCS
CA
Several hundred mΩ
to several Ω

Filter (LPF)

Figure 2.1 Current Detection Circuit

Rev.3, Jul. 2002, page 37 of 37

HA16107P/FP, HA16108P/FP
The reason for this is that, when the switch element is on in each cycle, there is an impulse current
associated with charging of transformer floating capacitance CX, and IC current detection malfunctions (see
Figure 2.2).

VTH
V11

V12

Figure 2.2 Current Detection Waveform

<Setting Numeric Values>

If the switch element current to be detected is designated ID, and the current detection resistance RCS, then
the following equation is satisfied using the parameters in Figure 2.1.

ID × RCS = ((RA + RB)/RB) VTH

VTH is the detection level voltage of the IC (240 mV in the case of the HA16107, for example). RA and RB
are set to values on the order of several hundred Ω to several kΩ, so that RCS is not affected.
Next, the filter cutoff frequency is set according to the following equation.

fC = 1/(2π CA (RA/RB))
fC can be found with the following guideline, using IC operating frequency fOSC, power supply rating on-
duty D, and power MOS element turn-on time tON.

fosc/D ≤ fC ≤ 1/(100 × tON)

Value 100 in the above equation provides a margin for noise, ringing, and so forth.

<Actual Example>
In an SW power supply using an HA16107, with a 100 kHz operating frequency and a D value of 30%, the
relevant values were as follows: VB = 140 V, CX = 80 pF, tON = 10 ns. Thus, when RCS = 1 Ω, the V11 level
peak value reaches the following figure.

V11 (peak) = RCS × ID peak

= RCS × (VB × CX)/tON
= 1Ω × (140 V × 80 pF)/10 ns
= 1.12 (V)
A filter with the following constants was then inserted.

RA = RB = 1 kΩ, CA = 1000 pF
At this time, the detectable drain current is 0.48 (A), and the filter cutoff frequency is 318 (kHz). Note that
increasing a filter time constant is effective against noise, but if the value is too large, error will arise in the
switch element current detection level.

Rev.3, Jul. 2002, page 38 of 38

 HA16107P/FP, HA16108P/FP

3. IC Heat Emission Problem and Countermeasures (HA16107 Series, HA16114 Series)

While the above ICs can directly drive a power MOS FET gate, if the method of use is not thoroughly
investigated, there will be a tendency for the gate drive power to increase and a problem of heat emission
by the IC may occur.
This section should therefore be noted and appropriate measures taken to prevent this kind of problem.

1. Power MOS FET Drive Characteristics

When power MOS FET drive is performed, in order to lower the on-resistance sufficiently, overdrive is
normally performed with a voltage considerably higher than 5 V, for example, such as the 15 V power
supply voltage of the IC.
At this time, the power that should be supplied from the IC to the power MOS FET is determined by
gate load Qg in Figure 4.2.
2. IC Heat-Emission Power Calculation (Figure 4.2)
The power that contributes to IC heat emission is calculated by means of the following equation.
Pd = VIN IQ + 2Qg VIN f
Where VIN : Power supply voltage of IC
IQ : Operating current of IC (unloaded)
Qg : Above-mentioned gate load
f : Operating frequency of IC
The coefficient, 2, indicates that gate discharging also contributes to heat emission.

4. Power MOS FET Gate Resistance Design (HA16107 Series, HA16114 Series)

There are the following three purposes in connecting a gate resistance, and the circuit is generally of the
kind shown in Figure 4.1.

(1) To suppress peak current due to gate charging

(2) To protect IC output pins
(3) To provide drive appropriate to power MOS FET input characteristics

DG To transformer

OUT Power
RG1 RG2 MOS FET
IC
output pin
CS
RCS

Figure 4.1 Gate Drive Circuit

Rev.3, Jul. 2002, page 39 of 39

HA16107P/FP, HA16108P/FP
This gate resistance RG is given by the following equation.
RG = (VG/IG) – (VG × tON)/Qg, RG = RG1 + RG2
IG : Gate input peak current
VG : Gate drive voltage wave high value (equal to power supply voltage of IC)
tON : Power MOS FET turn-on time
tOFF : Power MOS FET turn-off time
Qg : Gate charge according to Figure 4.2

VDS
VDS VGS
(V) (V)
VGS

Qg (nc)

Figure 4.2 Power MOS FET Dynamic Input Characteristics

Refer to the power MOS FET catalog for information on tON and Qg.
By dividing RG into RG1 and RG2, it is possible for speed to be slowed when the power MOS FET is on, and
increased when off.
Power MOS FET on and off times when mounted, tON’ and tOFF’, are as follows.
tON’ = tON + Qg(RG1 + RG2)/VG
tOFF’ = tOFF + Qg ⋅ RG2/VG
<Actual Example>
When driving a power MOS FET and 2SK1567 with an HA16107, etc.
(RG1 = 100 Ω, RG2 = 20 Ω, VG = 15 V)
tON’ = 70 ns + 36 nc ⋅ (100 Ω + 20 Ω)/(15 V) = 360 (ns)
tOFF’ = 135 ns + 36 nc ⋅ (20 Ω)/(15 V) = 183 (ns)
Generally, the gate resistance values in the case of this circuit configuration are on the order of 100 to 470
Ω for RG1 and 10 to 47 Ω for RG2.

Rev.3, Jul. 2002, page 40 of 40

 HA16107P/FP, HA16108P/FP

Package Dimensions

As of January, 2002
19.20
Unit: mm
20.00 Max
16 9

7.40 Max
6.30
1 8
1.3

1.11 Max
7.62

2.54 Min 5.06 Max

0.51 Min

+ 0.13
2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05

0˚ – 15˚
Hitachi Code DP-16
JEDEC Conforms
JEITA Conforms
Mass (reference value) 1.07 g

As of January, 2002
Unit: mm
10.06
10.5 Max
16 9
5.5

1 8
*0.22 ± 0.05
0.20 ± 0.04

7.80 +– 0.30
0.20
2.20 Max

0.80 Max 1.15

0˚ – 8˚
0.10 ± 0.10

1.27 0.70 ± 0.20

*0.42 ± 0.08
0.40 ± 0.06
0.15

0.12 M
Hitachi Code FP-16DA
JEDEC —
*Dimension including the plating thickness JEITA Conforms
Base material dimension Mass (reference value) 0.24 g

Rev.3, Jul. 2002, page 41 of 41

HA16107P/FP, HA16108P/FP

Disclaimer

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

Sales Offices

Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109

URL http://www.hitachisemiconductor.com/

For further information write to:

Hitachi Semiconductor Hitachi Europe Ltd. Hitachi Asia Ltd. Hitachi Asia (Hong Kong) Ltd.
(America) Inc. Electronic Components Group Hitachi Tower Group III (Electronic Components)
179 East Tasman Drive Whitebrook Park 16 Collyer Quay #20-00 7/F., North Tower
San Jose,CA 95134 Lower Cookham Road Singapore 049318 World Finance Centre,
Tel: <1> (408) 433-1990 Maidenhead Tel : <65>-6538-6533/6538-8577 Harbour City, Canton Road
Fax: <1>(408) 433-0223 Berkshire SL6 8YA, United Kingdom Fax : <65>-6538-6933/6538-3877 Tsim Sha Tsui, Kowloon Hong Kong
Tel: <44> (1628) 585000 URL : http://semiconductor.hitachi.com.sg Tel : <852>-2735-9218
Fax: <44> (1628) 585200 Fax : <852>-2730-0281
URL : http://semiconductor.hitachi.com.hk
Hitachi Europe GmbH Hitachi Asia Ltd.
Electronic Components Group (Taipei Branch Office)
Dornacher Straße 3 4/F, No. 167, Tun Hwa North Road
D-85622 Feldkirchen Hung-Kuo Building
Postfach 201, D-85619 Feldkirchen Taipei (105), Taiwan
Germany Tel : <886>-(2)-2718-3666
Tel: <49> (89) 9 9180-0 Fax : <886>-(2)-2718-8180
Fax: <49> (89) 9 29 30 00 Telex : 23222 HAS-TP
URL : http://www.hitachi.com.tw
Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 6.0

Rev.3, Jul. 2002, page 42 of 42

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.