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Sequential Circuits Problem

The document outlines an assignment to design a finite state machine (FSM) that outputs 'Y' if the last four inputs are either 'abab' or 'baba', and 'N' otherwise. It includes specifications for input and output symbols, building blocks available for the design, and steps to create an abstract Mealy machine, encode symbols, complete the logic network, and verify the implementation using VHDL. Additionally, it requires characterization of the timing of the FSM implementations.

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Shubham Gupta
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28 views2 pages

Sequential Circuits Problem

The document outlines an assignment to design a finite state machine (FSM) that outputs 'Y' if the last four inputs are either 'abab' or 'baba', and 'N' otherwise. It includes specifications for input and output symbols, building blocks available for the design, and steps to create an abstract Mealy machine, encode symbols, complete the logic network, and verify the implementation using VHDL. Additionally, it requires characterization of the timing of the FSM implementations.

Uploaded by

Shubham Gupta
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Assignment: Lets Design an FSM

Madhav P. Desai
February 15, 2016

Implement an FSM with the following specification:


• The set of input symbols is Σ = {a, b}.
• The set of output symbols is Λ = {Y, N }.
The behaviour of the FSM is as follows:
• The FSM outputs a Y at time instant k only if the last 4 inputs were
either

abab
baba

(that is, either x(k) = a, x(k − 1) = b, x(k − 2) = a, x(k − 3) = b or


x(k) = b, x(k − 1) = a, x(k − 2) = b, x(k − 3) = a). Otherwise the FSM
outputs N .
Suppose you are given the following building blocks:
• Inverters, NAND2, NOR2 gates each with a delay of 2 units.
• D-flipflops with clock → q delay of 3 units, set-up time of 2 units and
hold-time of 2 units.

1. Design an abstract Mealy machine (identify a potential set of states and


next-state, output functions) which implements the required behaviour.
2. Encode the input, output and state symbols using binary encoding.
• Try two state encodings: the one-hot encoding and a compact en-
coding using log2 |Q| state variables.
3. Complete the logic network for the FSM based on your encodings. Don’t
forget to add the reset signal. You may assume that the output is a
dont-care when the reset signal is applied.
4. Confirm, using a VHDL model, that your implementations are correct.
Check the following test-case

1
k 0 1 2 3 4 5 6 7 8 9
x reset a b b a b a b a a
y _ N N N N N Y Y Y N

5. Characterize the timing of your FSM implementations (find the minimum


and maximum values of the input to flop, flop to flop, flop to output and
input to output delays).

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