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Top 50 Most Frequently
Asked Interview Questions

Prasanthi Chanda
1. How do you debug a setup violation in a path with a
combinational loop?
Asked in: Apple, NVIDIA, Qualcomm
Answer:
Combinational loop = no flop in the loop → timing can’t
be computed.
STA tools report infinite delay or zero slack depending on
the loop logic.
Debug steps:
1. Trace the loop using report_timing -loops.
2. Identify the feedback path.
3. If valid: insert latch or flop to break the loop.
4. If invalid: fix RTL bug or wrong net connection.
5. Add false path constraint only if the loop is intentional
and non-timing-critical.

2. Explain the role of metal layers in congestion and timing.

Why are higher metal layers used in clock routing?
Asked in: Intel, Google, Texas Instruments
Answer:
Lower layers (M1-M4): Narrow, high resistance → used for
standard cell connections.
Higher layers (M5-M10): Wider, low resistance → used for
long nets, power grid, and clocks.
Clock Routing:
Needs low RC delay and minimal skew/jitter.
Hence, routed on top metal layers, often shielded with GND.
3. If you have a short critical path, but still facing hold
violations at signoff, what could be wrong?
Asked in: Analog Devices, Broadcom
Answer:
Possible reasons:
1. Cross-corner variation: Fast corner has aggressive OCV
derating.
2. Aging effects or IR drop changing cell speeds.
3. Incorrect early-mode constraint setup.
4. Incorrect clock latency modeling or skew modeling.
Fix:
Use late-mode clock latency tuning.
Add RC delay buffers.
Improve clock tree balance.
Re-analyze parasitics.

4. What is cross-talk noise? How does it affect timing and

functionality?
Asked in: Samsung, Micron
Answer:
Crosstalk: Capacitive coupling between adjacent nets.
Causes noise injection → functional failure or glitch.
Can delay or speed up signals, causing setup or hold
violations.
Fixes:
1. Shield nets with GND/VDD.
2. Increase spacing between critical nets.
5. What happens if there’s a negative clock skew? Is it always
bad?
Asked in: ARM, Cadence
Answer:
Negative skew: Capture clock arrives before launch clock.
Can be good for hold, but bad for setup.
Excessive negative skew can cause data to be captured
early → setup violation.
Conclusion:
Negative skew is not always bad. Use it intelligently in
hold fix strategies.

6. How do you calculate setup slack and hold slack using

delay equations?
Asked in: Marvell, Infineon
Answer:
Let:
Tclk: Clock period
Ddata: Data path delay
Dclk: Clock skew (launch - capture)
Tsetup: Setup time of flop
Thold: Hold time of flop
Equations:
Setup slack = Tclk - (Ddata + Tsetup - Dclk)
Hold slack = Ddata - (Dclk + Thold)
Use actual skew numbers (+ve/-ve) to compute.
7. How does multi-bit flip-flop insertion help in physical
design?
Asked in: Apple, Synopsys, Qualcomm
Answer:
Merges multiple single-bit flops into 2-bit, 4-bit, etc.
Reduces clock load → fewer clock tree branches.
Saves power (less switching).
Reduces congestion → fewer clock buffers.
Caution:
Requires timing and placement awareness → grouped FFs
must have similar timing.

8. What happens if you insert too many buffers in a timing

path?
Asked in: MediaTek, Google
Answer:
Good side:
Controls slew.
Fixes transition violations.
Helps drive large loads.
Bad side:
Increases delay and area.
Adds power consumption.
Can increase hold risk in FF corners.
Always perform buffer insertion with timing analysis.
9. Describe the impact of ECO (Engineering Change Order)
on timing closure and how you handle it.
Asked in: Texas Instruments, Broadcom, Intel
Answer:
ECO changes post sign-off may:
Break existing timing paths.
Affect clock tree balance.
Cause hold/setup violations due to changes in logic
depth or load.
Fix steps:
1. Re-run incremental STA.
2. If path is impacted, use cell resizing or re-buffering.
3. Update SPEF/RC if physical layout changed.
4. Re-verify SI and IR drop.
5. Avoid full re-run → use ECO-friendly flows (e.g.,
Conformal ECO, IC Compiler II ECO mode).

10. What is useful skew? How is it leveraged in timing

optimization?
Asked in: Intel, Apple, Cadence
Answer:
Useful skew is the intentional delay added to clock paths to
improve timing (especially setup).
If setup slack is negative, delaying the capture clock
increases available time for data to arrive.
Usage:
Implemented via clock tree synthesis (CTS) and must ensure
it doesn't degrade hold timing
11. Explain the timing impact of placing a flop near the
launch or capture edge. How does cell location affect setup
and hold?
Asked in: Qualcomm, Google, AMD
Answer:
If the launch flop is far and the capture flop is near →
longer data path, shorter clock path → setup violation
risk.
If the launch flop is near and the capture flop is far →
shorter data path, longer clock path → hold violation risk.
Placement Strategy:
Balance data and clock paths.
Apply clock latency budgeting during placement.
Use data-to-clock path alignment to optimize timing.

12. What’s the effect of high fanout nets on timing, and how
do you handle them?
Asked in: NVIDIA, Synopsys
Answer:
High fanout nets → Large RC delay, high transition,
possible SI noise.
Often appear in reset, enable, or test control signals.
Fix:
Use buffer tree (fanout tree).
Split using H-tree or fishbone topology.
Place sources centrally to balance load.
13. How do you analyze and fix IR drop issues in physical
design?
Asked in: Apple, Micron
Answer:
IR drop = Voltage drop across power rails due to
resistance.
Leads to timing degradation, hold/setup issues, and even
functional failure.
Analysis:
Use RedHawk, Voltus, or PrimeRail tools.
Run EM/IR-aware CTS and routing.
Fix:
Wider metal tracks for PG grid.
More vias between power layers.
Optimize cell spreading to reduce local density.

14. Explain the role of LEF and DEF in the physical design
flow.
Asked in: Cadence, Marvell
Answer:
LEF (Library Exchange Format):
Provides abstract view of cells (height, width, pin locs).
No timing info.
DEF (Design Exchange Format):
Describes actual physical placement and routing of
instances in a block.
Both are crucial for P&R tools to understand the physical
structure and legal placement.
15. In which scenario would you prefer LVT over HVT cells
in timing paths?
Asked in: MediaTek, Infineon
Answer:
LVT (Low Vth): Faster, more leakage.
HVT (High Vth): Slower, less leakage.
Use LVT when:
Fixing setup violations in critical paths.
High-speed designs.
Use HVT when:
Path is non-critical.
Leakage power is a concern.

16. How do you approach timing ECO for hold fixes at

signoff stage without impacting setup?
Asked in: Google, Synopsys
Answer:
ECO = local changes post-signoff.
For hold:
Add delay cells (e.g., AND, OR gates used as buffers).
Use HVT cells to avoid switching power overhead.
Avoid data path changes if possible.
Never touch paths with negative setup slack.
Use incremental STA to verify and converge quickly.
17. Explain the timing impact of placing a flop near the
launch or capture edge. How does cell location affect setup
and hold?
Asked in: Qualcomm, Google, AMD
Solution:
Far launch & near capture: long data path, short clock
path → setup violation risk.
Near launch & far capture: short data path, long clock
path → hold violation risk.
Fix: Optimize placement and clock latency budgeting.

18. How do you fix congestion in physical design at the

global placement stage?
Asked in: Google, Synopsys
Answer:
1. Cell padding: Add spacing between cells.
2. Move macros: Relocate large blocks to reduce blockage.
3. Use congestion-driven placement.
4. Add white space in dense regions.
5. Change floorplan (e.g., flip macro orientation, use
channels).
Tools like Innovus and IC Compiler II provide congestion maps
for visualization.
19. Why is clock tree synthesis (CTS) done after placement
and before routing? Can you explain the implications if
done earlier or later?
Asked in: Qualcomm, NVIDIA, AMD
Answer:
After placement: Because flop locations are fixed → tool
can estimate accurate clock loads and build tree
accordingly.
Before routing: So that routing knows clock tree structure
and doesn’t interfere.
If done earlier:
Clock tree will be non-optimal, incorrect clock
latency/skew.
If done later:
Routing congestion will make CTS harder, may violate
timing or DRC.

20. What are the effects of metal fill on timing and how do
you account for them in physical design?
Asked in: AMD, Synopsys
Answer:
Metal fill is inserted to maintain planarity during CMP
(chemical mechanical polishing).
It adds parasitic capacitance to nearby nets → increases
delay and can affect signal integrity.
Fix:
Use timing-aware metal fill in signoff tools.
Shield sensitive nets with ground fills.
21. Can a path have both setup and hold violations at
different PVT corners? How do you analyze this?
Asked in: Synopsys, NVIDIA, Intel
Yes. It’s very common.
Setup violation → happens at slow-slow (SS), high temp,
high Vt → data is slow.
Hold violation → happens at fast-fast (FF), low temp, low
Vt → data is fast.
Fix strategy:
Fix setup by optimizing data path.
Fix hold by adding delay in fast corner → BUT ensure it
doesn't worsen setup.
Use multi-corner multi-mode (MCMM) analysis in static timing
analysis (STA) tools (e.g., PrimeTime) to verify both
constraints are met.

22. Describe the impact of high fanout nets on timing and

how to address them.
Asked in: NVIDIA, Intel
Answer:
High fanout nets (e.g., resets, clocks, enables) → high
capacitive load → longer delay, higher transition time →
can cause setup/hold violations.
Fix strategies:
1. Buffer tree insertion: Divide the load using buffers or
inverters.
2. Use higher drive strength cells.
3. Split net using hierarchical partitioning.
23. Given a path with setup violation, but the path delay is
already minimal, what other options do you have to fix the
violation?
Asked in: Samsung, Micron
Answer:
If data path delay is already optimized, you can:
1. Decrease clock uncertainty (jitter + skew margin) if
possible.
2. Use OCV (On-Chip Variation) margins more conservatively.
3. Use useful skew (delay capture flop clk).
4. Replace flip-flop with one having lower setup time.
5. Reduce number of logic stages by restructuring logic
(logic optimization).
6. Consider multi-bit flops to reduce clock load (decreases
clock tree delay).

24. What is antenna effect? How do you fix antenna

violations in your design?
Asked in: Intel, Google, Texas Instruments
Answer:
Antenna effect happens during fabrication (plasma etching)
when long metal wires accumulate charge before
connecting to the gate → can destroy gate oxide.
Fix methods:
1. Diode insertion: Add antenna diode between net and
ground → provides charge discharge path.
2. Routing jumps: Break metal continuity; connect at
different metal layers to avoid accumulation.
25. Explain how clock skew can be used beneficially to fix
setup and hold violations. Give examples.
Asked in: Samsung, Micron
Answer:
Clock skew is the difference in arrival time of the clock at
different sequential elements.
For setup violation:
If launch flop's clk is late and capture flop's clk is early →
data has less time to reach → setup violation.
Skew the capture clock later (intentionally add delay) →
gives more time for data to reach → setup improves.
For hold violation:
If launch flop's clk is early and capture flop's clk is late →
data may arrive too soon at capture flop → hold
violation.
Skew the capture clock earlier → data arrives after the
clock → hold is fixed.
Example:
Setup Slack = Data Path Delay - (Clock Period - Skew)
Hold Slack = (Skew) - Data Path Delay
Adjust skew to optimize setup or hold accordingly. But
remember: too much skew is risky, may cause race conditions.
26. How do hold violations behave with process-voltage-
temperature (PVT) corners, and how do you fix a hold
violation considering worst-case scenarios?
Asked in: Intel, AMD, NVIDIA
Answer:
Hold time violations are most critical in fast-fast (FF), low
voltage, low temperature corners, where the data path
becomes too fast.
At this corner, the clock delay is small (fast clk) and data
propagates faster due to faster gates → possible hold
violation.
Fix strategies:
1. Add delay buffers/inverters in the data path.
2. Use lower Vt cells in the clock path to speed up clock (but
this is less common, more often data path is delayed).
3. Use higher Vt or larger-sized cells in the data path to
slow it down.
4. Add delay chains if needed.
5. Avoid modifying flip-flop placement — target cell-based
timing fixes instead of placement fixes.
Key Point: Always fix hold in FF, 0.81V, 0°C type corners —
the fastest scenario is most dangerous for hold.
27. What are PBA and GBA in Static Timing Analysis? When
do they differ and how does it affect signoff?
Asked in: Apple, Qualcomm, Cadence
Answer:
GBA (Graph-Based Analysis): Fast approximation,
pessimistic. Analyzes all paths between launch and
capture points assuming all paths are sensitizable.
PBA (Path-Based Analysis): Accurate, realistic. Only
considers truly sensitizable paths based on logic
conditions.
Differences:
GBA is used for early timing estimation and quick
convergence.
PBA is used for final signoff as it gives less pessimistic
results.
Impact:
GBA may falsely flag violations.
PBA helps in timing ECOs, avoiding unnecessary changes.

28. In a large SoC, how do you handle timing closure in

hierarchical top-down design flows?
Asked in: Intel, NVIDIA, AMD
Answer:
Use interface timing models (ITMs) or abstract views
(black-box or grey-box models).
Top-level STA uses block-level constraints with derived
clocks, IO delays, and mode combinations.
29. How do you fix negative slack that varies across PVT
corners without overdesigning?
Asked in: Synopsys, Broadcom, Marvell
Answer:
Identify corner-specific violations using corner-aware STA.
Apply corner-specific ECOs:
Insert LVTHVT mix cells depending on the corner.
Use voltage-aware placement.
Add selective buffering for critical corner only.
Best Practice:
Use voltage binning and adaptive body biasing (if
technology allows).
Avoid blind fixes that degrade other corners.

30.Explain the concepts of OCV, AOCV, and POCV. When

should each be used?
Asked in: Texas Instruments, AMD, Qualcomm
Answer:
OCV (On-Chip Variation): Worst-case margin for all cells
globally. Very pessimistic.
AOCV (Advanced OCV): Derates based on path depth and
distance. Less pessimistic.
POCV (Parametric OCV): Statistical, derates based on actual
process/voltage/temperature characteristics and spatial
distribution.
Usage:
OCV: Used in legacy flows or for conservative designs.
AOCV: Balances accuracy with runtime.
POCV: Best for advanced nodes (≤7nm)
31. Describe the full signoff flow for a high-performance
block in advanced FinFET technology (5nm/7nm).
Asked in: Google, Apple, ARM
Answer:
1. Pre-CTS STA: Check data paths, insert ideal clock.
2. CTS Planning: Clock tree topology, balancing skew &
latency.
3. Post-CTS STA:
Multi-corner-multi-mode (MCMM) analysis.
SI, PBA checks.
4. Final Optimization:
Use of CCOpt, IR-aware routing, AOCV/POCV tuning.
5. Signoff Checks:
Timing closure (setup, hold, WNS, TNS, FEP).
IR drop, EM, signal integrity.
LVS, DRC using Calibre or Pegasus.
6. Tapeout Prep:
GDS export, fill, antenna fix, ECO netlist
backannotation.
32. How do you handle EM/IR drop issues during post-route
signoff in sub-7nm designs?
Asked in: Apple, MediaTek, Intel
Answer:
EM (Electromigration): Caused by high current densities
→ metal atom migration → signal opens.
IR drop: Voltage drop across power grid due to resistance.
Fixes:
Increase metal width and via count (multi-cut and stacked
vias).
Add straps, power tap cells, and grid enhancement.
Use dynamic IR analysis tools (e.g., Ansys RedHawk,
Voltus).
Implement EM-aware cell spreading or dynamic power-
aware placement.
At advanced nodes:
Must consider local temperature variations, activity
factor, and stress-driven metal reliability.
33. What are false paths and multi-cycle paths? How do you
define and verify them in STA?
Asked in: AMD, Google, Synopsys
Answer:
False Path: A path that never toggles logically (e.g., from
a reset to a data bus).
Multi-Cycle Path (MCP): Path that is allowed to take >1
cycle to complete data transfer.
In STA:
Defined using:

set_false_path -from X -to Y

set_multicycle_path 2 -setup -from A -to B
set_multicycle_path 1 -hold -from A -to B

Verification:
Cross-check with RTL designers.
Use waveform-based simulation (with stimulus) and CDC
tools.
34. How do you debug and fix max transition violations in
post-route timing closure?
Asked in: NVIDIA, Broadcom, Qualcomm
Answer:
Causes: Long wire, insufficient buffering, high fanout.
Impacts: Setup degradation, signal integrity noise,
reliability issues.
Fixes:
Insert buffers or inverters (timing-aware).
Use sizing (increase drive strength).
Perform layer promotion (route on higher metal layers to
reduce RC).
Re-run clock reconvergence pessimism removal (CRPR) to
reduce pessimism in paths near clock sources.

35. Explain how you handle asynchronous clock domain

crossings (CDC) in physical design.
Asked in: Intel, Marvell, Cadence
Answer:
CDC occurs when data transfers between different clock
domains.
Risks: Metastability, data loss, timing failures.
Best Practices:
Use 2-stage synchronizer flops for control signals.
For data:
Use asynchronous FIFOs.
Apply handshake logic or valid-ready protocols.
36. What is metal fill and how can it affect timing and
signal integrity?
Asked in: TSMC, TI, GlobalFoundries
Answer:
Metal fill: Dummy metal added to meet metal density
requirements of the foundry.
Required for planarization, etching consistency, and CMP.
Impact on Timing:
Parasitic coupling between signal wires and fill can:
Increase capacitance.
Delay signal transitions.
Fix:
Use timing-aware metal fill (tools like Calibre xRC or
StarRC).
Introduce shielding and increased spacing to mitigate
crosstalk.
Adjust fill post-route and re-run extraction and STA.
37. How do you handle cross-talk noise in post-route
signoff, and how does it affect hold/setup analysis?
Asked in: Apple, Samsung, Broadcom
Answer:
Crosstalk = Capacitive coupling between neighboring nets
(aggressor-victim).
Affects:
Hold: Noise-induced early arrival.
Setup: Noise-induced delay → late arrival.
Fix Methods:
Shielding: Add ground/VDD lines between aggressor-
victim nets.
Spacing: Increase spacing to reduce coupling capacitance.
Layer movement: Route on different layers.
Re-buffering or reduce load/fanout.
Tool Insight:
Perform Noise-aware STA using tools like PrimeTime-SI,
Tempus-SI.
38. What are antenna violations? How do you fix them
without impacting timing?
Asked in: TSMC, Apple, Synopsys
Answer:
Antenna Effect: Charge accumulation on long metal wires
during fabrication → damages gate oxide.
Detection:
Found in LVS/DRC checks during post-route signoff (using
Calibre/Pegasus).
Fixes:
Diode Insertion: Route-to-diode path to drain charge.
Layer Jumping: Early VIA up/down to connect layers and
reduce antenna ratio.
Wire Segmentation: Break wire, connect to intermediate
vias or gates.
Without timing impact:
Prefer diode insertion over rerouting.
Use non-critical nets for antenna fixes.
39. How do you manage congestion hotspots without
violating design rules or degrading timing?
Asked in: Apple, Nvidia, Broadcom
Answer:
Congestion: Area where routing demand > routing
resources.
Causes:
High fanout nets, poorly placed macros, tight standard
cell rows.
Solutions:
1. Macro Re-orientation or Spreading: Space for channels.
2. Cell Padding: Extra spacing to prevent pin overlaps.
3. Layer Promotion: Use higher metal layers (e.g., M6+).
4. Track Assignment Tuning: Avoid blockages in M1–M3
layers.
5. Pre-routing analysis: Use congestion map before CTS.
Without timing hit:
Only reroute non-critical nets.
Avoid changes near timing-critical paths unless absolutely
needed.
40. How does thermal variation impact STA, and how do
you model thermal-aware timing analysis in PD flow?
Asked in: Google, AMD, MediaTek
Answer:
Thermal variation affects:
Cell delays (increased resistance in interconnects).
Threshold voltage (V_th) drift.
Leakage power (increases exponentially with
temperature).
Timing Variation:
Need temperature-aware libraries (.lib) at various corners
(e.g., SS_125C, TT_85C).
Localized heating → non-uniform delay spread.
Fixes:
Use thermal map overlays with P&R tools (like Innovus +
RedHawk).
Co-optimize floorplan, power grid, and cooling zones.
Run temperature-aware STA (with tool-integrated
localized temperature profiles).
41. How do you implement DVFS (Dynamic Voltage and
Frequency Scaling) in PD, and how does it affect timing and
physical closure?
Asked in: Google, Apple, Samsung
Answer:
DVFS = Power management technique to switch between
V/f domains dynamically.
PD Challenges:
Multiple voltage domains → requires level shifters.
Clock trees must support multiple frequencies.
IR drop varies by voltage mode → more complex signoff.
Key Components:
Define power domains with create_power_domain.
Place isolation cells, level shifters, and retention flops.
Perform mode-aware IR/EM/timing analysis.
Pro tip: Use corner-based voltage scaling libraries, and
simulate both low-V and high-V corners separately.

42. Explain the interaction of machine learning with physical

design flows. What problems are being solved using ML
today?
Asked in: Google (TPU team), NVIDIA (DL accelerators)
Answer:
Modern tools like Cadence Cerebrus, Synopsys DSO.ai use ML
to:
Predict optimal floorplans (block placements, macro
orientations).
 Automate PPA tradeoff decisions (timing, area, leakage).
Learn from historical design data and improve over
iterations.
ML Use Cases:
Routing congestion prediction.
Clock tree skew optimization.
EM-aware net selection for special routing.
Tools train models on millions of design iterations, saving
weeks of manual tuning.

43. How do you handle IR drop in hierarchical vs flat design

flows?
Asked in: Intel, Qualcomm, Broadcom
Answer:
Flat flow: Full-chip IR drop analysis with all blocks visible.
Pros: Accurate modeling of shared grid and bump
pads.
Cons: Huge runtime and memory.
Hierarchical flow:
Block-level IR analysis done independently with
assumed constraints (like max current draw).
Top-level IR includes macro-level vias and power ring
planning.
Fix Strategy:
Add more vias (VIA ladders, VIAs under std cells).
Use metal fill with connection to power rails.
Switch to higher-width metal (M6–M8) for straps.
44. What are the key DRC challenges in 5nm and below, and
how do you prevent them in P&R?
Asked in: Apple, TSMC, Samsung
Answer:
5nm and lower nodes introduce:
FinFET layout restrictions (grid-based).
EUV-specific DRCs (mask coloring, 1D design).
Min/Max spacing, via enclosures, multi-patterning (MP).
Prevention Tips:
Use ECO-friendly cell libraries compliant with MP rules.
Enable in-design DRC (DRC-aware placement/routing).
Use coloring-aware routers (Cadence Innovus, Synopsys
ICC2).
At these nodes, DRC isn't post-layout — it's baked into every
stage of the P&R.

45. Explain the concept of glitch power. How do glitches

impact power estimation in PD?
Asked in: Google (TPU), Apple, AMD
Answer:
Glitch power = Power due to unnecessary toggling before
final value settles.
Happens when signals arrive at different times → creates
temporary logic instability.
Impacts:
Increases dynamic power (especially in deep combinational
paths).
Not captured in static toggle rate estimates.
46. How do you handle timing ECOs in a late-stage PD flow
without violating LVS/DRC and preserving PPA?
Asked in: Synopsys, AMD, Marvell
Answer:
Timing ECOs at post-route stage must:
Not change cell rows, macros, or legal pin positions.
Avoid new vias/tracks that violate DRC.
Types:
Cell swap (e.g., INVX1 → INVX2)
Cell move (to reduce wire length/skew)
Buffer insert/remove
Workflow:
1. Use ECO-friendly netlist generation (PrimeTime ECO
mode).
2. ECO placement with physical-aware timing tools (Tempus
ECO, IC Compiler II ECO).
3. Incremental routing & in-design DRC/LVS recheck.
Rule: ECOs should be incremental, timing-driven, and signoff-
clean.
47. How do you optimize power grid design in a design with
multiple voltage islands and stacked dies (2.5D/3DIC)?
Asked in: Google (TPU team), AMD, Intel
Answer:
3DIC and stacked dies introduce complex power delivery
challenges.
Power Grid Strategy:
1. Multi-voltage Domains:
Each island has individual power rings and dedicated
IR drop targets.
Level shifters and isolation logic powered by a shared
reference domain.
2. Power Grid Mesh Design:
Uniform mesh for each island → connected via C4
bumps, TSVs, or RDLs.
Use non-overlapping metal layers to minimize
crosstalk and shorts.
3. Inter-die Power Planning:
Map C4 bump and TSV locations early in floorplan.
Assign high-current nets to low-inductance TSVs or
multi-drop bumps.
4. Voltage Drop Co-Simulation:
Simulate die-to-die IR drop using co-simulation tools:
Ansys RedHawk + Cadence Voltus-Fi + TSV/SPICE
models.
Voltage stack requires careful multi-die IR planning, cross-
power-domain constraints, and floorplan-driven TSV planning.
48. What techniques are used in modern clock mesh design,
and when is it preferred over traditional H-tree CTS?
Asked in: Apple (CPU team), NVIDIA, Intel
Answer:
Clock mesh = A grid-like clock distribution network with
massive redundancy.
When to Use:
High-frequency CPU/GPU cores.
Ultra-low skew and high tolerance to variation are
needed.
Key Features:
Redundant short paths reduce clock skew and jitter.
Better resistance to EM, IR, and local variation.
Excellent for voltage-droop tolerance.
Techniques:
1. Hybrid Mesh + Tree:
Use H-tree → mesh leaf insertion points.
Mesh connects local regions; H-tree connects global
branches.
2. Mesh Cell Design:
Use balanced drive strengths.
Often use custom clock buffers with skew
compensation logic.
3. Active Clock Deskewing:
PLLs/DLLs dynamically adjust skew in high-end
meshes.
49. Explain the impact of metal fill on parasitics and how it
is addressed during signoff timing.
Asked in: Intel, Synopsys, Marvell
Answer:
Metal fill (dummy fill) is used to meet planarity (CMP) and
density rules, but:
Side Effect: Creates coupling capacitance → increases net
parasitics
Affects: clock nets, critical data paths, SI
Solutions:
1. Fill-Aware Extraction:
Use extraction tools like StarRC, Quantus in fill-aware
mode:
2. Fill Shape Optimization:
Use "smart fill" (non-uniform spacing, same-net
shielding).
Do not insert fill near high-speed nets (opt for
exclusion zones).
3. Dummy Fill Shielding:
Assign dummy fill to same net as aggressor/victim to
reduce coupling.
4. Post-Fill STA Signoff:
Perform final signoff timing with fill parasitics.
Expect WNS/TNS degradation after fill → rebuffering
or margining needed.
Timing degradation due to metal fill must be preemptively
margin-adjusted in pre-fill timing corners.
50. What are the techniques used to optimize via
redundancy and DRC-clean routing at advanced nodes (e.g.,
3nm)?
Asked in: Apple, TSMC (design enablement team), Intel

Answer:
At 3nm, routing is highly constrained:
Via size comparable to metal pitch
Higher EM and yield risks → via redundancy is critical
Solutions:
1. Auto via duplication during routing:
Tools insert multi-cut via or double via:
2. Routing Grid-Aware Via Selection:
Adjust routing grid so vias land on DRC-clean sites.
Prevent DRC with diagonal or off-grid via placement.
3. Post-Route Optimization:
Use via optimization engines in ICC2, Innovus:
Improve DRC scores, EM robustness
Maintain timing (slack-aware via selection)
4. Manufacturing-Aware Routing:
Use TSMC/Samsung PDK rules for via enclosures,
spacing
Tools support "DRC+ routing rules" (double-
patterning, self-aligned vias)
5. Redundant Via Checkers:
Use DRC checkers for redundant via coverage:
Via planning is not an afterthought at 3nm — it’s a core
signoff requirement.
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