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Solution Key Week 1 Application Assignment

The document outlines an assignment to design a 2-bit full adder using logic gates, providing a truth table and a schematic for comparison. It includes boolean equations for the outputs and instructions for implementing a specific logic equation using a Programmable Logic Array (PLA) and a Look-Up Table (LUT). Additionally, it requires explanations for the design choices made in the implementation.

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qamar4503117
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112 views6 pages

Solution Key Week 1 Application Assignment

The document outlines an assignment to design a 2-bit full adder using logic gates, providing a truth table and a schematic for comparison. It includes boolean equations for the outputs and instructions for implementing a specific logic equation using a Programmable Logic Array (PLA) and a Look-Up Table (LUT). Additionally, it requires explanations for the design choices made in the implementation.

Uploaded by

qamar4503117
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Solution Key - Week 1 Application

Assignment:
Mission 001

1. Using only logic gates, design a 2-bit full adder with carry. Here is a partial truth
table for the circuit.

INPUTS OUTPUTS
A0 A1 B0 B1 Ci S0 S1 Co
0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0
0 1 0 0 0 0 1 0
1 0 1 0 0 0 1 0
0 1 0 1 0 0 0 1
0 1 0 0 1 1 1 0
1 0 1 0 1 1 1 0
1 1 1 1 1 1 1 1

Where A and B are inputs, Ci is carry in, Si is output and Co is carry out.

Draw a schematic showing the gate interconnections. Include either a boolean equation
or an explanation of your design that matches the schematic you submit.

➤Solution:

Correct/Possible Boolean Equation(s)


S0 = A0 XOR B0 XOR Cin
S1 = A1 XOR B1 XOR C0out where C0out = (A0 AND B0) OR
(Cin AND ((A0 XOR B0)))
Co = (A1 AND B1) OR (C0out AND ((A1 XOR B1)))

A0 XOR B0 could be represented as (A0 OR B0) AND NOT(A0


AND B0), among other equivalent expressions.
Schematic for Learners to Compare Against
2. Show how the logic equation (A AND NOT(B)) OR (C AND NOT(D)) can be implemented
using the following:

A. The PLA shown here:


B. The LUT shown here:

RAM CONTENTS
Address Output Data
A B C D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Be sure to include the PLA fuse pattern and the contents of the LUT. Also provide an
explanation for your design choices.
➤Solution:

Correct PLA fuse pattern for Learners to Compare


Against (below)

Correct LUT contents

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