COURSE PLAN (THEORY)

Acadeic Year: 2024-2025

University : ANNA UNIVERSITY CHENNAI
Regulation : 2021
Degree : B.E
Programme : ELECTRONICS AND COMMUNICATION ENGINEERING

Semester: 5
Course Code: EC3552
Course Title: VLSI AND CHIP DESIGN
Faculty Name: 9104206-R.NAGADEEPA
Faculty Ass. Prof./ECE
Designation:
COLLEGE VISION & MISSION

VISION To be one of the leading and preferred engineering colleges in education, research and ethics,
and achieve greater recognition for our efforts to make the world look to us for technology for
future trends and innovations.
MISSION 1 To develop high-quality technical education and technocrats with a sound grip on basic
engineering principles, technical, and managerial skills.
MISSION 2 To innovate research capabilities, and exemplary professional conduct to lead and to use
technology for the progress of humanity.
MISSION 3 To adapt themselves to changing technological conditions with the highest ethical values.

DEPARTMENT VISION & MISSION

VISION To produce Electronics and Communication Engineers capable of generating a knowledge

economy with social responsibility.
MISSION. 1 To Equip the students with the current trends and latest technologies in the field of Electronics
and Communication Engineering to make them technically strong and ethically sound.
MISSION. 2 Constantly motivate the students and faculty members to achieve excellence in Electronics
and Communication Engineering and Research & Development activities.
MISSION. 3 Ideate and implement interdisciplinary projects and foster continuous learning in association
with students and colleagues across disciplines of the institute.
MISSION. 4 Collaborate with academia, industries, organizations and professional bodies for training,
consultancy and research.

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PROGRAMME EDUCATIONAL OUTCOMES ( PEOs )

PEO. 1 To provide the students with a strong foundation in the required sciences in order to pursue studies
in Electronics and Communication Engineering.
PEO. 2 To gain adequate knowledge to become good professional in electronic and communication
engineering associated industries, higher education and research
PEO. 3 To develop attitude in lifelong learning, applying and adapting new ideas and technologies as their
field evolves.
PEO. 4 To prepare students to critically analyze existing literature in an area of specialization and ethically
develop innovative and research oriented methodologies to solve the problems identified.
PEO. 5 To inculcate in the students a professional and ethical attitude and an ability to visualize the
engineering issues in a broader social context.

PROGRAMME OUTCOMES ( POs )

PROGRAMME OUTCOMES ( POs )

Engineering knowledge :
PO1 Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering
specialization to the solution of complex engineering problems.
Problem analysis :

PO2 Identify, formulate, review research literature, and analyze complex engineering problems reaching
substantiated conclusions using first principles of mathematics, natural sciences, and engineering
sciences.
Design/development of solution :

PO3 Design solutions for complex engineering problems and design system components or processes that
meet the specified needs with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations.
Conduct investigations of comp :
PO4 Use research-based knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.
Modern tool usage :

PO5 Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools
including prediction and modeling to complex engineering activities with an understanding of the
limitations.
The engineer and society :
PO6 Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and
cultural issues and the consequent responsibilities relevant to the professional engineering practice.
PO7 Environment and sustainability :
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 Understand the impact of the professional engineering solutions in societal and environmental contexts,
and demonstrate the knowledge of, and need for sustainable development.
Ethics :
PO8 Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice
Individual and team work :
PO9 Function effectively as an individual, and as a member or leader in diverse teams, and in
multidisciplinary settings.
Communication :

PO10 Communicate effectively on complex engineering activities with the engineering community and with
society at large, such as, being able to comprehend and write effective reports and design documentation,
make effective presentations, and give and receive clear instructions.
Project management and finance :

PO11 Demonstrate knowledge and understanding of the engineering and management principles and apply
these to one?s own work, as a member and leader in a team, to manage projects and in multidisciplinary
environments.
Life-long learning :
PO12 Recognize the need for, and have the preparation and ability to engage in independent and life-long
learning in the broadest context of technological change.

PROGRAMME SPECIFIC OBJECTIVES ( PSOs )

PSO. 1 Design, develop and analyze electronic systems through application of relevant electronics,
mathematics and engineering principles
PSO. 2 Design, develop and analyze communication systems through application of fundamentals from
communication principles, signal processing, and RF System Design & Electromagnetics.
PSO. 3 Adapt to emerging electronics and communication technologies and develop innovative solutions
for existing and newer problems

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COURSE OBJECTIVES

Seri Objective Objectives

al Number.
No.
1 OBJ521 Understand the fundamentals of IC technology components and their characteristics.
2 OBJ522 Understand combinational logic circuits and design principles.
3 OBJ523 Understand sequential logic circuits and clocking strategies.
4 OBJ524 Understand ASIC Design functioning and design.
5 OBJ525 Understand Memory Architecture and building blocks

COURSE OUTCOMES

Seri COURSE BLOOMS

al OUTECOME TOXANOMY COURSE OUTECOMEs
No. NUMBER. LEVEL
1 CO521 K4-UNDERSTAND In depth knowledge of MOS technology
2 CO522 K5-EVALUATE Evaluate Combinational Logic Circuits and Design Principles

3 CO523 K5- EVALUATE Evaluate Sequential Logic Circuits and Clocking Strategies
4 CO524 K3-ANALYZE Analyze Memory architecture and building blocks
5 CO525 K3-ANALYZE Analyze the ASIC Design Process and Testing.

MAPPING OF COURSE OUTCOMES WITH PROGRAMME OUTCOMES & PROGRAM SPECIFIC

OBJECTIVES(PSOs)
4/
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Seri COURSE_OUT PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PSO
al COME NO # # # # # # # # # # # # #1 #2 #3
No. 1 2 3 4 5 6 7 8 9 10 11 12
1 CO521 1 1 - - - - - - - - - - 3 3 3
2 CO522 3 2 3 2 - - - - - - - 1 3 3 3
3 CO523 2 3 2 3 1 1 - - - - - 2 3 2 3
4 CO524 - - 1 1 - - - - - - - 3 3 3 2
5 CO525 - - - - - 2 - - - - 1 - 3 2 2

TEXT / REFERENCE BOOKS

Seri BOOKNUM BOOK DETAILS

al BER.
No.
1 TB-1 JanD Rabaey, Anantha Chandrakasan, “ Digital Integrated Circuits: A Design
Perspective”,PHI, 2016.(Units II, III and IV).
2 TB-2 Neil H E Weste, Kamran Eshranghian, “ Principles of CMOS VLSI Design: A System
Perspective,” Addison Wesley, 2009.( Units-I, IV).
3 TB-3 Michael J Smith ,” Application Specific Integrated Circuits, Addison Wesley, (Unit-V)
4 TB-4 Samir Palnitkar,” Verilog HDL:A guide to Digital Design and Synthesis”, Second
Edition,Pearson Education,2003.(Unit-V)
5 TB-5 Parag K.Lala,” Digital Circuit Testing and Testability”, Academic Press, 1997, (Unit-V)
6 RB-1 D.A. Hodges and H.G. Jackson, Analysis and Design of Digital Integrated
Circuits,International Student Edition, McGraw Hill 1983
7 RB-2 P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification-Methodology and
Techniques", Kluwer Academic Publishers,2001
8 RB-3 SamihaMourad and YervantZorian, “Principles of Testing Electronic Systems”, Wiley
2000
9 RB-4 M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits", Kluwer Academic Publishers,2000

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 COURSE TIME TABLE

Period : Period : Period : Period : Period : Period : Period : Period

1 2 3 4 5 6 7 :8

MONDAY

TUESDAY
WEDNESDAY

THURSDAY

FRIDAY

6/
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COURSE PLAN for UNIT - I and UNIT TITLE : MOS TRANSISTOR PRINCIPLES

COURSE TEACHING
Serial LECTURE NO OF TEACHING BOOK
LECTURE TOPIC OUTCOME METHOD METHODOLOGY
No. TYPE PERIOD NUMBER
NO. LEVEL
1 MOS logic families (NMOS L 1 CO521
K2-
K1- Lecture TB-1
and CMOS) UNDERSTAND

Ideal IV K2-
2 L 1 CO521 K1- Lecture TB-1
UNDERSTAND
Characteristics
K2-
3 Non Ideal IV Characteristics L 1 CO521 K1- Lecture TB-1
UNDERSTAND
4 K2-
CMOS devices. L 1 CO521 K1- Lecture TB-1
UNDERSTAND
5 K2-
MOS(FET) Transistor L 1 CO521 K1- Lecture TB-1
UNDERSTAND
Characteristic under Static K2- K4- Practice by
6 L 1 CO521 TB-1
Conditions doing
UNDERSTAND
Characteristic under Dynamic K2- K4- Practice by
7 L 1 CO521 TB-1
Conditions UNDERSTAND doing
8 K2- K4- Practice by
L 1 CO521 TB-1
Technology Scaling doing
UNDERSTAND
9 Power K2- K4- Practice by
L 1 CO521 TB-1
doing
consumption UNDERSTAND

K1-
10 Revision L 1 CO521 K1- Lecture TB-1
REMEMBER

7/
22
COURSE PLAN for UNIT - II and UNIT TITLE :COMBINATIONAL LOGIC CIRCUITS

COURSE TEACHING
Serial LECTURE NO OF TEACHING BOOK
LECTURE TOPIC OUTCOME METHOD
No. TYPE PERIOD METHODOLOG NUMBER
NO. LEVEL
Y
K3-APPLY
1 Propagation L 1 CO522 K1- Lecture TB-1
Delays, stick
diagram
K3-APPLY
2 Layout diagrams L 1 CO522 K1- Lecture TB-1
Examples of combinational logic K3-APPLY
3 L 1 CO522 K1- Lecture TB-1
design
4 Elmore’s constant L 1 CO522 K3-APPLY K1- Lecture TB-1
5 Static Logic Gates L 1 CO522 K3-APPLY K1- Lecture TB-1
6 Dynamic Logic Gates L 1 CO522 K3-APPLY K1- Lecture TB-1

7 Pass Transistor Logic L 1 CO522 K3-APPLY K1- Lecture TB-1

8 L 1 CO522 K2- K1- Lecture TB-1
Power Dissipation UNDERSTAND
9 Low Power Design L 1 CO522 K2- K1- Lecture TB-1
UNDERSTAND
principles.

K1-
10 Revision L 1 CO522 REMEMBER K1- Lecture TB-1

8/
22
COURSE PLAN for UNIT - III and UNIT TITLE :Synchronous Sequential Circuits and clocking
Strategies

COURSE TEACHING
Serial LECTURE NO OF TEACHING BOOK
LECTURE TOPIC OUTCOME METHOD
No. TYPE PERIOD METHODOLOGY NUMBER
NO. LEVEL
K2-
1 L 1 CO523 K1- Lecture TB-1
Static Latches UNDERSTAN
D
K2-
2 L 1 CO523 K1- Lecture TB-1
Static Registers UNDERSTAN
D
K2-
3 L 1 CO523 K1- Lecture TB-1
Dynamic Latches UNDERSTAN
D
K2-
4 L 1 CO523 K1- Lecture TB-1
Dynamic Registers UNDERSTAN
D
K2-
5 L 1 CO523 K1- Lecture TB-1
Pipelines UNDERSTAN
D
K2-
Non bistable Sequential
6 L 1 CO523 UNDERSTAN K1- Lecture TB-1
Circuits.Timing D
K2-
7 Classification of Digital L 1 CO523 K1- Lecture TB-1
UNDERSTAN
Systems D
K2-
8 L 1 CO523 K1- Lecture TB-1
Synchronous Design UNDERSTAN
D
Self-Timed Circuit K2-
9 L 1 CO523 K1- Lecture TB-1
UNDERSTAN
Design D

K2-
10 Revision L 1 CO523 K1- Lecture TB-1
UNDERSTAN
D

9/
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COURSE PLAN for UNIT - IV and UNIT TITLE : INTERCONNECT , MEMORY ARCHITECTURE
AND ARITHMETIC CIRCUITS

COURSE TEACHING
Seria LECTURE NO OF TEACHING BOOK
LECTURE OUTCOME METHOD
l TYPE PERIOD METHODOLO NUMBER
TOPIC NO. LEVEL
No. GY
Interconnect K2-
1 L 1 CO524 K1- Lecture TB-1
UNDERSTAND
parameters-
capacitance,R
esistance and
Inductance
Electrical WireModels K4-ANALYZE
2 L 1 CO524 K1- Lecture TB-1

3 Sequential digital circuits: L 1 CO524

K4-ANALYZE
K1- Lecture TB-1
adders,
Multipliers K4-ANALYZE
4 L 1 CO524 K1- Lecture TB-1

Comparators K4-ANALYZE
5 L 1 CO524 K1- Lecture TB-1

Shift registers K4-ANALYZE

6 L 1 CO524 K1- Lecture TB-1

7 Logic Implementation L 1 CO524

K3-APPLY
K1- Lecture TB-1
using Programmable
Devices (ROM, PLA,
FPGA)
Memory Architecture and K2-
8 L 1 CO524 K1- Lecture TB-1
Building Blocks UNDERSTAND
Memory Core K2-
9 L 1 CO524 K1- Lecture TB-1
UNDERSTAND
and Memory
Peripherals
Circuitry

K1-REMEMBER
10 Revision L 1 CO524 K1- Lecture TB-1

COURSE PLAN for UNIT - V and UNIT TITLE : ASIC DESIGN AND TESTING
10
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 COURSE TEACHING
Serial LECTURE NO OF TEACHING BOOK
LECTURE OUTCOME METHOD
No. TYPE PERIO METHODOLOGY NUMBER
TOPIC NO. LEVEL
D
Introduction to K2-
1 L 1 CO525 K1- Lecture TB-1
UNDERSTAND
wafer to chip
fabrication
process flow.
Microchip
design process
& issues in test
2 Verification of complex L 1 CO525 K2- K1- Lecture TB-1
chips, embedded cores and UNDERSTAND
SOCs, Fault models, Test
coding.
K2-
3 ASIC Design Flow L 1 CO525 K1- Lecture TB-1
UNDERSTAND
K2-
4 Introduction to ASICs L 1 CO525 K1- Lecture TB-1
UNDERSTAND
Introduction to test K2-
5 benches L 1 CO525 UNDERSTAND K1- Lecture TB-1

6 Writing test benches in L 1 CO525 K3-APPLY K1- Lecture TB-1

Verilog HDL
7 Automatic test pattern L 1 CO525 K4-ANALYZE K1- Lecture TB-1
generation
Design for testability, K5- EVALUATE
8 L 1 CO525 K1- Lecture TB-1

Scan design: K3-APPLY

9 L 1 CO525 K1- Lecture TB-1
Test interface
and boundary
scan.

K5- EVALUATE
10 Revision L 1 CO525 K1- Lecture TB-1

11
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COURSE PLAN for CLASS TYPE WISE

PRACTICAL TUTORIAL
Serial UNIT LECTURE PERIOD PEROID REVISION TOTAL
No. NUMBER PERIOD PERIOD PERIOD
1. UNIT - I 9 0 0 1 10
2. UNIT - II 9 0 0 1 10
3. UNIT - III 9 0 0 1 10
4. UNIT - IV 9 0 0 1 10
5. UNIT - V 9 0 0 1 10
SUBJECT HANDLERS OF YESTER YEARS
Se ACAD % OF
ri EMI SEMEST NAME OF THE DESIGNA DEPART BATCH RESULT
al C ER FACULTY TION MENT PRODU
N YEA CED
o. R

1 2023- 5 R.NAGADEEPA AP ECE 2021- 75%

2024 2025

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 COURSE REGISTRED STUDENT LIST

Se ACADEM S BATCH REGISTE NAME OF THE GENDER MOBILE E-MAIL ID

ri IC E R NO. STUDENT NO
al YEAR M
N E
o. S
T
E
R
2022- 91042210600 9751084987 [email protected]
1 2024-2025 ALEXPANDIAN M MALE
5 2026 1
2022- 91042210600 8248610332 [email protected]
2 2024-2025 ALIYA FATIMA A FEMALE
5 2026 2
2022- 91042210600 9042094171 [email protected]
3 2024-2025 AMUTHAVAN N MALE
5 2026 3
2022- 91042210600 9342882655
4 2024-2025 ARAVIND K.G MALE [email protected]
5 2026 4
2022- 91042210600 9751653416 [email protected]
5 2024-2025 ARUNKUMAR R MALE
5 2026 5 m
2022- 91042210600 6379559886 [email protected]
6 2024-2025 BHARATHVAJ M.E MALE
5 2026 6 m
2022- 93631
91042210600 [email protected]
7 2024-2025 2026 CHITHRA DEVI M MALE 71648
7
5
2022- 91042210600 9884192565 [email protected]
8 2024-2025 DHAARANI M FEMALE
5 2026 8
2022- 91042210600 9080985341 [email protected]
9 2024-2025 DHUSBIHAA BANU M FEMALE
5 2026 9
2022- 91042210601 9894265610 [email protected]
10 2024-2025 DURGESH M MALE
5 2026 0
2022- 91042210601 9944563055 [email protected]
11 2024-2025 HARINI K FEMALE
5 2026 2
2022- 91042210601 6383996479 [email protected]
12 2024-2025 HARISH KUMAR K MALE
5 2026 3
2022- 91042210601 9360291454 [email protected]
13 2024-2025 IFRAN KHAN P MALE
5 2026 4
2022- 91042210601 6380340269
14 2024-2025 JAMUNA RANI B FEMALE [email protected]
5 2026 5
2022- 91042210601 8838279652 [email protected]
15 2024-2025 KAVIPRIYA J FEMALE
5 2026 6
2022- 91042210601 [email protected]
16 2024-2025 MADESHKANNA S.B MALE 6382919783
5 2026 8
2022- 91042210601 8270030152 [email protected]
17 2024-2025 MATHEESWAR B MALE
5 2026 9
2022- mohamedabubakker0701@gma
91042210602 MOHAMED 8148648395
18 2024-2025 2026 MALE il.com
0 ABUBAKKAR S
5
2022- mohmedfahad24042004@gmail
91042210602 9080596940
19 2024-2025 2026 MOHAMMED FAHAD N MALE .com
1
5
2022- 91042210602 8098064890 [email protected]
20 2024-2025 NARASIMMAN K FEMALE
5 2026 2
2022- 91042210602 9342602268 [email protected]
21 2024-2025 NAVEEN A MALE
5 2026 3
2022- 91042210602 9626968046 [email protected]
22 2024-2025 PONNAMMAL R FEMALE
5 2026 5
2022- 91042210602 7639805658 [email protected]
23 2024-2025 PRADEEPA M FEMALE
5 2026 6
13
/22
 2022- 91042210602 9942392253 [email protected]
24 2024-2025 RAJASEKAR B MALE
5 2026 7
2022- 91042210602 9159196357 [email protected]
25 2024-2025 RESHMA O FEMALE
5 2026 8
2022- 91042210602 9080539559 [email protected]
26 2024-2025 RIYA JASMINE N FEMALE
5 2026 9
2022- 91042210603 9655579716 [email protected]
27 2024-2025 SANJINI V FEMALE
5 2026 0
2022- shanthiyashanthiya485@gmail.
91042210603 8124635629
28 2024-2025 2026 SANTHIYA S FEMALE com
1
5
2022- [email protected]
91042210603 8667653006
29 2024-2025 2026 SHANMUGA PRIYA A FEMALE om
3
5
2022- 91042210603 9944690535 [email protected]
30 2024-2025 SULAIMAN D MALE
5 2026 4
2022- suryadevasenathypathy@gmail.
91042210603 SURYADEVASENATHYP 9626981552
31 2024-2025 2026 MALE com
5 ATHY S
5
2022- thilakavathirajalakshimi@gmail
91042210603 8531841707
32 2024-2025 2026 THILAGAVATHI T MALE .com
7
5
2022- 91042210603 8489527831 [email protected]
33 2024-2025 VAIRA SELVAM V MALE
5 2026 8
2022- [email protected]
91042210603 9345154790
34 2024-2025 2026 VARSHA C FEMALE m
9
5
2022- 91042210604 9489047121 [email protected]
35 2024-2025 VIJAYALAKSHMI V FEMALE
5 2026 0
2022- [email protected]
91042210604 8056892644
36 2024-2025 2026 YUVARAJ P MALE
2
5

14
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COURSE ASSESSMENT DETAILS
Se SEMESTER REGISTER NAME OF THE INTERNAL INTERNAL
ri NO. STUDENT -1- -2-
a MARK MARK
l
N
o.
1 5 910422106001 ALEXPANDIAN M 70 95
2 5 910422106002 ALIYA FATIMA A 98 95
3 5 910422106003 AMUTHAVAN N 38 40
4 5 910422106004 ARAVIND K.G 68 65
5 5 910422106005 ARUNKUMAR R 60 68
6 5 910422106006 BHARATHVAJ M.E 75 75
7 5 910422106007 CHITHRA DEVI M 50 AB
8 5 910422106008 DHAARANI M 68 90
9 5 910422106009 DHUSBIHAA BANU M AB AB
10 5 910422106010 DURGESH M AB 58
11 5 910422106012 HARINI K 50 65
12 5 910422106013 HARISH KUMAR K AB 58
13 5 910422106014 IFRAN KHAN P 3 38
14 5 910422106015 JAMUNA RANI B 20 73
15 5 910422106016 KAVIPRIYA J 95 95
16 5 910422106018 MADESHKANNA S.B 3 58
17 5 910422106019 MATHEESWAR B 58 75
18 5 910422106020 MOHAMED ABUBAKKAR S 83 75
19 5 910422106021 MOHAMMED FAHAD N 30 60
20 5 910422106022 NARASIMMAN K 50 68
21 5 910422106023 NAVEEN A AB AB
22 5 910422106025 PONNAMMAL R 78 90
23 5 910422106026 PRADEEPA M 73 70
24 5 910422106027 RAJASEKAR B 73 88
25 5 910422106028 RESHMA O 68 95
26 5 910422106029 RIYA JASMINE N 40 70
27 5 910422106030 SANJINI V 68 95
28 5 910422106031 SANTHIYA S 55 60
29 5 910422106033 SHANMUGA PRIYA A 53 60
30 5 910422106034 SULAIMAN D 78 95
SURYADEVASENATHYPATHY
31 5 910422106035
S 98 95
32 5 910422106037 THILAGAVATHI T 63 68
33 5 910422106038 VAIRA SELVAM V 90 95
34 5 910422106039 VARSHA C 53 53

15
/22
 35 5 910422106040 VIJAYALAKSHMI V 55 70
36 5 910422106042 YUVARAJ P 63 93

COURSE ASSESSMENT - UNIVERSITY RESULT

Serial SEMESTER REGISTER NO. NAME OF THE STUDENT UNIVERSITY MONTH &
No. RESULT YEAR OF
GRADE PASSING

1 5 910422106001 ALEXPANDIAN M

2 5 910422106002 ALIYA FATIMA A

3 5 910422106003 AMUTHAVAN N

4 5 910422106004 ARAVIND K.G

5 5 910422106005 ARUNKUMAR R

6 5 910422106006 BHARATHVAJ M.E

7 5 910422106007 CHITHRA DEVI M

8 5 910422106008 DHAARANI M

9 5 910422106009 DHUSBIHAA BANU M

10 5 910422106010 DURGESH M

11 5 910422106012 HARINI K

12 5 910422106013 HARISH KUMAR K

13 5 910422106014 IFRAN KHAN P

14 5 910422106015 JAMUNA RANI B

15 5 910422106016 KAVIPRIYA J

16 5 910422106018 MADESHKANNA S.B

17 5 910422106019 MATHEESWAR B

18 5 910422106020 MOHAMED ABUBAKKAR S

19 5 910422106021 MOHAMMED FAHAD N

20 5 910422106022 NARASIMMAN K

21 5 910422106023 NAVEEN A

22 5 910422106025 PONNAMMAL R

23 5 910422106026 PRADEEPA M

24 5 910422106027 RAJASEKAR B

25 5 910422106028 RESHMA O

26 5 910422106029 RIYA JASMINE N

27 5 910422106030 SANJINI V

16
/22
28 5 910422106031 SANTHIYA S

29 5 910422106033 SHANMUGA PRIYA A

30 5 910422106034 SULAIMAN D

31 5 910422106035 SURYADEVASENATHYPATHY S

32 5 910422106037 THILAGAVATHI T

33 5 910422106038 VAIRA SELVAM V

34 5 910422106039 VARSHA C

35 5 910422106040 VIJAYALAKSHMI V

36 5 910422106042 YUVARAJ P

17
/22
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
LIST OF SLOW LEARNERS(After Internal Assessment Test-I)

Students Scored less than or equal to 50

Se SEMESTER REGISTER NAME OF THE INTERNAL

ri NO. STUDENT -1-
a MARK
l
N
o.
1 5 910422106003 AMUTHAVAN N 38
2 5 910422106014 IFRAN KHAN P 3
3 5 910422106015 JAMUNA RANI B 20
4 5 910422106018 MADESHKANNA S.B 3
5 5 910422106021 MOHAMMED FAHAD N 30
6 5 910422106029 RIYA JASMINE N 40

18
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 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LIST OF REMEDIAL MEASURES FOR SLOW LEARNERS

(After Internal Assessment Test-I)

Subject code/Name:EC3552-VLSI and Chip Design

 Remedical Classes(Special Timetable)

 Assignments
 Repeated University Questions

TIME 5.00-6.00pm
MON TLRF
TUES VLSI
WED WC
THURS MIS/IP
FRI OCN/IP

19
/22
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
LIST OF SLOW LEARNERS(After Internal Assessment Test-II)

Students Scored less than or equal to 50

Se SEMESTER REGISTER NAME OF THE INTERNAL INTERNAL

ri NO. STUDENT -1- -2-
a MARK MARK
l
N
o.
1 5 910422106003 AMUTHAVAN N 38 40
2 5 910422106014 IFRAN KHAN P 3 38
3 5 910422106015 JAMUNA RANI B 20 73
4 5 910422106018 MADESHKANNA S.B 3 58
5 5 910422106021 MOHAMMED FAHAD N 30 60
6 5 910422106029 RIYA JASMINE N 40 70

20
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 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

LIST OF REMEDIAL MEASURES FOR SLOW LEARNERS

(After Internal Assessment Test-II)

Subject code/Name:EC3552-VLSI and Chip Design

 Remedical Classes(Special Timetable)

 Assignments
 Repeated University Questions

TIME 5.00-6.00pm
MON TLRF
TUES VLSI
WED WC
THURS MIS/IP
FRI OCN/IP

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 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SLOW LEARNERS-STUDENT PROGRESSION

Subject code/Name: EC3552-VLSI and Chip Design

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