Name- Mumukshu Bohra (23FE10ECE00035)
Subject- HDL Lab Record
Experiment 1: Introduction to EDA Tool & Logic
Gates Using Verilog
Aim:
To explore the basics of Electronic Design Automation
(EDA) tools and implement basic logic gates using
Verilog HDL.
Apparatus:
Computer with EDA software (ModelSim/Quartus/ISE),
Verilog HDL.
Theory:
EDA tools assist in designing and simulating digital
circuits. Verilog HDL is a language used to model
electronic systems. Logic gates like AND, OR, NOT, etc.,
form the foundation of digital design.
Code:
module logic_gates(a, b, and_out, or_out, not_out,
nand_out, nor_out, xor_out, xnor_out);
input a, b;
output and_out, or_out, not_out, nand_out, nor_out,
xor_out, xnor_out;
assign and_out = a & b;
assign or_out = a | b;
assign not_out = ~a;
assign nand_out = ~(a & b);
assign nor_out = ~(a | b);
assign xor_out = a ^ b;
assign xnor_out = ~(a ^ b);
endmodule
Result:
Successfully implemented and simulated various logic
gates.
Conclusion:
Basic understanding of EDA tools and logic gate
modeling in Verilog HDL was achieved.
Experiment 2: Arithmetic Circuits - Adders and
Subtractors
Aim:
To implement and simulate half adder, full adder, half
subtractor, and full subtractor using Verilog.
Code:
module half_adder(a, b, sum, carry);
input a, b;
output sum, carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
module full_adder(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
module half_subtractor(a, b, diff, borrow);
input a, b;
output diff, borrow;
assign diff = a ^ b;
assign borrow = ~a & b;
endmodule
module full_subtractor(a, b, bin, diff, bout);
input a, b, bin;
output diff, bout;
assign diff = a ^ b ^ bin;
assign bout = (~a & b) | (~(a ^ b) & bin);
endmodule
Result:
All adders and subtractors were implemented and
verified using simulation.
Conclusion:
Successfully designed basic arithmetic circuits using
Verilog HDL.
Experiment 3: 4-bit Ripple Carry Adder and CLA
Adder
Aim:
To design and simulate a 4-bit ripple carry adder and a
carry look-ahead adder.
Code:
module ripple_carry_adder_4bit(a, b, cin, sum, cout);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire c1, c2, c3;
full_adder FA0(a[0], b[0], cin, sum[0], c1);
full_adder FA1(a[1], b[1], c1, sum[1], c2);
full_adder FA2(a[2], b[2], c2, sum[2], c3);
full_adder FA3(a[3], b[3], c3, sum[3], cout);
endmodule
module cla_adder(a, b, cin, sum, cout);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p = a ^ b;
assign g = a & b;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & c[1]);
assign c[3] = g[2] | (p[2] & c[2]);
assign cout = g[3] | (p[3] & c[3]);
assign sum = p ^ c;
endmodule
Result:
Implemented and verified both ripple carry and CLA
adders.
Conclusion:
Ripple and CLA adders were designed and simulated
using Verilog successfully.
Experiment 4: 8 to 1 Multiplexer Using Case
Statement
Aim:
To write Verilog code for 8 to 1 multiplexer using a case
statement.
Code:
module mux8to1(sel, in, out);
input [2:0] sel;
input [7:0] in;
output reg out;
always @(sel or in)
case (sel)
3'b000: out = in[0];
3'b001: out = in[1];
3'b010: out = in[2];
3'b011: out = in[3];
3'b100: out = in[4];
3'b101: out = in[5];
3'b110: out = in[6];
3'b111: out = in[7];
endcase
endmodule
Result:
Multiplexer output varied correctly with selection input.
Conclusion:
8:1 MUX successfully implemented using Verilog.
Experiment 5: Demultiplexer and Decoders
Aim:
To design a demultiplexer using case statement and
decoders for higher-order decoding.
Code:
module demux1to4(sel, din, dout);
input [1:0] sel;
input din;
output reg [3:0] dout;
always @(sel or din)
case (sel)
2'b00: dout = {3'b000, din};
2'b01: dout = {2'b00, din, 1'b0};
2'b10: dout = {1'b0, din, 2'b00};
2'b11: dout = {din, 3'b000};
endcase
endmodule
module decoder_2to4(input [1:0] a, output reg [3:0] y);
always @(a)
case(a)
2'b00: y = 4'b0001;
2'b01: y = 4'b0010;
2'b10: y = 4'b0100;
2'b11: y = 4'b1000;
endcase
endmodule
Result:
Demux and decoder functionality verified using
simulation.
Conclusion:
Demultiplexer and decoder circuits implemented
successfully using Verilog.
Experiment 6: Encoders and N-bit Comparator
Aim:
To write Verilog programs for encoders (with and
without priority) and N-bit comparator.
Code:
module encoder8to3(in, out);
input [7:0] in;
output reg [2:0] out;
always @(in)
casez(in)
8'b00000001: out = 3'b000;
8'b0000001?: out = 3'b001;
8'b000001??: out = 3'b010;
8'b00001???: out = 3'b011;
8'b0001????: out = 3'b100;
8'b001?????: out = 3'b101;
8'b01??????: out = 3'b110;
8'b1???????: out = 3'b111;
default: out = 3'b000;
endcase
endmodule
module comparator(a, b, eq);
input [3:0] a, b;
output eq;
assign eq = (a == b);
endmodule
Result:
Priority encoder and comparator simulation matched
expected output.
Conclusion:
Successfully modeled encoder and comparator circuits
using Verilog.
Experiment 7: Flip-Flop Implementation
Aim:
To design and simulate a D flip-flop and verify its truth
table.
Code:
module d_flip_flop(d, clk, q);
input d, clk;
output reg q;
always @(posedge clk)
q <= d;
endmodule
Result:
Output followed the input at the rising edge of the clock.
Conclusion:
Flip-flop functionality verified and understood via
simulation.
Experiment 8: Up/Down Synchronous Counter
Aim:
To design a synchronous up/down counter and simulate
its operation.
Code:
module up_down_counter(clk, reset, up_down, count);
input clk, reset, up_down;
output reg [3:0] count;
always @(posedge clk or posedge reset)
if (reset)
count <= 0;
else if (up_down)
count <= count + 1;
else
count <= count - 1;
endmodule
Result:
Counter counted up/down based on the control input.
Conclusion:
Up/down counter was implemented and validated using
Verilog simulation.
