250325 Digital System Design

Memory

1
Memory

2
 CPU Memory Interface
address bus
CPU Memory Interface usually consists of: data bus
❑ unidirectional address bus Read
❑ bidirectional data bus
Memo
CPU Write
ry
❑ read control line Ready

❑ write control line

size

❑ ready control line

❑ size (byte, word) control line
Memory access involves a memory bus transaction
❑ read:
I. set address, read control signal and size signal,
II. copy data when ready is set by memory
❑ write:
I. set address, data, write control signal and size,
II. done when ready is set

3
 Memory Hierarchy
The design constraints on a computer memory can be summed up by three
questions (i) How Much (ii) How Fast (iii) How expensive.
There is a tradeoff among the three key characteristics
A variety of technologies are used to implement memory system
Dilemma facing designer is clear 🡪 large capacity, fast, low cost!!
Solution 🡪 Employ memory hierarchy

Cost
registers

Cache Capacity
Main Memory

Disk Cache Access

Magnetic Disk Time
Removable Media

4
 Memory

Registers Static RAM

CPU

Dynamic RAM
Cache Cache
Controller Memory
Local CPU / Memory Bus

PCI
DRAM Co-processor
Controller
Peripheral Component Interconnect Bus

EISA/PCI Bridge Hard Drive Video SCSI

Controller Controller Adaptor Adaptor

EISA PC Bus
SCSI
Bus
PC Card 1 PC Card 2 PC Card 3
ENG3640 Fall 2012 5
Memory Classification:

6
Classifications: Key Design Metrics

7
 The Memory Hierarchy
Let’s look at numbers for an Intel Pentium 4, 3.2 GHz Server.
Component Access Speed Size of Component
(Time for data to be
returned)
Registers 1 cycle = 8 registers
0.3 nanoseconds

L1 Cache 3 cycles = Separate Data and Instruction

1 nanoseconds Caches: 16 Kbytes each

L2 Cache 20 cycles = 256 Kbytes,

7 nanoseconds 8-way set associative

L3 Cache 40 cycles = 4096 Kbytes,

13 nanoseconds 8-way set associative

Memory 300 cycles = 16 Gigabytes

100 nanoseconds

Disk 30,000,000 cycles = 400 Gigabytes

10 milliseconds

Chapter 6: Memory 8
 Basic Organization
Memory Cell Operation

• Represent two stable/semi-stable states

representing 1 and 0
• Capable of being written to at least once
• Capable of being read multiple times
 Static RAM (SRAM)
• Desired for main memory
• Used in cache
• Basically an array of flip-flops
• Simple to interface and control
• Fast
• Relatively low density - complex
• Relatively expensive
Static RAM model
 Block diagram of RAM
2k x n memory
k n
ADRS OUT
n
DATA
CS
WR

• This block diagram introduces the main interface to RAM.

– A Chip Select, CS, enables or disables the RAM.
– ADRS specifies the address or location to read from or write to.
– WR selects between reading from or writing to the memory.
4 To read from memory, WR should be set to 0.
OUT will be the n-bit value stored at ADRS.
4 To write to memory, we set WR = 1.
DATA is the n-bit value to save in memory.
• This interface makes it easy to combine RAMs together, as we’ll see.

12
 Memory sizes
• We refer to this as a 2k x n memory.
– There are k address lines, which can specify one of 2k addresses.
– Each address contains an n-bit word.

2k x n memory
k n
ADRS OUT
n
DATA
CS
WR

• For example, a 224 x 16 RAM contains 224 = 16M words, each 16 bits
long.
– The RAM would need 24 address lines.
– The total storage capacity is 224 x 16 = 228 bits.

13
 Size matters!
• Memory sizes are usually specified in numbers of bytes (8 bits).
• The 228-bit memory on the previous page translates into:
228 bits / 8 bits per byte = 225 bytes
• With the abbreviations below, this is equivalent to 32 megabytes.

• To confuse you, RAM size is measured in base 2 units, while hard drive size
is measured in base 10 units.
– In this class, we’ll only concern ourselves with the base 2 units.

14
 Typical memory sizes
• Some typical memory capacities:
– PCs usually come with 128-512MB RAM.
– PDAs have 8-64MB of memory.
– Digital cameras and MP3 players can
have 32MB or more of storage.
• Many operating systems implement
virtual memory, which makes the
memory seem larger than it really is.
– Most systems allow up to 32-bit
addresses. This works out to 232, or
about four billion, different possible
addresses.
– With a data size of one byte, the result is
apparently a 4GB memory!
– The operating system uses hard disk
space as a substitute for “real” memory.

15
 Reading RAM
• To read from this RAM, the controlling circuit
must:
– Enable the chip by ensuring CS = 1.
– Select the read operation, by setting WR = 0.
– Send the desired address to the ADRS input.
– The contents of that address appear on OUT after
a little while.
• Notice that the DATA input is unused for read
operations. k
2 x n memory
k n
ADRS OUT
n
DATA
CS
16
WR
SRAM Memory Timing for Read Accesses

17
 Writing RAM
• To write to this RAM, you need to:
– Enable the chip by setting CS = 1.
– Select the write operation, by setting WR = 1.
– Send the desired address to the ADRS input.
– Send the word to store to the DATA input.
• The output OUT is not needed for memory
write operations.
2k x n memory
k n
ADRS OUT
n
DATA
CS
WR
18
SRAM Memory Timing for Write Accesses

19
 PIC To SRAM ‘#’ means low true

PIC 8Kx8

RA[7:0] A[7:0]
RB[4:0] A[12:8]
RC[7:0] IO[7:0]
Vdd CE2
OE# CE1#
RD0
RD1 WE#

To read: Address on RA, RB. RC port is all inputs; RD0 = ‘0’, RD1 = ‘1’.
To write: Address on RA, RB. RC port is all outputs; RD0 = ‘1’, RD1 = 0.

V 0.1 20
Expanding Memory RAM1 8Kx8

RA[7:0] A[7:0]
RB[4:0] A[12:8]
RC[7:0] IO[7:0]
RB5 CE2
OE# CE1#
RD0
PIC
RD1 WE#

RAM0 8Kx8
RAM1 accessed when A[7:0]
RB5 = 1
A[12:8]
IO[7:0]
CE1#
RAM0 accessed when OE# CE2
RB5 = 0
WE#

21
 More Memory RAM0 RAM1
13 A[12:0]
RB[4:0], RA[7:0] A[12:0]
8
RC[7:0] IO[7:0] IO[7:0]
RD0 OE# OE#
RD1 WE# WE#
PIC CE1# CE1#

RB[6:5]

2-to-4 decoder RAM2 RAM3

RB[6:5]=00 A[12:0]
2 0 A[12:0]
RB[6:5]=01 IO[7:0]
1 IO[7:0]
RB[6:5]=10 OE#
2 OE#
RB[6:5]=11 WE# WE#
3 CE1# CE1#
chip select decoding
V 0.1 22
 Memory Organization
• A 16Mbit chip can be organised as 1M of 16 bit
words
• A bit per chip system has 16 lots of 1Mbit chip
with bit 1 of each word in chip 1 and so on
• A 16Mbit chip can be organised as a 2048 x 2048
x 4bit array
– Reduces number of address pins
• Multiplex row address and column address
• 11 pins to address (211=2048)
• Adding one more pin doubles range of values so x4 capacity
2 BIT Decoder (2 to 4)
2 to 1 MUX
4 to 1 MUX
 Dynamic RAM (DRAM)
• Used in main memory
• Bits stored as charge in capacitors
Essentially analog device
Charges leak
• Need refreshing even when powered
Need refresh circuits
• Higher density (more bits per chip)
• Slower than Static RAM
• Less expensive
Dynamic RAM model
 DRAM Organization and Operations
In the traditional DRAM, any storage location can be randomly accessed for
read/write by inputting the address of the corresponding storage location.

❑ Memory cell consists of a transistor and a capacitor. The charge on the

capacitor represents 0 or 1 for the memory cell. The support circuitry
for the DRAM chip is used to read/write to a memory cell.
❑ A typical DRAM of bit capacity 2N * 2M consists of an array of memory
cells arranged in 2N rows (word-lines) and 2M columns (bit-lines).
❑ Each memory cell has a unique location represented by the
intersection of word and bit line.

ENG3640 Fall 2012 29

 DRAM Cell

ENG3640 Fall 2012 30

Memory Array Architecture

ENG3640 Fall 2012 31

 Symbolic Representation of DRAM
To write data:
❑ Signals from address decoding R/W logic will close switches S1, S2 while
keeping S3,S4 open
❑ So input data is connected to C then switches (S1, S2) are disconnected.
To read data:
❑ Switches S2,S3,S4 are closed while S1 is open
❑ This connects stored capacitor voltage to sense amplifier
❑ The sense amplifier will compare the capacitor voltage to a reference voltage
and produce a solid ‘0’ or ‘1’ and C gets refreshed.

ENG3640 Fall 2012 32

 DRAM Characteristics
Destructive Read
❑ When cell read, charge removed
❑ Must be restored after a read
Refresh
❑ Also, there’s steady leakage
❑ Charge must be restored periodically
DRAM are dense (lots of cells) so there are many address lines.
❑ To reduce the physical size of DRAM we can reduce the number of pins
by applying the address lines serially in to parts (Row Address and then
Column Address)

ENG3640 Fall 2012 33

 Address Multiplexing
16K x 1 DRAM 🡪 14 address lines
64K x 1 DRAM 🡪 16 address lines
4M x 1 DRAM 🡪 22 address lines
High capacity memory chips require many pins if each address required a
separate pin
Solution: In order to reduce # of pins on DRAM chips manufacturers
utilize address multiplexing 🡪 whereby each address input pin can
accommodate two different address bits.
What does this translate to?
1. Significant decrease in size of IC package
2. Better yield
3. Maximize the amount of memory that can fit on one board
4. Cheaper ICs

ENG3640 Fall 2012 34

34
 DRAM Memory Access

DRAM Memory is arranged in a XY grid pattern of rows and

columns.
❖ First, the row address is sent to the memory chip and latched,
❖ then the column address is sent in a similar fashion.
This row and column-addressing scheme (called multiplexing)
allows a large memory address to use fewer pins.
The charge stored in the chosen memory cell is amplified
using the sense amplifier and then routed to the output pin.
Read/Write is controlled using the read/write logic.

ENG3640 Fall 2012 35

 How DRAM Works
A7A6A5A4A3A2A1A0 A7A6A5A4
A3A2A1A0

ENG3640 Fall 2012 36

DRAM Logical Diagram

ENG3640 Fall 2012 37

DRAM `Read’ Timing Waveform
After Applying RAS and CAS the output enable is
applied to access the data

Delay until
data
available

ENG3640 Fall 2012 38

DRAM `Write’ Timing

ENG3640 Fall 2012 39

 Key DRAM Timing
• tRAC Parameters
: minimum time from RAS line falling to the valid data
output.
– Quoted as the speed of a DRAM
– A fast 4Mb DRAM tRAC = 60 ns
• tRC: minimum time from the start of one row access to the
start of the next.
– tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns
• tCAC: minimum time from CAS line falling to valid data
output.
– 15 ns for a 4Mbit DRAM with a tRAC of 60 ns
• tPC: minimum time from the start of one column access to
the start of the next.
– 35 ns for a 4Mbit DRAM with a tRAC of 60 ns 40
 DRAM Types:
Synchronous vs. Asynchrnous

DRAM - Dynamic RAM

FPM DRAM - Fast page-mode RAM
EDO DRAM - Extended Data Out RAM
BEDO DRAM - Burst Extended-data-out RAM
SDRAM - Synchronous Dynamic RAM
DDRRAM - Double Data Rate RAM
DDR2 (Twice the speed of DDR SDRAM)
DDR3 (Twice the speed of DDR2 SDRAM)
DDR4 (In Production ??)

ENG3640 Fall 2012 41

 Page Mode DRAM
DRAMs made to read & write blocks
Example
❑ Assert RAS, leave asserted
❑ Assert CAS multiple times to read sequence of data
Similar for writes

42
ENG3640 Fall 2012
DRAM Evolution (Synchronous)

There has been multiple improvements to the DRAM design in

the past 10 years.
❖ A Clock signal was added making the design synchronous (SDRAM).
❖ The data bus transfers data on both rising and falling edge of the clock
(DDR SDRAM)
❖ Second generation of DDR memory (DDR2) scales to higher clock
frequencies.
❖ Third generation (DDR3) has lower power consumption, higher clock
frequency and denser modules

Fall 2012 ENG364/Interfacing 43

 Synchronous DRAM (SDRAM)

Double Data Rate

SDRAM
▪ Transfers data on
both edges of the
clock

ENG3640 Fall 2012 44

 Volatile Memory Comparison
• DRAM Cell

• SRAM Cell
word line word line

bit line bit line

• Smaller line⇒ higher density, lower
bitcell
cost/bit
• Needs periodic refresh, and refresh after
read
• Larger cell ⇒ lower density, higher • Complex read ⇒ longer access time
cost/bit • Special IC process ⇒ difficult to integrate
• No refresh required with logic circuits

• Simple read ⇒ faster access

• Standard IC process ⇒ natural for
integration with logic

45
 Read Only Memory (ROM)
• Permanent storage
– Nonvolatile
• Microprogramming (will address later)
• Library subroutines
• Systems programs (BIOS)
• Function tables
• Controllers
 Types of ROM
• ROM: Written during manufacture
– Very expensive for small runs

• PROM: Programmable (once)

– Needs special equipment to program

• Read “mostly”
– EPROM: Erasable Programmable
• Erased by UV (All of chip!)
– Flash memory
• Whole blocks of memory stored/changed electrically
– EEPROM: Electrically Erasable
• Takes much longer to write than read (lower density)
EPROM
Semiconductor Memory

16Mbit DRAM
256kByte Module Organisation (256K x 1)
Typical 16 Mb DRAM (4M x 4)
1MByte Module Organization (1Meg x 8 bits)
 Refreshing
• Refresh circuit is included on the chip
• Count through rows
• Read & Write back
• Chip must be disabled during refresh
• Takes time
• Occurs asynchronously
• Slows down apparent performance
 Improvements in memory
RAM – continually gets denser.

DRAM – Several improvements:

SDRAM – synchronous DRAM
DDR-SDRAM - doubles transfer speed
RDRAM – asynchronous one transfer
per clock cycle
Comparison of improved DRAM

Conventional DRAM – 40 to 100 MB/S transfer rate?

 Synchronous DRAM (SDRAM)
• Access is synchronized with an external clock
• Address is presented to RAM
• RAM finds data (CPU waits in conventional DRAM)
• Since SDRAM moves data in time with system clock, CPU
knows when data will be ready
• CPU does not have to wait, it can do something else
• Burst mode allows SDRAM to set up stream of data and fire it
out in block
• DDR-SDRAM sends data twice per clock cycle (leading &
trailing edge)
SDRAM Read Timing
SDRAM
 DDR SDRAM

• SDRAM can only send data once per clock

• Double-data-rate SDRAM can send data twice
per clock cycle
– Rising edge and falling edge
 RAMBUS
• Adopted by Intel for Pentium & Itanium
• Main competitor to SDRAM

• Separate bus (hence the name RAMBUS)

– maximum 12 centimeter length bus !
• Bus addresses up to 320 RDRAM chips
– at 1.6Gbps
• Asynchronous block protocol
– Precise control signal timing
– 480ns access time
RAMBUS Diagram
 Direct Memory Access
• Transfers data from one address to another,
without CPU intervention
• Increase throughput and decrease power
consumption
DMA Addressing Modes

Source/destination
address can be
configured to be
unchange/increment/d
ecrement after each
transfer
 DMA Transfer Modes
• Six transfer modes
– Single transfer, block transfer, burst-block transfer, repeated single transfer,
repeated block transfer, repeated burst-block transfer
• Single transfer
– Each transfer requires a separate trigger, DMA is disable after transfer
• Must re-enable DMA before receive another trigger
– Repeated single transfer: DMA remains enable
• Another trigger start another transfer
• Block transfer
– Transfer of a complete block after one trigger, DMA is disable after transfer
– Repeated block transfer: DMA remains enable,
• Another trigger start another transfer
• Burst-block transfer
– Block transfers with CPU activity interleaved,
– Repeated burst-block transfer: DMA remains enable
• Keep transferring
• CPU executes at 20% capacity
Appendix

65
 Introduction

3 to 8 decoder

A5 A4 A3

3 to 8 decoder
A2 A1 A0

Address wires Data wires

A5 A4 A3….A0 D0
66
 Introduction

Selected cell

If A=110010
110 One cell selected

Avec 6 fils d’adresses,

On peut selectionner64
Positions (One bit per
Position)

With n Address wires,

we can select 2n
010
Positions(One bit per
Position)

Address wires Data wires

A5 A4 A3….A0 D0
67
Memory basics

If A=110010
One cell selected

With 6 address wires,

we can select 64
Positions (two bits per
Position)

With n Address wires,

we can select 2n
Positions (two bits per
Position)

68
Address wires Data wires
 Capacity
• 1 address bit: 2 locations, 0-------1
• 2 address bits: 4 locations, 0------3
• 3 address bits: 8 locations, 0------7
• 4 address bits: 16 locations, 0------15 (F)
• 5 address bits: 32 locations, 0------31(1F)
• 6 address bits: 64 locations, 0------63(3F)
• 7 address bits: 128 locations, 0------127(7F)
• 8 address bits: 256 locations, 0------255(FF)
• 9 address bits: 512 locations, 0------511(1FF)
• 10 address bits: 1024 locations, 0------1023(3FF) (1K)
• 11 address bits: 2048 locations, 0------2047(7FF)(2K)
• 12 address bits: 4096 locations, 0------4095(FFF)(4K)
• 13 address bits: 8K locations, 0------1FFF
• 14 address bits: 16K locations, 0------3FFF
• 15 address bits: 32K locations, 0------7FFF
• 16 address bits: 64K locations, 0------FFFF
69
Notes on addres 1Kilo:210=1024 Notes on data: 8 bits=byte
 Classification of memory

Classes of memories:

• RAM
– SRAM
– DRAM
– RDD-RAM
– SDRAM

• ROM
– ROM
– PROM
– EPROM
– EEPROM

70
Mother board

71
 Random access memory
• Sequential circuits all depend upon the presence of memory.
– A flip-flop can store one bit of information.
– A register can store a single “word,” typically 32-64 bits.
• Random access memory, or RAM, allows us to store even larger amounts
of data. We’ll see:
– The basic interface to memory.
– How you can implement static RAM chips hierarchically.
• This is the last piece we need to put together a computer!

72
 Static memory
• How can you implement the memory chip?
• There are many different kinds of RAM.
– We’ll start off discussing static memory, which is most commonly
used in caches and video cards.
– Later we mention a little about dynamic memory, which forms the
bulk of a computer’s main memory.
• Static memory is modeled using one latch for each bit of storage.
• Why use latches instead of flip flops?
– A latch can be made with only two NAND or two NOR gates, but a
flip-flop requires at least twice that much hardware.
– In general, smaller is faster, cheaper and requires less power.
– The tradeoff is that getting the timing exactly right is a pain.

73
 Starting with latches
• To start, we can use one latch to store each bit. A one-bit RAM cell is
shown here.

• Since this is just a one-bit memory, an ADRS input is not needed.

• Writing to the RAM cell:
– When CS = 1 and WR = 1, the latch control input will be 1.
– The DATA input is thus saved in the D latch.
• Reading from the RAM cell and maintaining the current contents:
– When CS = 1 or when WR = 0, the latch control input is also 0, so
the latch just maintains its present state.
– The current latch contents will appear on OUT.
74
• CS=0, C=0 , no changes
 My first RAM
• We can use these cells
to make a 4 x 1 RAM.
• Since there are four
words, ADRS is two bits.
• Each word is only one
bit, so DATA and OUT
are one bit each.
• Word selection is done
with a decoder attached
to the CS inputs of the
RAM cells. Only one cell
can be read or written
at a time.
• Notice that the outputs
are connected together
with a single line!

75
 Those funny triangles
• The triangle represents a three-state buffer.
• Unlike regular logic gates, the output can be one of three different
possibilities, as shown in the table.

• “Disconnected” means no output appears at all, in which case it’s safe to

connect OUT to another output signal.
• The disconnected value is also sometimes called high impedance or Hi-Z.

76
 Connecting three-state buffers together
• You can connect several three-state
buffer outputs together if you can
guarantee that only one of them is
enabled at any time.
• The easiest way to do this is to use a
decoder!
• If the decoder is disabled, then all the
three-state buffers will appear to be
disconnected, and OUT will also appear
disconnected.
• If the decoder is enabled, then exactly
one of its outputs will be true, so only
one of the tri-state buffers will be
connected and produce an output.
• The net result is we can save some wire
and gate costs. We also get a little more
flexibility in putting circuits together.

77
 Bigger and better
• Here is the 4 x 1 RAM
once again.
• How can we make a
“wider” memory with
more bits per word, like
maybe a 4 x 4 RAM?
• Duplicate the stuff in
the blue box!

78
 A 4 x 4 RAM
• DATA and OUT are now each four bits long, so you can read and write
four-bit words.

79
 Bigger RAMs from smaller RAMs
• We can use small RAMs as building blocks for making larger memories,
by following the same principles as in the previous examples.
• As an example, suppose we have some 64K x 8 RAMs to start with:
– 64K = 26 x 210 = 216, so there are 16 address lines.
– There are 8 data lines.

16
8 8

80
 Making a larger memory
• We can put four 64K x 8 chips
together to make a 256K x 8 8

memory.
16
• For 256K words, we need 18
address lines.
– The two most significant
address lines go to the
decoder, which selects one of
the four 64K x 8 RAM chips.
– The other 16 address lines are
shared by the 64K x 8 chips.
• The 64K x 8 chips also share WR
and DATA inputs.
• This assumes the 64K x 8 chips
have three-state outputs. 8

81
 Analyzing the 256K x 8 RAM
• There are 256K words of memory,
spread out among the four smaller 8

64K x 8 RAM chips.

16
• When the two most significant
bits of the address are 00, the
bottom RAM chip is selected. It
holds data for the first 64K
addresses.
• The next chip up is enabled when
the address starts with 01. It
holds data for the second 64K
addresses.
• The third chip up holds data for
the next 64K addresses.
• The final chip contains the data of
the final 64K addresses. 8

82
 Address ranges

16 11 1111 1111 1111 1111 (0x3ffff)

to
11 0000 0000 0000 0000 (0x30000)

10 1111 1111 1111 1111 (0x2ffff)

to
10 0000 0000 0000 0000 (0x20000)

01 1111 1111 1111 1111 (0x1ffff)

to
01 0000 0000 0000 0000 (0x10000)

00 1111 1111 1111 1111 (0x0ffff)

to
8 00 0000 0000 0000 0000 (0x00000)

83
 Making a wider memory
• You can also combine smaller chips to make wider memories, with the
same number of addresses but more bits per word.
• Here is a 64K x 16 RAM, created from two 64K x 8 chips.
– The left chip contains the most significant 8 bits of the data.
– The right chip contains the lower 8 bits of the data.
8 8

16

8 8

84
Input==output

85
 Other memories
• Last time we showed how to build arbitrarily-large static memories
from single-bit RAM cells.
• Today we’ll look at some other kinds of memories.
– Dynamic RAM is used for the bulk of computer memory.
– Read-only memories and PLAs are two “programmable logic devices,”
which can be considered as special types of memories.

86
 Dynamic memory in a nutshell
• Dynamic memory is built with capacitors.
– A stored charge on the capacitor represents a logical 1.
– No charge represents a logic 0.
• However, capacitors lose their charge after a few milliseconds. The
memory requires constant refreshing to recharge the capacitors.
(That’s what’s “dynamic” about it.)
• Dynamic RAMs tend to be physically smaller than static RAMs.
– A single bit of data can be stored with just one capacitor and one
transistor, while static RAM cells typically require 4-6 transistors.
– This means dynamic RAM is cheaper and denser—more bits can be
stored in the same physical area.

87
 SDRAM
• Synchronous DRAM, or SDRAM, is one of
the most common types of PC memory now.
• Memory chips are organized into “modules”
that are connected to the CPU via a 64-bit
(8-byte) bus.
• Speeds are rated in megahertz: PC66, PC100
and PC133 memory run at 66MHz, 100MHz
and 133MHz respectively.
• The memory bandwidth can be computed by
multiplying the number of transfers per
second by the size of each transfer.
– PC100 can transfer up to 800MB per
second (100MHz x 8 bytes/cycle).
– PC133 can get over 1 GB per second. (from amazon.com)

88
 DDR-RAM
• A newer type of memory is Double Data Rate, or DDR-RAM.
• It’s very similar to regular SDRAM, except data can be transferred on
both the positive and negative clock edges. For 100-133MHz buses, the
effective memory speeds appear to be 200-266MHz.
• This memory is confusingly called PC1600 and PC2100 RAM, because
– 200MHz x 8 bytes/cycle = 1600MB/s
– 266MHz x 8 bytes/cycle = 2100MB/s.
• DDR-RAM has lower power consumption, using 2.5V instead of 3.3V like
SDRAM. This makes it good for notebooks and other mobile devices.

89
 RDRAM
• Another new type of memory called RDRAM
is used in the Playstation 2 as well as some
Pentium 4 computers.
• The data bus is only 16 bits wide.
• But the memory runs at 400MHz, and data
can be transferred on both the positive and
negative clock edges.
– That works out to a maximum transfer
rate of 1.6GB per second.
– You can also implement two “channels”
of memory, resulting in up to 3.2GB/s of
bandwidth.

(from amazon.com)

90
 Dynamic vs. static memory
• In practice, dynamic RAM is used for a computer’s main memory, since
it’s cheap and you can pack a lot of storage into a small space.
– These days you can buy 256MB of memory for as little as $60.
– You can also load a system with 1.5GB or more of memory.
• The disadvantage of dynamic RAM is its speed.
– Transfer rates are 800MHz at best, which can be much slower than
the processor itself.
– You also have to consider latency, or the time it takes data to travel
from RAM to the processor.
• Real systems augment dynamic memory with small but fast sections of
static memory called caches.
– Typical processor caches range in size from 128KB to 320KB.
– That’s small compared to a 128MB main memory, but it’s enough to
significantly increase a computer’s overall speed.

91
 Read-only memory

2k x n ROM
k n
ADRS OUT
CS

• A read-only memory, or ROM, is a special kind of memory whose

contents cannot be easily modified.
– The WR and DATA inputs that we saw in RAMs are not needed.
– Data is stored onto a ROM chip using special hardware tools.
• ROMs are useful for holding data that never changes.
– Arithmetic circuits might use tables to speed up computations of
logarithms or divisions.
– Many computers use a ROM to store important programs that
should not be modified, such as the system BIOS.
– PDAs, game machines, cell phones, vending machines and other
electronic devices may also contain non-modifiable programs.
92
 Read Only Memory (ROM)

• Read but cannot write.

• Non volatile.
• Used for:
– Microprogramming.
– System programs.
– Whole programs in embedded systems.
– Library subroutines and function tables.
– Constants.

• Manufactured with the data wired into the chip.

– No room for mistakes.

93
 Memories and functions
• ROMs are actually combinational devices, not
sequential ones!
– You can’t store arbitrary data into a ROM,
so the same address will always contain the
same data.
– You can think of a ROM as a combinational
circuit that takes an address as input, and
produces some data as the output.
• A ROM table is basically just a truth table.
– The table shows what data is stored at each
ROM address.
– You can generate that data combinationally,
using the address as the input.

94
 Decoders
• We can already convert truth tables to circuits easily, with decoders.

• For example, you can think of this old circuit as a memory that “stores”
the sum and carry outputs from the truth table on the right.

95
 ROM setup
• ROMs are based on this decoder implementation of functions.
– A blank ROM just provides a decoder and several OR gates.
– The connections between the decoder and the OR gates are
“programmable,” so different functions can be implemented.
• To program a ROM, you just make the desired connections between the
decoder outputs and the OR gate inputs.

96
 ROM example
• Here are three functions, V2V1V0, implemented with an 8 x 3 ROM.
• Blue crosses (X) indicate connections between decoder outputs and OR
gates. Otherwise there is no connection.

A2
A1
A0

V2 = Σm(1,2,3,4) V1 = Σm(2,6,7) V0 = Σm(4,6,7)

97
 The same example again
• Here is an alternative presentation of the same 8 x 3 ROM, using
“abbreviated” OR gates to make the diagram neater.

A2
A1
A0

V2 =
Σm(1,2,3,4)
V1 =
Σm(2,6,7) V2 V1 V0
V0 =
Σm(4,6,7)

98
 Why is this a “memory”?
• This combinational circuit can be considered a read-only memory.
– It stores eight words of data, each consisting of three bits.
– The decoder inputs form an address, which refers to one of the
eight available words.
– So every input combination corresponds to an address, which is
“read” to produce a 3-bit data output.

A2
A1
A0

V2 V1 V0
99
 ROMs vs. RAMs
• There are some important differences between ROM and RAM.
– ROMs are “non-volatile”—data is preserved even without power. On
the other hand, RAM contents disappear once power is lost.
– ROMs require special (and slower) techniques for writing, so they’re
considered to be “read-only” devices.
• Some newer types of ROMs do allow for easier writing, although the
speeds still don’t compare with regular RAMs.
– MP3 players, digital cameras and other toys use CompactFlash,
Secure Digital, or MemoryStick cards for non-volatile storage.
– Many devices allow you to upgrade programs stored in “flash ROM.”

100
 Programmable logic arrays
• A ROM is potentially inefficient because it uses a decoder, which
generates all possible minterms. No circuit minimization is done.
• Using a ROM to implement an n-input function requires:
– An n-to-2n decoder, with n inverters and 2n n-input AND gates.
– An OR gate with up to 2n inputs.
– The number of gates roughly doubles for each additional ROM input.
• A programmable logic array, or PLA, makes the decoder part of the
ROM “programmable” too. Instead of generating all minterms, you can
choose which products (not necessarily minterms) to generate.

101
PLA

102
 PROM
Programmable read only memory

• Non volatile.
• Can be programmed - written into - only once.
• Programming is done electrically and can be done after manufacturing.
• Special equipment is needed for the programming process.
– Uses fuses instead of diodes.
• Fuses that need to be removed are “vaporized” during the
programming process using a high voltage pulse (10 – 30 V).

• CAN NOT BE ERASED.

103
 EPROM

Erasable programmable read only memory

• Uses floating-gate MOS transistors with insulating

material that changes behavior when exposed to ultraviolet
light.
– Programmed electrically and erased optically.
– Erasing can be repeated a relatively large but limited
number of times (~100,000 times).
– Erasing time ~20 minutes.

• Electrically read and written.

– Before writing, ALL cells must be erased by exposure
to ultraviolet light.

• Non volatile.
• More expensive than PROM.

104
 EEPROM

Electrical erasable read only memory

• EEPROM or E2PROM
• Erasable electrical address by address
Uses the same floating-gate transistors, except that the insulating
material is much thinner.
– Its operation can be inverted using voltage.
• Can be written to any time without erasing the previous contents.
– Only the bytes addressed are modified.
– Write takes a relatively long time (~100μsec/byte).
– Can be erased only about 10,000 times.

• Non volatile.
• Updatable in place.
• More expensive and less dense than EPROM.
105
 Flash Memory

• Called flash due to the speed of re-programming.

• Uses electrical erasure technology.
– An entire chip can be erased in 1-2 sec.
• Possible to erase only blocks of data.
– Does not provide byte level erasure.
• Uses one transistor per bit.
– Very high density.

• Cost is between EPROM and EEPROM.

• Non Volatile.

106
 Increasing the capacity of the memory
• Procedure:
– Find the capacity of the memory that can be used by the
microprocessor
– Find the capacity and the characteristics of the available memories
– Put these chips of memories in a table (ascending way)
– Find the range of addresses for each chip (beginning address and
final address)
– Find the expression of CS
– Connect with the microprocessor

…Example:

Connect the 4 chips of RAM: 8K bytes , 8K bytes, 16 K bytes, 32 K

bytes with the microprocessor 6800 (16 address bits).

107