Logic Gates (Decision-making Elements)
NOR Gates: The NOR gate has two or more input signals but only
one output signal. All inputs must be low to get a high output. In other
words, the NOR gate recognizes only the input word whose bits are all
0s.
Figure (a) shows the logical structure of a NOR gate, which is an OR gate
followed by an inverter. This is also originally called a NOT-OR gate.
Figure (b) above is the standard symbol for a NOR gate.
• All the inputs must be low to get a high output. if one input is low
and the other high, the output is low. And if both inputs are high, the
output is low. The following Truth Table summarizes the circuit action
of the NOR Gate.
• Incidentally, the Boolean equation for a 2-input
NOR gate is:
𝑌 = 𝐴 + 𝐵 (Read this as “Y equals NOT A OR B.”)
If you use this equation, remember that the ORing
is done first, then the inversion.
• 3-Input NOR Gate: Regardless of how many
inputs a NOR gate has, it is still logically equivalent to an OR gate
followed by an inverter. For instance, Fig. (a) below shows a 3-input
NOR gate. The 3 inputs are ORed, and the result is inverted. Therefore,
the Boolean equation is:
𝑌 = 𝐴 + 𝐵 + 𝐶 (Read this as “Y equals NOT A OR B OR C.”)
The analysis of Fig. (a) below goes like this. If all inputs are low, the
result of ORing is low; therefore,
the final output is high. If one
or more inputs are high, the
result of ORing is high; so the
final output is low.
• The following Table summarizes the action of a 3-input NOR gate.
• 4-Input NOR Gate: Figure (b) above is the
symbol for a 4-input NOR gate. The inputs are
Ored, and the result is inverted as given by the
Boolean equation is :
𝑌 =𝐴+𝐵+𝐶+𝐷
DE MORGAN’S 1st Theorem:
De Morgan first theorem says:
𝐴+𝐵 = 𝐴 𝐵
• The following Figure is a graphic summary of De Morgan’s first
theorem. A NOR gate & a bubbled AND gate are equivalent.
Considering the De Morgan 1st theorem,
and comparing Tables 1 and 2 indicates
that they’re identical. This means that
the two circuits are logically equivalent;
given the same inputs, the outputs are
the same. In other words, the circuits
given in the above Figure for elaborating
the De Morgan 1st theorem are
interchangeable.
• More than Two Inputs:
When 3 inputs are involved, De Morgan’s
1st theorem is written as:
𝐴 + 𝐵 + 𝐶 = 𝐴 𝐵 𝐶 …..(a)
For 4 inputs:
𝐴 + 𝐵 + 𝐶 + 𝐷 = 𝐴 𝐵 𝐶 𝐷 ….(b)
In both cases, the theorem says that the complement of a sum equals
the product of the complements.
Eq. (a) says that a 3- input NOR gate and a 3-input bubbled AND gate
are equivalent (see Fig. a above). Eq. (b) means that a 4-input nor gate
and a 4-input bubbled and gate are equivalent (see Fig. b above)
Example: Prove that the following Figs. (a) and (c) are equivalent.
Solution: The final NOR gate in Fig. (a) is equivalent to a bubbled AND
gate. This allows us to redraw the circuit as shown in Fig. (b). Double
inversion produces non-inversion; therefore, each double inversion in
Fig. (b) cancels out, leaving the
simplified circuit of Fig. (c).
Figs (a) and (c) are therefore
equivalent. Remember the
Idea that given a logic circuit,
you can replace any NOR gate by
a bubbled AND gate. Then any
double inversion (A pair of bubbles
in a series path) cancels out.
NAND Gates: The NAND gate has two or more input signals but only
one output signal. All inputs must be high to get a low output. In other
words, the NAND gate recognizes any input word with one or more 0s.
That is, one or more low inputs produce a high output.
Figure (a) shows the logical structure of a NAND gate, which is an AND
gate followed by an inverter. This is also originally called a NOT-AND
gate, the circuit is now referred to as a NAND gate.
Figure (b) above is the standard symbol for a NAND gate.
• Hence, if one or more inputs are low, the result of ANDing is low;
therefore, the final inverted output is high. Only when all inputs are
high does the ANDing produce a high signal; then the final output is
low. The following Truth Table summarizes the circuit action of the
NAND Gate.
• The Boolean equation for a 2-input NAND gate is:
𝑌 = 𝐴 𝐵 (Read this as “Y equals NOT AB.”)
If you use this equation, remember that the ANDing is
done first, then the inversion.
• 3-Input NAND Gate: Regardless of how many
inputs a NAND gate has, it is still logically equivalent to an AND gate
followed by an inverter. For example, Fig. (a) below shows a 3-input
NAND gate. The inputs are ANDed, and the product is inverted.
Therefore, the Boolean equation is:
𝑌 = 𝐴𝐵𝐶 (Read this as “Y equals NOT ABC.”)
Here is the analysis of Fig. (a) below goes like this. If one or more inputs
are low, the result of ANDing is low;
therefore, the final output is high.
If all inputs are high, the ANDing
gives a high signal; so the final
output is low.
• The following Table summarizes the action of a 3-input NAND gate.
• 4-Input NAND Gate: Figure (b) above is the symbol
for a 4-input NAND gate. The inputs are ANDed, and
the result is inverted as given by the Boolean
equation is :
𝑌 = 𝐴𝐵𝐶𝐷
DE MORGAN’S 2nd Theorem:
When two inputs are used, De Morgan 2nd theorem
says:
𝐴𝐵 = 𝐴 + 𝐵
• In words, the complement of a product equals the sum of the
complements. The following Figure is a graphic summary of De
Morgan’s second theorem. A NAND gate & a bubbled OR gate are
equivalent.
• More than Two Inputs:
When 3 inputs are involved, De
Morgan’s 2nd theorem is written as:
𝐴𝐵𝐶 = 𝐴 + 𝐵 + 𝐶 …..(c)
If 4 inputs are used:
𝐴𝐵𝐶𝐷 = 𝐴 + 𝐵 + 𝐶 + 𝐷 ….(d)
In both cases, the theorem says
that the complement of a product
equals the sum of the complements.
• Above Figure (a & b) is a visual summary of the second theorem.
Whether 3 or 4 inputs are involved, a NAND gate and a bubbled OR
gate are equivalent (interchangeable).
Example: Prove that the following Figs. (a) and (c) are equivalent.
Solution:
Replace the final NAND gate
in Fig. (a) by a bubbled OR
gate which gives Fig. (b).
The double inversions
cancel out, & leaving the
simplified circuit of Fig. (c).
Figure (a) and (c) are therefore
equivalent. Driven by the same
inputs, either circuit
produces the same output as the other.
Exclusive-OR Gates:
An OR gate recognizes words with one or more 1s. The exclusive-OR
gate is different; it recognizes only words that have an odd number of
1s.
Figure (a) shows one way to build an exclusive-OR gate, abbreviated
XOR. The upper AND gate forms the product 𝐴𝐵, and the lower AND
gate gives 𝐴𝐵. Therefore, the Boolean equation is:
𝑌 = 𝐴𝐵 + 𝐴𝐵
• Here’s what the circuit does.
In Fig. (a) two low inputs mean
both AND gates have low outputs;
so the final output is low. If A is low
& B is high, the upper AND gate has
a high output; therefore, the final
output is high. Likewise, a high A
and low B result in a final output that is high. If both inputs are high,
both AND gates have low outputs and the final output is low.
The following Table shows the truth table for a 2-input exclusive-OR
gate. The output is high when A or B is high but not both; this is why
the circuit is known as an exclusive-or gate.
• Logic Symbol & Boolean Sign for XOR Gate:
Figure (b) above is the standard symbol for a
2-input XOR gate. A word equation for this
Fig. is:
𝑌 = 𝐴 𝑋𝑂𝑅 𝐵
In Boolean algebra the sign stands for XOR
addition. So, above Eq. can be written as:
𝑌 = 𝐴 𝐴 𝐵 (Read this as “Y equals A XOR B.“)
Here’s a summary of the four possible XOR additions:
• In Case of 4-Inputs: In Fig. (a) below, the upper gate
produces 𝐴 𝐵 , while the lower gate gives C D. The final gate XORs
both of these sums to get:
𝑌 = (𝐴 𝐵) (𝐶 𝐷)
For instance, if A through C are low and D is high, then
☞ Using 2-input XOR gates as building blocks, we can make XOR
gates with any number of inputs.
The above Table summarizes the action 4-input XOR gate. Here is an
important property: each input word with an odd number of 1s
produces a 1 output.
Exclusive-NOR Gates:
The Exclusive-NOR gate, abbreviated XNOR, is logically equivalent to an
XOR gate followed by an inverter. For example, Fig. (a) shows a 2-input
XNOR gate. Figure (b) is an abbreviated way to draw the same circuit.
• Because of the inversion on the output side, the truth
table of an XNOR gate is the complement of an XOR
truth table. As shown in Table above, the output is high when the
inputs are the same. For this reason, the 2-input XNOR gate is ideally
suited for bit comparison , recognizing when two input bits are
identical.
Figure (a) below is the symbol for a 3-input XNOR gate, and Fig. (b) is
the 4-input XNOR gate. Because of the inversion on the output side,
these XNOR gates perform the complementary function of XOR gates.
☞ Instead of recognizing odd- parity words, XNOR gates recognize
even-parity words.
