4.

INTERFACING

CHAPTER 4
INTERFACING
4.1 Interfacing
Interfacing is a way to communicate and transfer information in either way without ending into
deadlocks. In our context it is a way of effective communication in real time.
This involves:
1) Addressing: The data sent by the master over a specified set of lines which enables just the
device for which it is meant.
2) Protocols: The literal meaning of protocol is a set of rules. Here it is a set of formal rules
describing how to transfer data, especially between two devices.
3) Arbitration: it specifies the process of generating the logic to select the bus connection over
different connected peripherals.

The interface is required:

• To speed synchronization between processor and peripherals since peripherals operates in
serial communication mode whereas processor operates in parallel mode.
• To manage the data format since the peripheral operates in bit or byte format where
memory and processor operates in word format. The word consists no of bytes.
• To maintain the energy of operation since processor and memory uses the semiconductor
and operates using electronic energy whereas peripherals are electromechanical.

4.2 Communication Basics

Figure: Simple Bus Architecture

Embedded System ©Er. Shiva Ramdam,2022 1

1. INTRODUCTION

Timing Diagram:
The most common methods for describing a communication protocol is with the timing
diagrams, A control and data signals in timing diagram are represented as:

As shown in the timing diagram for read protocol in Figure (a) the processor sets rd’/write to
low and places a valid address line addr for at least tsetup time before setting the enable line
high.
The diagram shows that the high enable line triggers the memory to put data on the data
wires after a time tread. Protocol may have sub protocols called as transaction or a bus cycle.
e.g. read and write and each may be several clock cycles.

For writing process, the processor sets rd’/write to high. The processor places a valid address on the
address line, places data on the data lines and activates enable by the time twrite.

Basic Protocol Concepts:

The basic protocol concepts are Actor, Data direction, Address, Time multiplexing and Control
methods:

1. Actor: Processor or memory involved in the data transfer. A protocol typically involves two
actors
a) Master: initiates the data transfer
b) Servant: Responds to the initiated request (Slave).
2. Data direction: Direction that the transferred data moves between the actors. Actor types are
independent of direction of data transfer.
3. Addresses: Special type of data used to indicate where regular data should go to come from. A
protocol often includes both an address and regular data. Addresses specify a location in
memory, a peripheral or a register within a peripheral.
4. Time Multiplexing: Time multiplexing means to share a single set of wires for a multiple piece of
data. In time multiplexing, multiple pieces of data are sent one at a time over the shared wire.
5. Control Methods: Control methods are schemas for initiating and ending the transfer. Two of
the most common methods are Strove and Hand shake.

2 Embedded System ©Er. Shiva Ramdam,2022

 4. INTERFACING

a) Strove: In Strove protocol, master uses one control line often called Request line to initiate
the data transfer. And the data transfer is considered to complete after fix interval time after
the initiation.
b) Handshake Protocol: The master uses a request line to initiate the transfer and servant used
an acknowledge line to inform the master when the data is ready.

4.3 Microprocessor Interfacing: IO Addressing, Interrupts, DMA

4.3.1 IO Addressing

The bus system establishes a connection between the processor and expansion devices and provides
a path for the flow of data. The system needs a way to track and control which device is sending data
and which device is receiving; without such a means-the bus system-there would be complete chaos.
The first step to establish orderly communication is to assign a unique I/O address to each device.
A microprocessor may have tens or hundreds of pins, consisting of the control pins (clock, reset) and
many of the other pins are used to communicate data to and from the microprocessor, which we call
processor I/O. There are two common methods for using pins to support I/O: ports and system
buses.

a) Port Based IO (Parallel IO)

It is also called Parallel IO. In Port-based IO, a port can be directly read and written by the
processor instruction like any other register in microprocessor. The port is usually connected to
a dedicated register.
One or more processor ports can be interfaced to a parallel IO peripheral extending total
number of ports available for IO. In figure b, 4 ports have been extended to 6.

Embedded System ©Er. Shiva Ramdam,2022 3

1. INTRODUCTION

b) Bus Based IO

In bus-based IO, a microprocessor has a set of address, data and control ports corresponding to
the bus line and uses the bus to access the memory as well as peripherals. The microprocessor
has the bus protocol built into its hardware. A single instruction carries out the read or write,
over the bus.
There are two methods for the microprocessor to communicate with the peripherals in bus-
based IO: Memory mapped IO and Standard IO.

i) Memory Mapped IO

Memory mapped IO is a method to perform input/output (I/O) operations

between the processor and peripheral devices that uses one address space for
memory and IO devices. This technique shares the same memory location (memory),
i.e., the processor and IO devices are mapped using the memory address. Memory-
mapped I/O uses the same
address bus to address both
memory and I/O devices,
and the CPU instructions
used are same for accessing
the memory and also
accessing devices.
• Devices and memory
share an address
space
• I/O looks just like memory read/write
• No special command for I/O
• Large selection of memory access commands available

ii) Standard IO

Also called Isolate IO. It uses separate

instruction classes to access primary
memory and device memory. In this case,
I/O devices have separate address space
either by separate I/O pin on CPU or by
entire separate bus. As it separates general
memory addresses with I/O devices, it is
called isolated I/O.
• Separate address spaces

4 Embedded System ©Er. Shiva Ramdam,2022

 4. INTERFACING

• Need I/O or memory select lines

• Special commands for I/O
• More efficient than Memory mapped IO.

4.3.2 Interrupts

• Interrupt is signals send by an external device to the processor, to request the processor to
perform a particular task or work.
• Mainly in the microprocessor-based system, the interrupts are used for data transfer
between the peripheral and the microprocessor.
• The processor will check the interrupts always at the 2nd T-state of last machine cycle.
• If there is any interrupt, it accepts the interrupt and send the INTA (active low) signal to the
peripheral.
• The vectored address of particular interrupt is stored in program counter.
• The processor executes an interrupt service routine (ISR) addressed in program counter.

Types of Interrupts
Interrupts can be broadly classified as
• Hardware Interrupts: These are interrupts caused by the connected devices.
• Software Interrupts: These are interrupts deliberately introduced by software instructions
to generate user defined exceptions
• Trap: These are interrupts used by the processor alone to detect any exception such as
divide by zero.
Depending on the service the interrupts also can be classified as
• Fixed interrupt
o Address of the ISR built into microprocessor, cannot be changed
o Either ISR stored at address or a jump to actual ISR stored if not enough bytes
available
• Vectored interrupt
o Peripheral must provide the address of the ISR
o Common when microprocessor has multiple peripherals connected by a system bus

4.3.3 DMA (Dynamic Memory Access)

The data being accumulated in a peripheral should be first stored in memory being processed by a
program running on the microprocessor. Such temporary storage od data is a waiting process called
Buffering.
We could write a simple ISR on microprocessor such that the peripheral device would interrupt the
microprocessor whenever it had data to be stored in memory. The ISR simply transfers data from the
peripheral to the memory and then resume running its application. The storing and restoring of the
stare may consume many clock cycles and it is somewhat inefficient.
The IO method of DMA eliminates these inefficiencies. In DMA, we use a separate single purpose
processor called DMA controller whose sole purpose id to transfer data between memories and
peripherals without intervening the processor.
Direct Memory Access is a technique for transferring data within main memory and external device
without passing it through the CPU. DMA is a way to improve processor activity and I/O transfer rate
by taking-over the job of transferring data from processor, and letting the processor to do other
tasks.

Embedded System ©Er. Shiva Ramdam,2022 5

1. INTRODUCTION

Advantages:
• allows a peripheral device to read from/write to memory without going through the
microprocessor.
• allows for faster processing since the processor can be working on something else while the
peripheral can be populating memory.
Disadvantages:
• requires a separate DMA controller to carry out the operation, which increases the cost of
the system
• cache coherence problems

4.4 Arbitration
Bus Arbitration refers to the process by which the current bus master accesses and then leaves the
control of the bus and passes it to another bus requesting processor unit. The controller that has
access to a bus at an instance is known as a Bus master.
A conflict may arise if the number of DMA controllers or other controllers or processors try to access
the common bus at the same time, but access can be given to only one of those. Only one processor
or controller can be Bus master at the same point in time. To resolve these conflicts, the Bus
Arbitration procedure is implemented to coordinate the activities of all devices requesting memory
transfers. The selection of the bus master must take into account the needs of various devices by
establishing a priority system for gaining access to the bus. The Bus Arbiter decides who would
become the current bus master.
The method can be divided into following.
• Priority Arbiter
• Daisy Chain Arbiter

i) Priority Arbiter
Peripheral devices are connected with the processor and a priority arbiter is attached with
processor. The arbiter selects the connection of peripheral with bus on the basis of fixed priority
basis or round robin approach.
If arbiter selects the peripheral device in fixed priority basis, then such arbiter is called Fixed priority
arbiter.
The round robin arbiter assigns a bus connection with peripheral devices for a fixed interval of time
and transfer to next connected device. The service taken by a device gets bus after a complete
round.
For example:

Let us assume that the Priority of the devices are Device1 > Device 2 ………………..then priority arbiter
works as:
1. The Processor is executing its program.

6 Embedded System ©Er. Shiva Ramdam,2022

 4. INTERFACING

2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts
Ireq2.
3. Priority arbiter sees at least one Ireq input asserted, so asserts Int.
4. Processor stops executing its program and stores its state.
5. Processor asserts Inta.
6. Priority arbiter asserts Iack1 to acknowledge Peripheral1.
7. Peripheral1 puts its interrupt address vector on the system bus
8. Processor jumps to the address of ISR read from data bus, ISR executes and returns (and
completes handshake with arbiter).
Thus, in case of simultaneous interrupts the device with the highest priority will be served.

ii) Daisy Chain Arbiter

In this case, the peripherals needing interrupt service are connected in a chain as shown in figure
below. The requests are chained and hence, any device interrupting shall be transmitted to the CPU
in a chain. The daisy-chaining method involves connecting all the devices that can request an
interrupt in a serial manner. This configuration is governed by the priority of the devices. The device
with the highest priority is placed first followed by the second highest priority device and so on. The
given figure depicts this arrangement.

Figure: Working of Daisy Chain Arbitration

There is an interrupt request line which is common to all the devices and goes into the CPU.
1. When no interrupts are pending, the line is in HIGH state. But if any of the devices raises an
interrupt (INT), it places the interrupt request line in the LOW state.
2. The CPU acknowledges this interrupt request from the line and then enables the interrupt
acknowledge (INT ACK) line in response to the request.
3. This signal is received at the PI (Priority in) input of device 1.
4. If the device has not requested the interrupt, it passes this signal to the next device through
its PO (priority out) output. (PI = 1 & PO = 1)
5. However, if the device had requested the interrupt, (PI =1 & PO = 0)
• The device consumes the acknowledge signal and block its further use by placing 0 at its
PO (priority out) output.
• The device then proceeds to place its interrupt vector address (VAD) into the data bus of
CPU.
• The device puts its interrupt request signal in HIGH state to indicate its interrupt has
been taken care of.
6. If a device gets 0 at its PI input, it generates 0 at the PO output to tell other devices that
acknowledge signal has been blocked. (PI = 0 & PO = 0)

Embedded System ©Er. Shiva Ramdam,2022 7

1. INTRODUCTION

Hence, the device having PI = 1 and PO = 0 is the highest priority device that is requesting an
interrupt. Therefore, by daisy chain arrangement we have ensured that the highest priority
interrupt gets serviced first and have established a hierarchy.

iii) Network-Oriented Arbitration:

Many Embedded systems contain multiple microprocessors communicating via a shared bus.
Such a bus is sometimes called a network. Arbitration in such cases is typically built right into the
bus protocol, since the bus serves as the only connection among the microprocessors.
A key feature of such a connection is that a processor about to write to the bus has no way of
knowing whether another processor is about to simultaneously write to the bus. Because of the
relatively long wires and high capacitances of such buses, a processor may write many bits of
data before those bits appear at another processor.
For example, Ethernet and I2C (Inter-IC) use a method in which multiple processors may write to
the bus simultaneously, resulting in a collision and causing any data on the bus to be corrupted.
The processors detect this collision, stop transmitting their data, wait for some time, and then
try transmitting again. The protocols must ensure that the contending processors do not start
sending again at the same time, or must at lease use statistical methods that make the chances
of them sending again at the same time small.
As another example, the CAN (Controller Area Network) bus uses a clever address encoding
scheme such that if two addresses are written simultaneously by different processors using the
bus. The higher-priority address will override the lower-priority one. Each processor that is
writing the bus also checks the bus, if the address it is writing does not appear, then that
processor realizes that a higher-priority transfer is taking place and so that processor stops
writing the bus.

4.5 Multilevel Bus Architecture

A microprocessor-base embedded system will have numerus types of communication that must take
place, varying in their frequencies and speed requirements. The most frequent and high-speed
communications will likely be between the microprocessor and its memories. Less frequent
communications, requiring less speed, will be between the microprocessor and its peripherals, like a
UART. We could try to implement a single high-speed bus for all the communications, but this
approach has several disadvantages.
• First, it requires each peripheral to have a high-speed bus interface. Since a peripheral may
not need such high-speed communication, having such an interface may result in extra
gates, power consumption and cost.
• Second, since a high-speed bus will be very processor-specific, a peripheral with an interface
to that bus may not be very portable.
• Third, having too many peripherals on the bus may result in a slower bus.
Therefore, we often design systems with two levels of buses; a high-speed processor local bus and a
lower-speed peripheral bus, as illustrated in figure below.

8 Embedded System ©Er. Shiva Ramdam,2022

 4. INTERFACING

Figure 6.23: A two-level bus architecture

• The processor-local bus typically connects the microprocessor, cache, memory, controllers
and certain high-speed co-processors, and its processor specific. It is usually wide, as wide as
memory word.
• The peripheral bus connects those processors that do not have fast processor local bus
access as a top priority, but rather emphasize portability, low power, or low gate count. The
peripheral bus is typically an industry standard bus, such as ISA or PCI, thus, supporting
portability of the peripherals. It is often narrower and/or slower than a processor-local bus,
thus requiring fewer pins, fewer gates and lower power for interfacing.
• A bridge connects the two buses. A bridge is a single-purpose processor that converts
communication on one bus to communication on another bus. For example, the
microprocessor may generate a read on the processor local bus with and address
corresponding to a peripheral. The bridge detects that the address corresponds to a
peripheral, and thus it generates a read on the peripheral bus. After receiving the data, the
bridge sends that data to the microprocessor. The microprocessor thus need not even know
that a bridge exists- it receives the data, albeit a few cycles later, as if the peripheral wee on
the processor local bus.
A three-level bus hierarchy is also possible, as proposed by the VSI alliance. The first level is the
processor local bus, the second level a system bus, and the third level a peripheral bus. The system
bus would be a high-speed bus, but would offload much of the traffic from the processor local bus. It
may be beneficial in complex systems with numerous coprocessors.

4.6 Advance Communication Principles

Communication can take place over a number of different types of media, such as a single wire, a set
of wires, radio waves, or infrared waves. we refer to the medium that is used to carry data from one
device to another as the physical layer. Depending on the protocol, we may refer to an actor as a
device or node, in either case, a device is simply a processor that uses the physical layer to send or
receive data to and from another device.
Here we discuss a general description of serial communication, parallel communication, and wireless
communication, layering, error detection and correction.

a) Parallel Communication:

Figure: Parallel Communication

• Parallel communication takes place when the physical layer is capable of carrying multiple
bits of data from one device to another.
• The data bus is composed of multiple data wires, each wire carries one of the bits.

Embedded System ©Er. Shiva Ramdam,2022 9

1. INTRODUCTION

• For parallel communication, binary data of 0s and 1s are organized into a group of n bits
each, And for that n bits, we need n wires, By grouping, we can send n-bits at a time. It is
suitable for short distances.
• Used when connecting devices reside on the same IC, or the device are on the same circuit
board.
• Advantages: high speed and high data rate
• Disadvantages: high cost due to more communication channel.

b) Serial Communication:

Figure: serial Communication

• Serial communication involves a physical layer that carries one bit of data at a time.
• The data bus is composed of a single data wire, with control and possibly power wires,
running from one device to another.
• When data is to be sent, the sender first transmits a start bit. This start bit merely signals the
receiver to wakeup and start receiving data.
• The start bit is followed by N data bits, and a stop bit.
• Advantage: low cost and suitable for long distance communication
• Disadvantage: low speed and low data rate.

c) Wireless Communication:
• Wireless communication eliminates the need for devices to be physically connected in order
to communicate.
• The physical layers used in the wireless communication is typically either an Infrared (IR)
channel or a Radio Frequency (RF) channel.

Infrared:
o It uses electromagnetic wave frequencies that are just below the visible light spectrum,
thus undetectable by human eye.
o IR wave are generated by Infrared diode and detected by IR transistor.
o The IR diode turn ON/OFF to send 1s or 0s.
o The IR transistor detects 1s when current flows through it and 0s otherwise.
o It is relatively cheap to build IR transmitters and receivers.
o It needs LOS communication, and the communication range is very restricted.

Radio Frequency:
o It uses electromagnetic wave frequencies in the radio spectrum.
o The RF transmitter needs to use analog circuitry and an antenna to transmit data. And so
does the receiver need.
o RF does not need LOS communication, and thus longer distance communication
depends on the transmission power used by the transmitter.

10 Embedded System ©Er. Shiva Ramdam,2022

 4. INTERFACING

d) Layering:
• Layering is a hierarchical organization of communication protocol where lower levels of the
protocol provides services to the higher levels.
• The lowest level od the communication protocol consist of the physical layer, whereas, the
highest level consists of the application layer. In between then are the other layers.
• An example of layering is the OSI protocol and TCP/IP protocol.

e) Error Detection and Correction:

• Error detection is the ability of a receiver to detect errors that may occur during the
transmission of a data word or packet.
• Possibly there are two errors: bit error and burst error.
• Bit error refers to the single bit error.
• Burst error refers to the multiple bit error.
• Error correction is the ability of a receiver and transmitter to cooperate in order to correct
the problem.
• Parity error detection and checksum error detection are the most common error detection
algorithms used.

4.7 Exam Questions:

1) Differentiate Interrupt Driven IO suing fixed and vectored interrupt. [2021 Fall]
2) What are the advantages of interrupt over DMA? Explain the operation of peripheral to
memory transfer with DMA. [2021 Fall]
3) Define Arbitration. Explain daisy chain arbitration with necessary diagram. [2020 Fall, 2017
Spring]
4) What are the methods that can be employed to find the address of Interrupt Service
Routine (ISR) Discuss a generalized DMA process? [2019 Fall]
5) Explain Daisy-chain arbitration in detail. What is the significance of Multilevel bus
architecture? [2019 Fall]
6) Define Arbitration. Explain in brief about daisy chain and Network-oriented Arbitration.
[2018 Spring, 2017 Fall]
7) Why we need DMA? Explain the working principle of DMA. [2018 Fall]
8) Compare and contrast bus-based IO and port-base IO. [2018 fall]
9) What is DMA? Why such circuitry is needed? Explain with its block diagram. [2017 spring]
10) Explain the benefits that an interrupt address table has over the fixed and vectored
interrupt methods. [2017 Fall]
11) What is Arbitration? Explain the steps used in Daisy-chain arbitration with a block diagram.
[2016 Fall]
12) Explain vectored Interrupt with a neat diagram. [2016 fall]
13) What is interrupt? Explain the steps used in data transfer using vector interrupt along wit
its flowchart. [2016 Spring]
14) Explain any two arbitration techniques that implemented to communicate with peripheral
devices from the microprocessor. [2015 spring]
15) What is the main difference between standard IO and Memory mapped IO? [2015 Spring]
16) Why is interrupt important? Compare and contrast interrupt and DMA. [2015 Spring]
17) Why DMA is used? Explain in detail. [2015 Fall]
18) Describe wireless communication protocols used in embedded system. [2015 spring]
19) Whys and interrupt s important? Discuss the methods to serve interrupts. [2014 spring]
20) Explain the differences between port-based IO and bus-based IO. Also explain the benefits
that an interrupt address table has over fixed and vectored interrupt methods. [2014 Fall]
21) Write Short notes:
Embedded System ©Er. Shiva Ramdam,2022 11
1. INTRODUCTION

a) Arbitration [2021 Fall]

b) Multilevel Bus Architecture [2020 Fall, 2019 Fall]
c) DMA [2019 Spring, 2018 Spring, 2016 Fall]
d) Clocking communication and Task synchronization [2016 Fall]
e) Wireless communication [2014 spring]
f) Daisy chain arbitration [2014 Fall]

***

12 Embedded System ©Er. Shiva Ramdam,2022